1 /* 2 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 3 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <clk-uclass.h> 10 #include <dm.h> 11 #include <stm32_rcc.h> 12 13 #include <asm/io.h> 14 #include <asm/arch/stm32.h> 15 #include <asm/arch/stm32_pwr.h> 16 17 #include <dt-bindings/mfd/stm32f7-rcc.h> 18 19 #define RCC_CR_HSION BIT(0) 20 #define RCC_CR_HSEON BIT(16) 21 #define RCC_CR_HSERDY BIT(17) 22 #define RCC_CR_HSEBYP BIT(18) 23 #define RCC_CR_CSSON BIT(19) 24 #define RCC_CR_PLLON BIT(24) 25 #define RCC_CR_PLLRDY BIT(25) 26 #define RCC_CR_PLLSAION BIT(28) 27 #define RCC_CR_PLLSAIRDY BIT(29) 28 29 #define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0) 30 #define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6) 31 #define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16) 32 #define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24) 33 #define RCC_PLLCFGR_PLLSRC BIT(22) 34 #define RCC_PLLCFGR_PLLM_SHIFT 0 35 #define RCC_PLLCFGR_PLLN_SHIFT 6 36 #define RCC_PLLCFGR_PLLP_SHIFT 16 37 #define RCC_PLLCFGR_PLLQ_SHIFT 24 38 39 #define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4) 40 #define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10) 41 #define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13) 42 #define RCC_CFGR_SW0 BIT(0) 43 #define RCC_CFGR_SW1 BIT(1) 44 #define RCC_CFGR_SW_MASK GENMASK(1, 0) 45 #define RCC_CFGR_SW_HSI 0 46 #define RCC_CFGR_SW_HSE RCC_CFGR_SW0 47 #define RCC_CFGR_SW_PLL RCC_CFGR_SW1 48 #define RCC_CFGR_SWS0 BIT(2) 49 #define RCC_CFGR_SWS1 BIT(3) 50 #define RCC_CFGR_SWS_MASK GENMASK(3, 2) 51 #define RCC_CFGR_SWS_HSI 0 52 #define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 53 #define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 54 #define RCC_CFGR_HPRE_SHIFT 4 55 #define RCC_CFGR_PPRE1_SHIFT 10 56 #define RCC_CFGR_PPRE2_SHIFT 13 57 58 #define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6) 59 #define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16) 60 #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 61 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 62 #define RCC_PLLSAICFGR_PLLSAIP_4 BIT(17) 63 #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26) 64 #define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29) 65 66 #define RCC_DCKCFGRX_CK48MSEL BIT(27) 67 #define RCC_DCKCFGRX_SDMMC1SEL BIT(28) 68 #define RCC_DCKCFGR2_SDMMC2SEL BIT(29) 69 70 #define RCC_APB2ENR_SAI1EN BIT(22) 71 72 /* 73 * RCC AHB1ENR specific definitions 74 */ 75 #define RCC_AHB1ENR_ETHMAC_EN BIT(25) 76 #define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26) 77 #define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27) 78 79 /* 80 * RCC APB1ENR specific definitions 81 */ 82 #define RCC_APB1ENR_TIM2EN BIT(0) 83 #define RCC_APB1ENR_PWREN BIT(28) 84 85 /* 86 * RCC APB2ENR specific definitions 87 */ 88 #define RCC_APB2ENR_SYSCFGEN BIT(14) 89 90 enum periph_clock { 91 SYSCFG_CLOCK_CFG, 92 TIMER2_CLOCK_CFG, 93 STMMAC_CLOCK_CFG, 94 }; 95 96 struct stm32_clk_info stm32f4_clk_info = { 97 /* 180 MHz */ 98 .sys_pll_psc = { 99 .pll_m = 8, 100 .pll_n = 360, 101 .pll_p = 2, 102 .pll_q = 8, 103 .ahb_psc = AHB_PSC_1, 104 .apb1_psc = APB_PSC_4, 105 .apb2_psc = APB_PSC_2, 106 }, 107 .has_overdrive = false, 108 .v2 = false, 109 }; 110 111 struct stm32_clk_info stm32f7_clk_info = { 112 /* 200 MHz */ 113 .sys_pll_psc = { 114 .pll_m = 25, 115 .pll_n = 400, 116 .pll_p = 2, 117 .pll_q = 8, 118 .ahb_psc = AHB_PSC_1, 119 .apb1_psc = APB_PSC_4, 120 .apb2_psc = APB_PSC_2, 121 }, 122 .has_overdrive = true, 123 .v2 = true, 124 }; 125 126 struct stm32_clk { 127 struct stm32_rcc_regs *base; 128 struct stm32_pwr_regs *pwr_regs; 129 struct stm32_clk_info *info; 130 }; 131 132 static int configure_clocks(struct udevice *dev) 133 { 134 struct stm32_clk *priv = dev_get_priv(dev); 135 struct stm32_rcc_regs *regs = priv->base; 136 struct stm32_pwr_regs *pwr = priv->pwr_regs; 137 struct pll_psc sys_pll_psc = priv->info->sys_pll_psc; 138 u32 pllsaicfgr = 0; 139 140 /* Reset RCC configuration */ 141 setbits_le32(®s->cr, RCC_CR_HSION); 142 writel(0, ®s->cfgr); /* Reset CFGR */ 143 clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON 144 | RCC_CR_PLLON | RCC_CR_PLLSAION)); 145 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */ 146 clrbits_le32(®s->cr, RCC_CR_HSEBYP); 147 writel(0, ®s->cir); /* Disable all interrupts */ 148 149 /* Configure for HSE+PLL operation */ 150 setbits_le32(®s->cr, RCC_CR_HSEON); 151 while (!(readl(®s->cr) & RCC_CR_HSERDY)) 152 ; 153 154 setbits_le32(®s->cfgr, (( 155 sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) 156 | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) 157 | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); 158 159 /* Configure the main PLL */ 160 setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */ 161 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK, 162 sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT); 163 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK, 164 sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT); 165 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK, 166 ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); 167 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, 168 sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT); 169 170 /* Configure the SAI PLL to get a 48 MHz source */ 171 pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 | 172 RCC_PLLSAICFGR_PLLSAIP_4; 173 pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT; 174 writel(pllsaicfgr, ®s->pllsaicfgr); 175 176 /* Enable the main PLL */ 177 setbits_le32(®s->cr, RCC_CR_PLLON); 178 while (!(readl(®s->cr) & RCC_CR_PLLRDY)) 179 ; 180 181 if (priv->info->v2) { /*stm32f7 case */ 182 /* select PLLSAI as 48MHz clock source */ 183 setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL); 184 185 /* select 48MHz as SDMMC1 clock source */ 186 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL); 187 188 /* select 48MHz as SDMMC2 clock source */ 189 clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL); 190 } else { /* stm32f4 case */ 191 /* select PLLSAI as 48MHz clock source */ 192 setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL); 193 194 /* select 48MHz as SDMMC1 clock source */ 195 clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL); 196 } 197 198 /* Enable the SAI PLL */ 199 setbits_le32(®s->cr, RCC_CR_PLLSAION); 200 while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY)) 201 ; 202 203 setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN); 204 205 if (priv->info->has_overdrive) { 206 /* 207 * Enable high performance mode 208 * System frequency up to 200 MHz 209 */ 210 setbits_le32(&pwr->cr1, PWR_CR1_ODEN); 211 /* Infinite wait! */ 212 while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY)) 213 ; 214 /* Enable the Over-drive switch */ 215 setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN); 216 /* Infinite wait! */ 217 while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY)) 218 ; 219 } 220 221 stm32_flash_latency_cfg(5); 222 clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); 223 setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL); 224 225 while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) != 226 RCC_CFGR_SWS_PLL) 227 ; 228 /* gate the SAI clock, needed for MMC 1&2 clocks */ 229 setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN); 230 231 return 0; 232 } 233 234 static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, 235 u32 sysclk) 236 { 237 struct stm32_rcc_regs *regs = priv->base; 238 u16 pllq, pllm, pllsain, pllsaip; 239 bool pllsai; 240 241 pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK) 242 >> RCC_PLLCFGR_PLLQ_SHIFT; 243 244 if (priv->info->v2) /*stm32f7 case */ 245 pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; 246 else 247 pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; 248 249 if (pllsai) { 250 /* PLL48CLK is selected from PLLSAI, get PLLSAI value */ 251 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); 252 pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK) 253 >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); 254 pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK) 255 >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); 256 return ((CONFIG_STM32_HSE_HZ / pllm) * pllsain) / pllsaip; 257 } 258 /* PLL48CLK is selected from PLLQ */ 259 return sysclk / pllq; 260 } 261 262 static unsigned long stm32_clk_get_rate(struct clk *clk) 263 { 264 struct stm32_clk *priv = dev_get_priv(clk->dev); 265 struct stm32_rcc_regs *regs = priv->base; 266 u32 sysclk = 0; 267 u32 shift = 0; 268 u16 pllm, plln, pllp; 269 /* Prescaler table lookups for clock computation */ 270 u8 ahb_psc_table[16] = { 271 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 272 }; 273 u8 apb_psc_table[8] = { 274 0, 0, 0, 0, 1, 2, 3, 4 275 }; 276 277 if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) == 278 RCC_CFGR_SWS_PLL) { 279 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); 280 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) 281 >> RCC_PLLCFGR_PLLN_SHIFT); 282 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) 283 >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); 284 sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; 285 } else { 286 return -EINVAL; 287 } 288 289 switch (clk->id) { 290 /* 291 * AHB CLOCK: 3 x 32 bits consecutive registers are used : 292 * AHB1, AHB2 and AHB3 293 */ 294 case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI): 295 shift = ahb_psc_table[( 296 (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK) 297 >> RCC_CFGR_HPRE_SHIFT)]; 298 return sysclk >>= shift; 299 /* APB1 CLOCK */ 300 case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8): 301 shift = apb_psc_table[( 302 (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK) 303 >> RCC_CFGR_PPRE1_SHIFT)]; 304 return sysclk >>= shift; 305 /* APB2 CLOCK */ 306 case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC): 307 /* 308 * particular case for SDMMC1 and SDMMC2 : 309 * 48Mhz source clock can be from main PLL or from 310 * SAI PLL 311 */ 312 switch (clk->id) { 313 case STM32F7_APB2_CLOCK(SDMMC1): 314 if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL) 315 /* System clock is selected as SDMMC1 clock */ 316 return sysclk; 317 else 318 return stm32_clk_pll48clk_rate(priv, sysclk); 319 break; 320 case STM32F7_APB2_CLOCK(SDMMC2): 321 if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL) 322 /* System clock is selected as SDMMC2 clock */ 323 return sysclk; 324 else 325 return stm32_clk_pll48clk_rate(priv, sysclk); 326 break; 327 } 328 329 shift = apb_psc_table[( 330 (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK) 331 >> RCC_CFGR_PPRE2_SHIFT)]; 332 return sysclk >>= shift; 333 default: 334 pr_err("clock index %ld out of range\n", clk->id); 335 return -EINVAL; 336 } 337 } 338 339 static int stm32_clk_enable(struct clk *clk) 340 { 341 struct stm32_clk *priv = dev_get_priv(clk->dev); 342 struct stm32_rcc_regs *regs = priv->base; 343 u32 offset = clk->id / 32; 344 u32 bit_index = clk->id % 32; 345 346 debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n", 347 __func__, clk->id, offset, bit_index); 348 setbits_le32(®s->ahb1enr + offset, BIT(bit_index)); 349 350 return 0; 351 } 352 353 void clock_setup(int peripheral) 354 { 355 switch (peripheral) { 356 case SYSCFG_CLOCK_CFG: 357 setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_SYSCFGEN); 358 break; 359 case TIMER2_CLOCK_CFG: 360 setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); 361 break; 362 case STMMAC_CLOCK_CFG: 363 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_EN); 364 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_RX_EN); 365 setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_ETHMAC_TX_EN); 366 break; 367 default: 368 break; 369 } 370 } 371 372 static int stm32_clk_probe(struct udevice *dev) 373 { 374 struct ofnode_phandle_args args; 375 int err; 376 377 debug("%s\n", __func__); 378 379 struct stm32_clk *priv = dev_get_priv(dev); 380 fdt_addr_t addr; 381 382 addr = dev_read_addr(dev); 383 if (addr == FDT_ADDR_T_NONE) 384 return -EINVAL; 385 386 priv->base = (struct stm32_rcc_regs *)addr; 387 388 switch (dev_get_driver_data(dev)) { 389 case STM32F4: 390 priv->info = &stm32f4_clk_info; 391 break; 392 case STM32F7: 393 priv->info = &stm32f7_clk_info; 394 break; 395 default: 396 return -EINVAL; 397 } 398 399 if (priv->info->has_overdrive) { 400 err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, 401 &args); 402 if (err) { 403 debug("%s: can't find syscon device (%d)\n", __func__, 404 err); 405 return err; 406 } 407 408 priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node); 409 } 410 411 configure_clocks(dev); 412 413 return 0; 414 } 415 416 static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) 417 { 418 debug("%s(clk=%p)\n", __func__, clk); 419 420 if (args->args_count != 2) { 421 debug("Invaild args_count: %d\n", args->args_count); 422 return -EINVAL; 423 } 424 425 if (args->args_count) 426 clk->id = args->args[1]; 427 else 428 clk->id = 0; 429 430 return 0; 431 } 432 433 static struct clk_ops stm32_clk_ops = { 434 .of_xlate = stm32_clk_of_xlate, 435 .enable = stm32_clk_enable, 436 .get_rate = stm32_clk_get_rate, 437 }; 438 439 U_BOOT_DRIVER(stm32fx_clk) = { 440 .name = "stm32fx_rcc_clock", 441 .id = UCLASS_CLK, 442 .ops = &stm32_clk_ops, 443 .probe = stm32_clk_probe, 444 .priv_auto_alloc_size = sizeof(struct stm32_clk), 445 .flags = DM_FLAG_PRE_RELOC, 446 }; 447