1Rockchip LVDS interface
2------------------
3
4Required properties:
5- compatible: "rockchip,rk3288-lvds";
6
7- reg: physical base address of the controller and length
8	of memory mapped region.
9- clocks: must include clock specifiers corresponding to entries in the
10	clock-names property.
11- clock-names: must contain "pclk_lvds"
12
13- rockchip,grf: phandle to the general register files syscon
14
15- rockchip,data-mapping: should be <LVDS_FORMAT_VESA> or  <LVDS_FORMAT_JEIDA>,
16	This describes how the color bits are laid out in the
17	serialized LVDS signal.
18- rockchip,data-width : should be <18> or <24>;
19- rockchip,output: should be <LVDS_OUTPUT_RGB>, <LVDS_OUTPUT_SINGLE> or
20	<LVDS_OUTPUT_DUAL>, This describes the output face.
21
22- display-timings : described by
23	doc/devicetree/device-tree-bindings/video/display-timing.txt.
24
25Example:
26	lvds: lvds@ff96c000 {
27		compatible = "rockchip,rk3288-lvds";
28		reg = <0xff96c000 0x4000>;
29		clocks = <&cru PCLK_LVDS_PHY>;
30		clock-names = "pclk_lvds";
31		pinctrl-names = "default";
32		pinctrl-0 = <&lcdc0_ctl>;
33		rockchip,grf = <&grf>;
34		status = "disabled";
35		ports {
36			#address-cells = <1>;
37			#size-cells = <0>;
38
39			lvds_in: port@0 {
40				reg = <0>;
41
42				#address-cells = <1>;
43				#size-cells = <0>;
44
45				lvds_in_vopb: endpoint@0 {
46					reg = <0>;
47					remote-endpoint = <&vopb_out_lvds>;
48				};
49				lvds_in_vopl: endpoint@1 {
50					reg = <1>;
51					remote-endpoint = <&vopl_out_lvds>;
52				};
53			};
54		};
55	};
56
57	&lvds {
58		rockchip,data-mapping = <LVDS_FORMAT_VESA>;
59		rockchip,data-width = <24>;
60		rockchip,output = <LVDS_OUTPUT_DUAL>;
61		rockchip,panel = <&panel>;
62		status = "okay";
63
64		display-timings {
65			timing@0 {
66				clock-frequency = <40000000>;
67				hactive = <1920>;
68				vactive = <1080>;
69				hsync-len = <44>;
70				hfront-porch = <88>;
71				hback-porch = <148>;
72				vfront-porch = <4>;
73				vback-porch = <36>;
74				vsync-len = <5>;
75			};
76		};
77	};
78