1 /* 2 * Generated by info2header.py 3 * Do not edit it. 4 */ 5 6 #define OTP_INFO_VER "1.0.1" 7 #define OTP_REG_RESERVED -1 8 #define OTP_REG_VALUE -2 9 #define OTP_REG_VALID_BIT -3 10 11 struct otpstrap_info { 12 signed char bit_offset; 13 signed char length; 14 signed char value; 15 char *information; 16 }; 17 18 struct otpconf_info { 19 signed char dw_offset; 20 signed char bit_offset; 21 signed char length; 22 signed char value; 23 char *information; 24 }; 25 26 static const struct otpstrap_info a0_strap_info[] = { 27 { 0, 1, 0, "Disable Secure Boot" }, 28 { 0, 1, 1, "Enable Secure Boot" }, 29 { 1, 1, 0, "Disable boot from eMMC" }, 30 { 1, 1, 1, "Enable boot from eMMC" }, 31 { 2, 1, 0, "Disable Boot from debug SPI" }, 32 { 2, 1, 1, "Enable Boot from debug SPI" }, 33 { 3, 1, 0, "Enable ARM CM3" }, 34 { 3, 1, 1, "Disable ARM CM3" }, 35 { 4, 1, 0, "No VGA BIOS ROM, VGA BIOS is merged in the system BIOS" }, 36 { 4, 1, 1, "Enable dedicated VGA BIOS ROM" }, 37 { 5, 1, 0, "MAC 1 : RMII/NCSI" }, 38 { 5, 1, 1, "MAC 1 : RGMII" }, 39 { 6, 1, 0, "MAC 2 : RMII/NCSI" }, 40 { 6, 1, 1, "MAC 2 : RGMII" }, 41 { 7, 2, 0, "CPU Frequency : 1GHz" }, 42 { 7, 2, 1, "CPU Frequency : 800MHz" }, 43 { 7, 2, 2, "CPU Frequency : 1.2GHz" }, 44 { 7, 2, 3, "CPU Frequency : 1.4GHz" }, 45 { 10, 2, 0, "HCLK ratio AXI:AHB = default" }, 46 { 10, 2, 1, "HCLK ratio AXI:AHB = 2:1" }, 47 { 10, 2, 2, "HCLK ratio AXI:AHB = 3:1" }, 48 { 10, 2, 3, "HCLK ratio AXI:AHB = 4:1" }, 49 { 12, 2, 0, "VGA memory size : 8MB" }, 50 { 12, 2, 1, "VGA memory size : 16MB" }, 51 { 12, 2, 2, "VGA memory size : 32MB" }, 52 { 12, 2, 3, "VGA memory size : 64MB" }, 53 { 15, 1, 0, "CPU/AXI clock ratio : 2:1" }, 54 { 15, 1, 1, "CPU/AXI clock ratio : 1:1" }, 55 { 16, 1, 0, "Enable ARM JTAG debug" }, 56 { 16, 1, 1, "Disable ARM JTAG debug" }, 57 { 17, 1, 0, "VGA class code : video_device" }, 58 { 17, 1, 1, "VGA class code : vga_device" }, 59 { 18, 1, 0, "Enable debug interfaces 0" }, 60 { 18, 1, 1, "Disable debug interfaces 0" }, 61 { 19, 1, 0, "Boot from eMMC speed mode : normal" }, 62 { 19, 1, 1, "Boot from eMMC speed mode : high" }, 63 { 20, 1, 0, "Disable Pcie EHCI device" }, 64 { 20, 1, 1, "Enable Pcie EHCI device" }, 65 { 21, 1, 0, "Enable ARM JTAG trust world debug" }, 66 { 21, 1, 1, "Disable ARM JTAG trust world debug" }, 67 { 22, 1, 0, "Normal BMC mode" }, 68 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" }, 69 { 23, 1, 0, "SSPRST# pin is for secondary processor dedicated reset pin" }, 70 { 23, 1, 1, "SSPRST# pin is for PCIE root complex dedicated reset pin" }, 71 { 24, 1, 0, "Enable watchdog to reset full chip" }, 72 { 24, 1, 1, "Disable watchdog to reset full chip" }, 73 { 25, 2, 0, "Internal bridge speed selection : 1x" }, 74 { 25, 2, 1, "Internal bridge speed selection : 1/2x" }, 75 { 25, 2, 2, "Internal bridge speed selection : 1/4x" }, 76 { 25, 2, 3, "Internal bridge speed selection : 1/8x" }, 77 { 29, 1, 0, "Enable RVAS function" }, 78 { 29, 1, 1, "Disable RVAS function" }, 79 { 32, 1, 0, "MAC 3 : RMII/NCSI" }, 80 { 32, 1, 1, "MAC 3 : RGMII" }, 81 { 33, 1, 0, "MAC 4 : RMII/NCSI" }, 82 { 33, 1, 1, "MAC 4 : RGMII" }, 83 { 34, 1, 0, "SuperIO configuration address : 0x2e" }, 84 { 34, 1, 1, "SuperIO configuration address : 0x4e" }, 85 { 35, 1, 0, "Enable LPC to decode SuperIO" }, 86 { 35, 1, 1, "Disable LPC to decode SuperIO" }, 87 { 36, 1, 0, "Enable debug interfaces 1" }, 88 { 36, 1, 1, "Disable debug interfaces 1" }, 89 { 37, 1, 0, "Disable ACPI function" }, 90 { 37, 1, 1, "Enable ACPI function" }, 91 { 38, 1, 0, "Select LPC/eSPI : eSPI" }, 92 { 38, 1, 1, "Select LPC/eSPI : LPC" }, 93 { 39, 1, 0, "Disable SAFS mode" }, 94 { 39, 1, 1, "Enable SAFS mode" }, 95 { 40, 1, 0, "Disable boot from uart5" }, 96 { 40, 1, 1, "Enable boot from uart5" }, 97 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" }, 98 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" }, 99 { 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" }, 100 { 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" }, 101 { 43, 1, 0, "Disable boot SPI or eMMC ABR" }, 102 { 43, 1, 1, "Enable boot SPI or eMMC ABR" }, 103 { 44, 1, 0, "Boot SPI ABR Mode : dual" }, 104 { 44, 1, 1, "Boot SPI ABR Mode : single" }, 105 { 45, 3, 0, "Boot SPI flash size : 0MB" }, 106 { 45, 3, 1, "Boot SPI flash size : 2MB" }, 107 { 45, 3, 2, "Boot SPI flash size : 4MB" }, 108 { 45, 3, 3, "Boot SPI flash size : 8MB" }, 109 { 45, 3, 4, "Boot SPI flash size : 16MB" }, 110 { 45, 3, 5, "Boot SPI flash size : 32MB" }, 111 { 45, 3, 6, "Boot SPI flash size : 64MB" }, 112 { 45, 3, 7, "Boot SPI flash size : 128MB" }, 113 { 48, 1, 0, "Disable host SPI ABR" }, 114 { 48, 1, 1, "Enable host SPI ABR" }, 115 { 49, 1, 0, "Disable host SPI ABR mode select pin" }, 116 { 49, 1, 1, "Enable host SPI ABR mode select pin" }, 117 { 50, 1, 0, "Host SPI ABR mode : dual" }, 118 { 50, 1, 1, "Host SPI ABR mode : single" }, 119 { 51, 3, 0, "Host SPI flash size : 0MB" }, 120 { 51, 3, 1, "Host SPI flash size : 2MB" }, 121 { 51, 3, 2, "Host SPI flash size : 4MB" }, 122 { 51, 3, 3, "Host SPI flash size : 8MB" }, 123 { 51, 3, 4, "Host SPI flash size : 16MB" }, 124 { 51, 3, 5, "Host SPI flash size : 32MB" }, 125 { 51, 3, 6, "Host SPI flash size : 64MB" }, 126 { 51, 3, 7, "Host SPI flash size : 128MB" }, 127 { 54, 1, 0, "Disable boot SPI auxiliary control pins" }, 128 { 54, 1, 1, "Enable boot SPI auxiliary control pins" }, 129 { 55, 2, 0, "Boot SPI CRTM size : 0KB" }, 130 { 55, 2, 1, "Boot SPI CRTM size : 256KB" }, 131 { 55, 2, 2, "Boot SPI CRTM size : 512KB" }, 132 { 55, 2, 3, "Boot SPI CRTM size : 1024KB" }, 133 { 57, 2, 0, "Host SPI CRTM size : 0KB" }, 134 { 57, 2, 1, "Host SPI CRTM size : 1024KB" }, 135 { 57, 2, 2, "Host SPI CRTM size : 2048KB" }, 136 { 57, 2, 3, "Host SPI CRTM size : 4096KB" }, 137 { 59, 1, 0, "Disable host SPI auxiliary control pins" }, 138 { 59, 1, 1, "Enable host SPI auxiliary control pins" }, 139 { 60, 1, 0, "Disable GPIO pass through" }, 140 { 60, 1, 1, "Enable GPIO pass through" }, 141 { 62, 1, 0, "Disable dedicate GPIO strap pins" }, 142 { 62, 1, 1, "Enable dedicate GPIO strap pins" } 143 }; 144 145 static const struct otpstrap_info a1_strap_info[] = { 146 { 0, 1, 0, "Disable Secure Boot" }, 147 { 0, 1, 1, "Enable Secure Boot" }, 148 { 1, 1, 0, "Disable boot from eMMC" }, 149 { 1, 1, 1, "Enable boot from eMMC" }, 150 { 2, 1, 0, "Disable Boot from debug SPI" }, 151 { 2, 1, 1, "Enable Boot from debug SPI" }, 152 { 3, 1, 0, "Enable ARM CM3" }, 153 { 3, 1, 1, "Disable ARM CM3" }, 154 { 4, 1, 0, "No VGA BIOS ROM, VGA BIOS is merged in the system BIOS" }, 155 { 4, 1, 1, "Enable dedicated VGA BIOS ROM" }, 156 { 5, 1, 0, "MAC 1 : RMII/NCSI" }, 157 { 5, 1, 1, "MAC 1 : RGMII" }, 158 { 6, 1, 0, "MAC 2 : RMII/NCSI" }, 159 { 6, 1, 1, "MAC 2 : RGMII" }, 160 { 7, 3, 0, "CPU Frequency : 1.2GHz" }, 161 { 7, 3, 1, "CPU Frequency : 1.6MHz" }, 162 { 7, 3, 2, "CPU Frequency : 1.2GHz" }, 163 { 7, 3, 3, "CPU Frequency : 1.6GHz" }, 164 { 7, 3, 4, "CPU Frequency : 800MHz" }, 165 { 7, 3, 5, "CPU Frequency : 800MHz" }, 166 { 7, 3, 6, "CPU Frequency : 800MHz" }, 167 { 7, 3, 7, "CPU Frequency : 800MHz" }, 168 { 10, 2, 0, "HCLK ratio AXI:AHB = default" }, 169 { 10, 2, 1, "HCLK ratio AXI:AHB = 2:1" }, 170 { 10, 2, 2, "HCLK ratio AXI:AHB = 3:1" }, 171 { 10, 2, 3, "HCLK ratio AXI:AHB = 4:1" }, 172 { 12, 2, 0, "VGA memory size : 8MB" }, 173 { 12, 2, 1, "VGA memory size : 16MB" }, 174 { 12, 2, 2, "VGA memory size : 32MB" }, 175 { 12, 2, 3, "VGA memory size : 64MB" }, 176 { 15, 1, 0, "CPU/AXI clock ratio : 2:1" }, 177 { 15, 1, 1, "CPU/AXI clock ratio : 1:1" }, 178 { 16, 1, 0, "Enable ARM JTAG debug" }, 179 { 16, 1, 1, "Disable ARM JTAG debug" }, 180 { 17, 1, 0, "VGA class code : video_device" }, 181 { 17, 1, 1, "VGA class code : vga_device" }, 182 { 18, 1, 0, "Enable debug interfaces 0" }, 183 { 18, 1, 1, "Disable debug interfaces 0" }, 184 { 19, 1, 0, "Boot from eMMC speed mode : normal" }, 185 { 19, 1, 1, "Boot from eMMC speed mode : high" }, 186 { 20, 1, 0, "Disable Pcie EHCI device" }, 187 { 20, 1, 1, "Enable Pcie EHCI device" }, 188 { 21, 1, 0, "Enable ARM JTAG trust world debug" }, 189 { 21, 1, 1, "Disable ARM JTAG trust world debug" }, 190 { 22, 1, 0, "Normal BMC mode" }, 191 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" }, 192 { 23, 1, 0, "SSPRST# pin is for secondary processor dedicated reset pin" }, 193 { 23, 1, 1, "SSPRST# pin is for PCIE root complex dedicated reset pin" }, 194 { 24, 1, 0, "Enable watchdog to reset full chip" }, 195 { 24, 1, 1, "Disable watchdog to reset full chip" }, 196 { 25, 2, 0, "Internal bridge speed selection : 1x" }, 197 { 25, 2, 1, "Internal bridge speed selection : 1/2x" }, 198 { 25, 2, 2, "Internal bridge speed selection : 1/4x" }, 199 { 25, 2, 3, "Internal bridge speed selection : 1/8x" }, 200 { 29, 1, 0, "Enable RVAS function" }, 201 { 29, 1, 1, "Disable RVAS function" }, 202 { 32, 1, 0, "MAC 3 : RMII/NCSI" }, 203 { 32, 1, 1, "MAC 3 : RGMII" }, 204 { 33, 1, 0, "MAC 4 : RMII/NCSI" }, 205 { 33, 1, 1, "MAC 4 : RGMII" }, 206 { 34, 1, 0, "SuperIO configuration address : 0x2e" }, 207 { 34, 1, 1, "SuperIO configuration address : 0x4e" }, 208 { 35, 1, 0, "Enable LPC to decode SuperIO" }, 209 { 35, 1, 1, "Disable LPC to decode SuperIO" }, 210 { 36, 1, 0, "Enable debug interfaces 1" }, 211 { 36, 1, 1, "Disable debug interfaces 1" }, 212 { 37, 1, 0, "Disable ACPI function" }, 213 { 37, 1, 1, "Enable ACPI function" }, 214 { 38, 1, 0, "Select LPC/eSPI : eSPI" }, 215 { 38, 1, 1, "Select LPC/eSPI : LPC" }, 216 { 39, 1, 0, "Disable SAFS mode" }, 217 { 39, 1, 1, "Enable SAFS mode" }, 218 { 40, 1, 0, "Disable boot from uart5" }, 219 { 40, 1, 1, "Enable boot from uart5" }, 220 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" }, 221 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" }, 222 { 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" }, 223 { 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" }, 224 { 43, 1, 0, "Disable boot SPI or eMMC ABR" }, 225 { 43, 1, 1, "Enable boot SPI or eMMC ABR" }, 226 { 44, 1, 0, "Boot SPI ABR Mode : dual" }, 227 { 44, 1, 1, "Boot SPI ABR Mode : single" }, 228 { 45, 3, 0, "Boot SPI flash size : 0MB" }, 229 { 45, 3, 1, "Boot SPI flash size : 2MB" }, 230 { 45, 3, 2, "Boot SPI flash size : 4MB" }, 231 { 45, 3, 3, "Boot SPI flash size : 8MB" }, 232 { 45, 3, 4, "Boot SPI flash size : 16MB" }, 233 { 45, 3, 5, "Boot SPI flash size : 32MB" }, 234 { 45, 3, 6, "Boot SPI flash size : 64MB" }, 235 { 45, 3, 7, "Boot SPI flash size : 128MB" }, 236 { 48, 1, 0, "Disable host SPI ABR" }, 237 { 48, 1, 1, "Enable host SPI ABR" }, 238 { 49, 1, 0, "Disable host SPI ABR mode select pin" }, 239 { 49, 1, 1, "Enable host SPI ABR mode select pin" }, 240 { 50, 1, 0, "Host SPI ABR mode : dual" }, 241 { 50, 1, 1, "Host SPI ABR mode : single" }, 242 { 51, 3, 0, "Host SPI flash size : 0MB" }, 243 { 51, 3, 1, "Host SPI flash size : 2MB" }, 244 { 51, 3, 2, "Host SPI flash size : 4MB" }, 245 { 51, 3, 3, "Host SPI flash size : 8MB" }, 246 { 51, 3, 4, "Host SPI flash size : 16MB" }, 247 { 51, 3, 5, "Host SPI flash size : 32MB" }, 248 { 51, 3, 6, "Host SPI flash size : 64MB" }, 249 { 51, 3, 7, "Host SPI flash size : 128MB" }, 250 { 54, 1, 0, "Disable boot SPI auxiliary control pins" }, 251 { 54, 1, 1, "Enable boot SPI auxiliary control pins" }, 252 { 55, 2, 0, "Boot SPI CRTM size : 0KB" }, 253 { 55, 2, 1, "Boot SPI CRTM size : 256KB" }, 254 { 55, 2, 2, "Boot SPI CRTM size : 512KB" }, 255 { 55, 2, 3, "Boot SPI CRTM size : 1024KB" }, 256 { 57, 2, 0, "Host SPI CRTM size : 0KB" }, 257 { 57, 2, 1, "Host SPI CRTM size : 1024KB" }, 258 { 57, 2, 2, "Host SPI CRTM size : 2048KB" }, 259 { 57, 2, 3, "Host SPI CRTM size : 4096KB" }, 260 { 59, 1, 0, "Disable host SPI auxiliary control pins" }, 261 { 59, 1, 1, "Enable host SPI auxiliary control pins" }, 262 { 60, 1, 0, "Disable GPIO pass through" }, 263 { 60, 1, 1, "Enable GPIO pass through" }, 264 { 62, 1, 0, "Disable dedicate GPIO strap pins" }, 265 { 62, 1, 1, "Enable dedicate GPIO strap pins" } 266 }; 267 268 static const struct otpstrap_info a2_strap_info[] = { 269 { 0, 1, 0, "Disable Secure Boot" }, 270 { 0, 1, 1, "Enable Secure Boot" }, 271 { 1, 1, 0, "Disable boot from eMMC" }, 272 { 1, 1, 1, "Enable boot from eMMC" }, 273 { 2, 1, 0, "Disable Boot from debug SPI" }, 274 { 2, 1, 1, "Enable Boot from debug SPI" }, 275 { 3, 1, 0, "Enable ARM CM3" }, 276 { 3, 1, 1, "Disable ARM CM3" }, 277 { 4, 1, 0, "No VGA BIOS ROM, VGA BIOS is merged in the system BIOS" }, 278 { 4, 1, 1, "Enable dedicated VGA BIOS ROM" }, 279 { 5, 1, 0, "MAC 1 : RMII/NCSI" }, 280 { 5, 1, 1, "MAC 1 : RGMII" }, 281 { 6, 1, 0, "MAC 2 : RMII/NCSI" }, 282 { 6, 1, 1, "MAC 2 : RGMII" }, 283 { 7, 3, 0, "CPU Frequency : 1.2GHz" }, 284 { 7, 3, 1, "CPU Frequency : 1.6MHz" }, 285 { 7, 3, 2, "CPU Frequency : 1.2GHz" }, 286 { 7, 3, 3, "CPU Frequency : 1.6GHz" }, 287 { 7, 3, 4, "CPU Frequency : 800MHz" }, 288 { 7, 3, 5, "CPU Frequency : 800MHz" }, 289 { 7, 3, 6, "CPU Frequency : 800MHz" }, 290 { 7, 3, 7, "CPU Frequency : 800MHz" }, 291 { 10, 2, 0, "HCLK ratio AXI:AHB = default" }, 292 { 10, 2, 1, "HCLK ratio AXI:AHB = 2:1" }, 293 { 10, 2, 2, "HCLK ratio AXI:AHB = 3:1" }, 294 { 10, 2, 3, "HCLK ratio AXI:AHB = 4:1" }, 295 { 12, 2, 0, "VGA memory size : 8MB" }, 296 { 12, 2, 1, "VGA memory size : 16MB" }, 297 { 12, 2, 2, "VGA memory size : 32MB" }, 298 { 12, 2, 3, "VGA memory size : 64MB" }, 299 { 15, 1, 0, "CPU/AXI clock ratio : 2:1" }, 300 { 15, 1, 1, "CPU/AXI clock ratio : 1:1" }, 301 { 16, 1, 0, "Enable ARM JTAG debug" }, 302 { 16, 1, 1, "Disable ARM JTAG debug" }, 303 { 17, 1, 0, "VGA class code : video_device" }, 304 { 17, 1, 1, "VGA class code : vga_device" }, 305 { 18, 1, 0, "Enable debug interfaces 0" }, 306 { 18, 1, 1, "Disable debug interfaces 0" }, 307 { 19, 1, 0, "Boot from eMMC speed mode : normal" }, 308 { 19, 1, 1, "Boot from eMMC speed mode : high" }, 309 { 20, 1, 0, "Disable Pcie EHCI device" }, 310 { 20, 1, 1, "Enable Pcie EHCI device" }, 311 { 21, 1, 0, "Enable ARM JTAG trust world debug" }, 312 { 21, 1, 1, "Disable ARM JTAG trust world debug" }, 313 { 22, 1, 0, "Normal BMC mode" }, 314 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" }, 315 { 23, 1, 0, "SSPRST# pin is for secondary processor dedicated reset pin" }, 316 { 23, 1, 1, "SSPRST# pin is for PCIE root complex dedicated reset pin" }, 317 { 24, 1, 0, "Enable watchdog to reset full chip" }, 318 { 24, 1, 1, "Disable watchdog to reset full chip" }, 319 { 25, 2, 0, "Internal bridge speed selection : 1x" }, 320 { 25, 2, 1, "Internal bridge speed selection : 1/2x" }, 321 { 25, 2, 2, "Internal bridge speed selection : 1/4x" }, 322 { 25, 2, 3, "Internal bridge speed selection : 1/8x" }, 323 { 29, 1, 0, "Enable RVAS function" }, 324 { 29, 1, 1, "Disable RVAS function" }, 325 { 32, 1, 0, "MAC 3 : RMII/NCSI" }, 326 { 32, 1, 1, "MAC 3 : RGMII" }, 327 { 33, 1, 0, "MAC 4 : RMII/NCSI" }, 328 { 33, 1, 1, "MAC 4 : RGMII" }, 329 { 34, 1, 0, "SuperIO configuration address : 0x2e" }, 330 { 34, 1, 1, "SuperIO configuration address : 0x4e" }, 331 { 35, 1, 0, "Enable LPC to decode SuperIO" }, 332 { 35, 1, 1, "Disable LPC to decode SuperIO" }, 333 { 36, 1, 0, "Enable debug interfaces 1" }, 334 { 36, 1, 1, "Disable debug interfaces 1" }, 335 { 37, 1, 0, "Disable ACPI function" }, 336 { 37, 1, 1, "Enable ACPI function" }, 337 { 38, 1, 0, "Select LPC/eSPI : eSPI" }, 338 { 38, 1, 1, "Select LPC/eSPI : LPC" }, 339 { 39, 1, 0, "Disable SAFS mode" }, 340 { 39, 1, 1, "Enable SAFS mode" }, 341 { 40, 1, 0, "Disable boot from uart5" }, 342 { 40, 1, 1, "Enable boot from uart5" }, 343 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" }, 344 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" }, 345 { 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" }, 346 { 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" }, 347 { 43, 1, 0, "Disable boot SPI or eMMC ABR" }, 348 { 43, 1, 1, "Enable boot SPI or eMMC ABR" }, 349 { 44, 1, 0, "Boot SPI ABR Mode : dual" }, 350 { 44, 1, 1, "Boot SPI ABR Mode : single" }, 351 { 45, 3, 0, "Boot SPI flash size : 0MB" }, 352 { 45, 3, 1, "Boot SPI flash size : 2MB" }, 353 { 45, 3, 2, "Boot SPI flash size : 4MB" }, 354 { 45, 3, 3, "Boot SPI flash size : 8MB" }, 355 { 45, 3, 4, "Boot SPI flash size : 16MB" }, 356 { 45, 3, 5, "Boot SPI flash size : 32MB" }, 357 { 45, 3, 6, "Boot SPI flash size : 64MB" }, 358 { 45, 3, 7, "Boot SPI flash size : 128MB" }, 359 { 48, 1, 0, "Disable host SPI ABR" }, 360 { 48, 1, 1, "Enable host SPI ABR" }, 361 { 49, 1, 0, "Disable host SPI ABR mode select pin" }, 362 { 49, 1, 1, "Enable host SPI ABR mode select pin" }, 363 { 50, 1, 0, "Host SPI ABR mode : dual" }, 364 { 50, 1, 1, "Host SPI ABR mode : single" }, 365 { 51, 3, 0, "Host SPI flash size : 0MB" }, 366 { 51, 3, 1, "Host SPI flash size : 2MB" }, 367 { 51, 3, 2, "Host SPI flash size : 4MB" }, 368 { 51, 3, 3, "Host SPI flash size : 8MB" }, 369 { 51, 3, 4, "Host SPI flash size : 16MB" }, 370 { 51, 3, 5, "Host SPI flash size : 32MB" }, 371 { 51, 3, 6, "Host SPI flash size : 64MB" }, 372 { 51, 3, 7, "Host SPI flash size : 128MB" }, 373 { 54, 1, 0, "Disable boot SPI auxiliary control pins" }, 374 { 54, 1, 1, "Enable boot SPI auxiliary control pins" }, 375 { 55, 2, 0, "Boot SPI CRTM size : 0KB" }, 376 { 55, 2, 1, "Boot SPI CRTM size : 256KB" }, 377 { 55, 2, 2, "Boot SPI CRTM size : 512KB" }, 378 { 55, 2, 3, "Boot SPI CRTM size : 1024KB" }, 379 { 57, 2, 0, "Host SPI CRTM size : 0KB" }, 380 { 57, 2, 1, "Host SPI CRTM size : 1024KB" }, 381 { 57, 2, 2, "Host SPI CRTM size : 2048KB" }, 382 { 57, 2, 3, "Host SPI CRTM size : 4096KB" }, 383 { 59, 1, 0, "Disable host SPI auxiliary control pins" }, 384 { 59, 1, 1, "Enable host SPI auxiliary control pins" }, 385 { 60, 1, 0, "Disable GPIO pass through" }, 386 { 60, 1, 1, "Enable GPIO pass through" }, 387 { 62, 1, 0, "Disable dedicate GPIO strap pins" }, 388 { 62, 1, 1, "Enable dedicate GPIO strap pins" } 389 }; 390 391 static const struct otpconf_info a0_conf_info[] = { 392 { 0, 1, 1, 0, "Disable Secure Boot" }, 393 { 0, 1, 1, 1, "Enable Secure Boot" }, 394 { 0, 3, 1, 0, "User region ECC disable" }, 395 { 0, 3, 1, 1, "User region ECC enable" }, 396 { 0, 4, 1, 0, "Secure Region ECC disable" }, 397 { 0, 4, 1, 1, "Secure Region ECC enable" }, 398 { 0, 5, 1, 0, "Enable low security key" }, 399 { 0, 5, 1, 1, "Disable low security key" }, 400 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" }, 401 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" }, 402 { 0, 7, 1, 0, "Secure Boot Mode: Mode_GCM" }, 403 { 0, 7, 1, 1, "Secure Boot Mode: Mode_2" }, 404 { 0, 10, 2, 0, "RSA mode : RSA1024" }, 405 { 0, 10, 2, 1, "RSA mode : RSA2048" }, 406 { 0, 10, 2, 2, "RSA mode : RSA3072" }, 407 { 0, 10, 2, 3, "RSA mode : RSA4096" }, 408 { 0, 12, 2, 0, "SHA mode : SHA224" }, 409 { 0, 12, 2, 1, "SHA mode : SHA256" }, 410 { 0, 12, 2, 2, "SHA mode : SHA384" }, 411 { 0, 12, 2, 3, "SHA mode : SHA512" }, 412 { 0, 14, 1, 0, "Enable patch code" }, 413 { 0, 14, 1, 1, "Disable patch code" }, 414 { 0, 15, 1, 0, "Enable Boot from Uart" }, 415 { 0, 15, 1, 1, "Disable Boot from Uart" }, 416 { 0, 16, 6, OTP_REG_VALUE, "Secure Region size (DW): 0x%x" }, 417 { 0, 22, 1, 0, "Secure Region : Writable" }, 418 { 0, 22, 1, 1, "Secure Region : Write Protect" }, 419 { 0, 23, 1, 0, "User Region : Writable" }, 420 { 0, 23, 1, 1, "User Region : Write Protect" }, 421 { 0, 24, 1, 0, "Configure Region : Writable" }, 422 { 0, 24, 1, 1, "Configure Region : Write Protect" }, 423 { 0, 25, 1, 0, "OTP strap Region : Writable" }, 424 { 0, 25, 1, 1, "OTP strap Region : Write Protect" }, 425 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" }, 426 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" }, 427 { 0, 27, 1, 0, "Disable image encryption" }, 428 { 0, 27, 1, 1, "Enable image encryption" }, 429 { 0, 29, 1, 0, "OTP key retire Region : Writable" }, 430 { 0, 29, 1, 1, "OTP key retire Region : Write Protect" }, 431 { 0, 31, 1, 0, "OTP memory lock disable" }, 432 { 0, 31, 1, 1, "OTP memory lock enable" }, 433 { 2, 0, 16, OTP_REG_VALUE, "Vender ID : 0x%x" }, 434 { 2, 16, 16, OTP_REG_VALUE, "Key Revision : 0x%x" }, 435 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" }, 436 { 4, 0, 8, OTP_REG_VALID_BIT, "Keys retire : %s" }, 437 { 5, 0, 32, OTP_REG_VALUE, "User define data, random number low : 0x%x" }, 438 { 6, 0, 32, OTP_REG_VALUE, "User define data, random number high : 0x%x" }, 439 { 10, 0, 64, OTP_REG_VALUE, "Manifest ID : 0x%x" }, 440 { 14, 0, 11, OTP_REG_VALUE, "Patch code location (DW): 0x%x" }, 441 { 14, 11, 6, OTP_REG_VALUE, "Patch code size (DW): 0x%x" } 442 }; 443 444 static const struct otpconf_info a1_conf_info[] = { 445 { 0, 1, 1, 0, "Disable Secure Boot" }, 446 { 0, 1, 1, 1, "Enable Secure Boot" }, 447 { 0, 3, 1, 0, "User region ECC disable" }, 448 { 0, 3, 1, 1, "User region ECC enable" }, 449 { 0, 4, 1, 0, "Secure Region ECC disable" }, 450 { 0, 4, 1, 1, "Secure Region ECC enable" }, 451 { 0, 5, 1, 0, "Enable low security key" }, 452 { 0, 5, 1, 1, "Disable low security key" }, 453 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" }, 454 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" }, 455 { 0, 7, 1, 0, "Secure Boot Mode: Mode_GCM" }, 456 { 0, 7, 1, 1, "Secure Boot Mode: Mode_2" }, 457 { 0, 10, 2, 0, "RSA mode : RSA1024" }, 458 { 0, 10, 2, 1, "RSA mode : RSA2048" }, 459 { 0, 10, 2, 2, "RSA mode : RSA3072" }, 460 { 0, 10, 2, 3, "RSA mode : RSA4096" }, 461 { 0, 12, 2, 0, "SHA mode : SHA224" }, 462 { 0, 12, 2, 1, "SHA mode : SHA256" }, 463 { 0, 12, 2, 2, "SHA mode : SHA384" }, 464 { 0, 12, 2, 3, "SHA mode : SHA512" }, 465 { 0, 14, 1, 0, "Enable patch code" }, 466 { 0, 14, 1, 1, "Disable patch code" }, 467 { 0, 15, 1, 0, "Enable Boot from Uart" }, 468 { 0, 15, 1, 1, "Disable Boot from Uart" }, 469 { 0, 16, 6, OTP_REG_VALUE, "Secure Region size (DW): 0x%x" }, 470 { 0, 22, 1, 0, "Secure Region : Writable" }, 471 { 0, 22, 1, 1, "Secure Region : Write Protect" }, 472 { 0, 23, 1, 0, "User Region : Writable" }, 473 { 0, 23, 1, 1, "User Region : Write Protect" }, 474 { 0, 24, 1, 0, "Configure Region : Writable" }, 475 { 0, 24, 1, 1, "Configure Region : Write Protect" }, 476 { 0, 25, 1, 0, "OTP strap Region : Writable" }, 477 { 0, 25, 1, 1, "OTP strap Region : Write Protect" }, 478 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" }, 479 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" }, 480 { 0, 27, 1, 0, "Disable image encryption" }, 481 { 0, 27, 1, 1, "Enable image encryption" }, 482 { 0, 29, 1, 0, "OTP key retire Region : Writable" }, 483 { 0, 29, 1, 1, "OTP key retire Region : Write Protect" }, 484 { 0, 31, 1, 0, "OTP memory lock disable" }, 485 { 0, 31, 1, 1, "OTP memory lock enable" }, 486 { 2, 0, 16, OTP_REG_VALUE, "Vender ID : 0x%x" }, 487 { 2, 16, 16, OTP_REG_VALUE, "Key Revision : 0x%x" }, 488 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" }, 489 { 4, 0, 8, OTP_REG_VALID_BIT, "Keys retire : %s" }, 490 { 5, 0, 32, OTP_REG_VALUE, "User define data, random number low : 0x%x" }, 491 { 6, 0, 32, OTP_REG_VALUE, "User define data, random number high : 0x%x" }, 492 { 10, 0, 64, OTP_REG_VALUE, "Manifest ID : 0x%x" }, 493 { 14, 0, 11, OTP_REG_VALUE, "Patch code location (DW): 0x%x" }, 494 { 14, 11, 6, OTP_REG_VALUE, "Patch code size (DW): 0x%x" } 495 }; 496 497 static const struct otpconf_info a2_conf_info[] = { 498 { 0, 1, 1, 0, "Enable OTP Memory BIST Mode" }, 499 { 0, 1, 1, 1, "Disable OTP Memory BIST Mode" }, 500 { 0, 1, 1, 0, "Disable Secure Boot" }, 501 { 0, 1, 1, 1, "Enable Secure Boot" }, 502 { 0, 3, 1, 0, "User region ECC disable" }, 503 { 0, 3, 1, 1, "User region ECC enable" }, 504 { 0, 4, 1, 0, "Secure Region ECC disable" }, 505 { 0, 4, 1, 1, "Secure Region ECC enable" }, 506 { 0, 5, 1, 0, "Enable low security key" }, 507 { 0, 5, 1, 1, "Disable low security key" }, 508 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" }, 509 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" }, 510 { 0, 7, 1, 0, "Secure Boot Mode: Mode_GCM" }, 511 { 0, 7, 1, 1, "Secure Boot Mode: Mode_2" }, 512 { 0, 9, 1, 0, "ROM code will dump boot messages" }, 513 { 0, 9, 1, 1, "ROM code message is disabled" }, 514 { 0, 10, 2, 0, "RSA mode : RSA1024" }, 515 { 0, 10, 2, 1, "RSA mode : RSA2048" }, 516 { 0, 10, 2, 2, "RSA mode : RSA3072" }, 517 { 0, 10, 2, 3, "RSA mode : RSA4096" }, 518 { 0, 12, 2, 0, "SHA mode : SHA224" }, 519 { 0, 12, 2, 1, "SHA mode : SHA256" }, 520 { 0, 12, 2, 2, "SHA mode : SHA384" }, 521 { 0, 12, 2, 3, "SHA mode : SHA512" }, 522 { 0, 14, 1, 0, "Enable patch code" }, 523 { 0, 14, 1, 1, "Disable patch code" }, 524 { 0, 15, 1, 0, "Enable Boot from Uart" }, 525 { 0, 15, 1, 1, "Disable Boot from Uart" }, 526 { 0, 16, 6, OTP_REG_VALUE, "Secure Region size (DW): 0x%x" }, 527 { 0, 22, 1, 0, "Secure Region : Writable" }, 528 { 0, 22, 1, 1, "Secure Region : Write Protect" }, 529 { 0, 23, 1, 0, "User Region : Writable" }, 530 { 0, 23, 1, 1, "User Region : Write Protect" }, 531 { 0, 24, 1, 0, "Configure Region : Writable" }, 532 { 0, 24, 1, 1, "Configure Region : Write Protect" }, 533 { 0, 25, 1, 0, "OTP strap Region : Writable" }, 534 { 0, 25, 1, 1, "OTP strap Region : Write Protect" }, 535 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" }, 536 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" }, 537 { 0, 27, 1, 0, "Disable image encryption" }, 538 { 0, 27, 1, 1, "Enable image encryption" }, 539 { 0, 29, 1, 0, "OTP key retire Region : Writable" }, 540 { 0, 29, 1, 1, "OTP key retire Region : Write Protect" }, 541 { 0, 30, 1, 0, "Boot from UART/VUART when normal boot is fail" }, 542 { 0, 30, 1, 1, "Disable auto UART/VUART boot option" }, 543 { 0, 31, 1, 0, "OTP memory lock disable" }, 544 { 0, 31, 1, 1, "OTP memory lock enable" }, 545 { 2, 0, 16, OTP_REG_VALUE, "Vender ID : 0x%x" }, 546 { 2, 16, 16, OTP_REG_VALUE, "Key Revision : 0x%x" }, 547 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" }, 548 { 3, 16, 1, 0, "Boot from UART using: UART5" }, 549 { 3, 16, 1, 1, "Boot from UART using: UART1" }, 550 { 3, 17, 1, 0, "Enable Auto Boot from UART or VUART" }, 551 { 3, 17, 1, 1, "Disable Auto Boot from UART or VUART" }, 552 { 3, 18, 1, 0, "Enable Auto Boot from VUART2 over PCIE" }, 553 { 3, 18, 1, 1, "Disable Auto Boot from VUART2 over PCIE" }, 554 { 3, 19, 1, 0, "Enable Auto Boot from VUART2 over LPC" }, 555 { 3, 19, 1, 1, "Disable Auto Boot from VUART2 over LPC" }, 556 { 3, 20, 1, 0, "Enable ROM code based programming control" }, 557 { 3, 20, 1, 1, "Disable ROM code based programming control" }, 558 { 3, 21, 3, OTP_REG_VALUE, "Rollback prevention shift bit : 0x%x" }, 559 { 3, 24, 6, OTP_REG_VALUE, "Extra Data Write Protection Region size (DW): 0x%x" }, 560 { 3, 30, 1, 0, "Do not erase signature data after secure boot check" }, 561 { 3, 30, 1, 1, "Erase signature data after secure boot check" }, 562 { 3, 31, 1, 0, "Do not erase RSA public key after secure boot check" }, 563 { 3, 31, 1, 1, "Erase RSA public key after secure boot check" }, 564 { 4, 0, 8, OTP_REG_VALID_BIT, "Keys retire : %s" }, 565 { 5, 0, 32, OTP_REG_VALUE, "User define data, random number low : 0x%x" }, 566 { 6, 0, 32, OTP_REG_VALUE, "User define data, random number high : 0x%x" }, 567 { 10, 0, 64, OTP_REG_VALUE, "Manifest ID : 0x%x" }, 568 { 14, 0, 11, OTP_REG_VALUE, "Patch code location (DW): 0x%x" }, 569 { 14, 11, 6, OTP_REG_VALUE, "Patch code size (DW): 0x%x" } 570 }; 571 572