1 /* 2 * This program is distributed in the hope that it will be useful, 3 * but WITHOUT ANY WARRANTY; without even the implied warranty of 4 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 5 * GNU General Public License for more details. 6 * 7 * You should have received a copy of the GNU General Public License 8 * along with this program; if not, write to the Free Software 9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 10 */ 11 #include <stdlib.h> 12 #include <common.h> 13 #include <console.h> 14 #include <bootretry.h> 15 #include <cli.h> 16 #include <command.h> 17 #include <console.h> 18 #include <malloc.h> 19 #include <inttypes.h> 20 #include <mapmem.h> 21 #include <asm/io.h> 22 #include <linux/compiler.h> 23 #include <u-boot/sha256.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define OTP_PASSWD 0x349fe38a 28 #define RETRY 3 29 #define OTP_REGION_STRAP BIT(0) 30 #define OTP_REGION_CONF BIT(1) 31 #define OTP_REGION_DATA BIT(2) 32 33 #define OTP_USAGE -1 34 #define OTP_FAILURE -2 35 #define OTP_SUCCESS 0 36 37 #define OTP_PROG_SKIP 1 38 39 #define OTP_KEY_TYPE_RSA 1 40 #define OTP_KEY_TYPE_AES 2 41 #define OTP_KEY_TYPE_VAULT 3 42 #define OTP_KEY_TYPE_HMAC 4 43 44 45 #define OTP_REG_RESERVED -1 46 #define OTP_REG_VALUE -2 47 #define OTP_REG_VALID_BIT -3 48 49 #define PBSTR "||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||" 50 #define PBWIDTH 60 51 52 #define OTP_BASE 0x1e6f2000 53 #define OTP_PROTECT_KEY OTP_BASE 54 #define OTP_COMMAND OTP_BASE + 0x4 55 #define OTP_TIMING OTP_BASE + 0x8 56 #define OTP_ADDR OTP_BASE + 0x10 57 #define OTP_STATUS OTP_BASE + 0x14 58 #define OTP_COMPARE_1 OTP_BASE + 0x20 59 #define OTP_COMPARE_2 OTP_BASE + 0x24 60 #define OTP_COMPARE_3 OTP_BASE + 0x28 61 #define OTP_COMPARE_4 OTP_BASE + 0x2c 62 63 #define OTP_MAGIC "SOCOTP" 64 #define CHECKSUM_LEN 32 65 #define OTP_INC_DATA (1 << 31) 66 #define OTP_INC_CONFIG (1 << 30) 67 #define OTP_INC_STRAP (1 << 29) 68 #define OTP_ECC_EN (1 << 28) 69 #define OTP_REGION_SIZE(info) ((info >> 16) & 0xffff) 70 #define OTP_REGION_OFFSET(info) (info & 0xffff) 71 #define OTP_IMAGE_SIZE(info) (info & 0xffff) 72 73 #define OTP_AST2600A0 0 74 #define OTP_AST2600A1 1 75 #define OTP_AST2600A2 7 // fpga 76 77 struct otp_header { 78 u8 otp_magic[8]; 79 u8 otp_version[8]; 80 u32 image_info; 81 u32 data_info; 82 u32 config_info; 83 u32 strap_info; 84 u32 checksum_offset; 85 } __attribute__((packed)); 86 87 struct otpstrap_status { 88 int value; 89 int option_array[7]; 90 int remain_times; 91 int writeable_option; 92 int reg_protected; 93 int protected; 94 }; 95 96 struct otpconf_parse { 97 int dw_offset; 98 int bit; 99 int length; 100 int value; 101 int ignore; 102 char status[80]; 103 }; 104 105 struct otpstrap_info { 106 int8_t bit_offset; 107 int8_t length; 108 int8_t value; 109 char *information; 110 }; 111 112 struct otpconf_info { 113 int8_t dw_offset; 114 int8_t bit_offset; 115 int8_t length; 116 int8_t value; 117 char *information; 118 }; 119 120 struct otpkey_type { 121 int value; 122 int key_type; 123 int need_id; 124 char information[110]; 125 }; 126 127 struct otp_info_cb { 128 int version; 129 const struct otpstrap_info *strap_info; 130 int strap_info_len; 131 const struct otpconf_info *conf_info; 132 int conf_info_len; 133 const struct otpkey_type *key_info; 134 int key_info_len; 135 136 }; 137 138 struct otp_image_layout { 139 int data_length; 140 int conf_length; 141 int strap_length; 142 uint8_t *data; 143 uint8_t *data_ignore; 144 uint8_t *conf; 145 uint8_t *conf_ignore; 146 uint8_t *strap; 147 uint8_t *strap_reg_pro; 148 uint8_t *strap_pro; 149 uint8_t *strap_ignore; 150 }; 151 152 static struct otp_info_cb info_cb; 153 154 static const struct otpstrap_info a0_strap_info[] = { 155 { 0, 1, 0, "Disable secure boot" }, 156 { 0, 1, 1, "Enable secure boot" }, 157 { 1, 1, 0, "Disable boot from eMMC" }, 158 { 1, 1, 1, "Enable boot from eMMC" }, 159 { 2, 1, 0, "Disable Boot from debug SPI" }, 160 { 2, 1, 1, "Enable Boot from debug SPI" }, 161 { 3, 1, 0, "Enable ARM CM3" }, 162 { 3, 1, 1, "Disable ARM CM3" }, 163 { 4, 1, 0, "No VGA BIOS ROM, VGA BIOS is merged in the system BIOS" }, 164 { 4, 1, 1, "Enable dedicated VGA BIOS ROM" }, 165 { 5, 1, 0, "MAC 1 : RMII/NCSI" }, 166 { 5, 1, 1, "MAC 1 : RGMII" }, 167 { 6, 1, 0, "MAC 2 : RMII/NCSI" }, 168 { 6, 1, 1, "MAC 2 : RGMII" }, 169 { 7, 3, 0, "CPU Frequency : 1GHz" }, 170 { 7, 3, 1, "CPU Frequency : 800MHz" }, 171 { 7, 3, 2, "CPU Frequency : 1.2GHz" }, 172 { 7, 3, 3, "CPU Frequency : 1.4GHz" }, 173 { 10, 2, 0, "HCLK ratio AXI:AHB = 2:1" }, 174 { 10, 2, 1, "HCLK ratio AXI:AHB = 2:1" }, 175 { 10, 2, 2, "HCLK ratio AXI:AHB = 3:1" }, 176 { 10, 2, 3, "HCLK ratio AXI:AHB = 4:1" }, 177 { 12, 2, 0, "VGA memory size : 8MB" }, 178 { 12, 2, 1, "VGA memory size : 16MB" }, 179 { 12, 2, 2, "VGA memory size : 32MB" }, 180 { 12, 2, 3, "VGA memory size : 64MB" }, 181 { 14, 3, OTP_REG_RESERVED, "" }, 182 { 17, 1, 0, "VGA class code : Class Code for video device" }, 183 { 17, 1, 1, "VGA class code : Class Code for VGA device" }, 184 { 18, 1, 0, "Enable debug interfaces 0" }, 185 { 18, 1, 1, "Disable debug interfaces 0" }, 186 { 19, 1, 0, "Boot from emmc mode : High eMMC speed" }, 187 { 19, 1, 1, "Boot from emmc mode : Normal eMMC speed" }, 188 { 20, 1, 0, "Enable Pcie EHCI device" }, 189 { 20, 1, 1, "Disable Pcie EHCI device" }, 190 { 21, 1, 0, "Enable VGA XDMA function" }, 191 { 21, 1, 1, "Disable VGA XDMA function" }, 192 { 22, 1, 0, "Normal BMC mode" }, 193 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" }, 194 { 23, 1, 0, "SSPRST# pin is for secondary processor dedicated reset pin" }, 195 { 23, 1, 1, "SSPRST# pin is for PCIE root complex dedicated reset pin" }, 196 { 24, 1, 0, "DRAM types : DDR4" }, 197 { 24, 1, 1, "DRAM types : DDR3" }, 198 { 25, 5, OTP_REG_RESERVED, "" }, 199 { 30, 2, OTP_REG_RESERVED, "" }, 200 { 32, 1, 0, "MAC 3 : RMII/NCSI" }, 201 { 32, 1, 1, "MAC 3 : RGMII" }, 202 { 33, 1, 0, "MAC 4 : RMII/NCSI" }, 203 { 33, 1, 1, "MAC 4 : RGMII" }, 204 { 34, 1, 0, "SuperIO configuration address : 0x2E" }, 205 { 34, 1, 1, "SuperIO configuration address : 0x4E" }, 206 { 35, 1, 0, "Enable LPC to decode SuperIO" }, 207 { 35, 1, 1, "Disable LPC to decode SuperIO" }, 208 { 36, 1, 0, "Enable debug interfaces 1" }, 209 { 36, 1, 1, "Disable debug interfaces 1" }, 210 { 37, 1, 0, "Disable ACPI function" }, 211 { 37, 1, 1, "Enable ACPI function" }, 212 { 38, 1, 0, "Enable eSPI mode" }, 213 { 38, 1, 1, "Enable LPC mode" }, 214 { 39, 1, 0, "Enable SAFS mode" }, 215 { 39, 1, 1, "Enable SAFS mode" }, 216 { 40, 2, OTP_REG_RESERVED, "" }, 217 { 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" }, 218 { 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" }, 219 { 43, 1, 0, "Disable boot SPI ABR" }, 220 { 43, 1, 1, "Enable boot SPI ABR" }, 221 { 44, 1, 0, "Boot SPI ABR mode : dual SPI flash" }, 222 { 44, 1, 1, "Boot SPI ABR mode : single SPI flash" }, 223 { 45, 3, 0, "Boot SPI flash size : no define size" }, 224 { 45, 3, 1, "Boot SPI flash size : 2MB" }, 225 { 45, 3, 2, "Boot SPI flash size : 4MB" }, 226 { 45, 3, 3, "Boot SPI flash size : 8MB" }, 227 { 45, 3, 4, "Boot SPI flash size : 16MB" }, 228 { 45, 3, 5, "Boot SPI flash size : 32MB" }, 229 { 45, 3, 6, "Boot SPI flash size : 64MB" }, 230 { 45, 3, 7, "Boot SPI flash size : 128MB" }, 231 { 48, 1, 0, "Disable host SPI ABR" }, 232 { 48, 1, 1, "Enable host SPI ABR" }, 233 { 49, 1, 0, "Disable host SPI ABR mode select pin" }, 234 { 49, 1, 1, "Enable host SPI ABR mode select pin" }, 235 { 50, 1, 0, "Host SPI ABR mode : dual SPI flash" }, 236 { 50, 1, 1, "Host SPI ABR mode : single SPI flash" }, 237 { 51, 3, 0, "Host SPI flash size : no define size" }, 238 { 51, 3, 1, "Host SPI flash size : 2MB" }, 239 { 51, 3, 2, "Host SPI flash size : 4MB" }, 240 { 51, 3, 3, "Host SPI flash size : 8MB" }, 241 { 51, 3, 4, "Host SPI flash size : 16MB" }, 242 { 51, 3, 5, "Host SPI flash size : 32MB" }, 243 { 51, 3, 6, "Host SPI flash size : 64MB" }, 244 { 51, 3, 7, "Host SPI flash size : 128MB" }, 245 { 54, 1, 0, "Disable boot SPI auxiliary control pins" }, 246 { 54, 1, 1, "Enable boot SPI auxiliary control pins" }, 247 { 55, 2, 0, "Boot SPI CRTM size : disable CRTM" }, 248 { 55, 2, 1, "Boot SPI CRTM size : 256KB" }, 249 { 55, 2, 2, "Boot SPI CRTM size : 512KB" }, 250 { 55, 2, 3, "Boot SPI CRTM size : 1MB" }, 251 { 57, 2, 0, "Host SPI CRTM size : disable CRTM" }, 252 { 57, 2, 1, "Host SPI CRTM size : 256KB" }, 253 { 57, 2, 2, "Host SPI CRTM size : 512KB" }, 254 { 57, 2, 3, "Host SPI CRTM size : 1MB" }, 255 { 59, 1, 0, "Disable host SPI auxiliary control pins" }, 256 { 59, 1, 1, "Enable host SPI auxiliary control pins" }, 257 { 60, 1, 0, "Disable GPIO pass through" }, 258 { 60, 1, 1, "Enable GPIO pass through" }, 259 { 61, 1, 0, "Enable low security secure boot key" }, 260 { 61, 1, 1, "Disable low security secure boot key" }, 261 { 62, 1, 0, "Disable dedicate GPIO strap pins" }, 262 { 62, 1, 1, "Enable dedicate GPIO strap pins" }, 263 { 63, 1, OTP_REG_RESERVED, "" } 264 }; 265 266 static const struct otpstrap_info a1_strap_info[] = { 267 { 0, 1, 0, "Disable secure boot" }, 268 { 0, 1, 1, "Enable secure boot" }, 269 { 1, 1, 0, "Disable boot from eMMC" }, 270 { 1, 1, 1, "Enable boot from eMMC" }, 271 { 2, 1, 0, "Disable Boot from debug SPI" }, 272 { 2, 1, 1, "Enable Boot from debug SPI" }, 273 { 3, 1, 0, "Enable ARM CM3" }, 274 { 3, 1, 1, "Disable ARM CM3" }, 275 { 4, 1, 0, "No VGA BIOS ROM, VGA BIOS is merged in the system BIOS" }, 276 { 4, 1, 1, "Enable dedicated VGA BIOS ROM" }, 277 { 5, 1, 0, "MAC 1 : RMII/NCSI" }, 278 { 5, 1, 1, "MAC 1 : RGMII" }, 279 { 6, 1, 0, "MAC 2 : RMII/NCSI" }, 280 { 6, 1, 1, "MAC 2 : RGMII" }, 281 { 7, 3, 0, "CPU Frequency : 1.2GHz" }, 282 { 7, 3, 1, "CPU Frequency : 1.6MHz" }, 283 { 7, 3, 2, "CPU Frequency : 1.2GHz" }, 284 { 7, 3, 3, "CPU Frequency : 1.6GHz" }, 285 { 7, 3, 4, "CPU Frequency : 800MHz" }, 286 { 7, 3, 5, "CPU Frequency : 800MHz" }, 287 { 7, 3, 6, "CPU Frequency : 800MHz" }, 288 { 7, 3, 7, "CPU Frequency : 800MHz" }, 289 { 10, 2, 0, "HCLK ratio AXI:AHB = 2:1" }, 290 { 10, 2, 1, "HCLK ratio AXI:AHB = 2:1" }, 291 { 10, 2, 2, "HCLK ratio AXI:AHB = 3:1" }, 292 { 10, 2, 3, "HCLK ratio AXI:AHB = 4:1" }, 293 { 12, 2, 0, "VGA memory size : 8MB" }, 294 { 12, 2, 1, "VGA memory size : 16MB" }, 295 { 12, 2, 2, "VGA memory size : 32MB" }, 296 { 12, 2, 3, "VGA memory size : 64MB" }, 297 { 14, 3, OTP_REG_RESERVED, "" }, 298 { 17, 1, 0, "VGA class code : Class Code for video device" }, 299 { 17, 1, 1, "VGA class code : Class Code for VGA device" }, 300 { 18, 1, 0, "Enable debug interfaces 0" }, 301 { 18, 1, 1, "Disable debug interfaces 0" }, 302 { 19, 1, 0, "Boot from emmc mode : High eMMC speed" }, 303 { 19, 1, 1, "Boot from emmc mode : Normal eMMC speed" }, 304 { 20, 1, 0, "Disable Pcie EHCI device" }, 305 { 20, 1, 1, "Enable Pcie EHCI device" }, 306 { 21, 1, 0, "Enable VGA XDMA function" }, 307 { 21, 1, 1, "Disable VGA XDMA function" }, 308 { 22, 1, 0, "Normal BMC mode" }, 309 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" }, 310 { 23, 1, 0, "SSPRST# pin is for secondary processor dedicated reset pin" }, 311 { 23, 1, 1, "SSPRST# pin is for PCIE root complex dedicated reset pin" }, 312 { 24, 1, 0, "Enable watchdog to reset full chip" }, 313 { 24, 1, 1, "Disable watchdog to reset full chip" }, 314 { 25, 5, OTP_REG_RESERVED, "" }, 315 { 30, 2, OTP_REG_RESERVED, "" }, 316 { 32, 1, 0, "MAC 3 : RMII/NCSI" }, 317 { 32, 1, 1, "MAC 3 : RGMII" }, 318 { 33, 1, 0, "MAC 4 : RMII/NCSI" }, 319 { 33, 1, 1, "MAC 4 : RGMII" }, 320 { 34, 1, 0, "SuperIO configuration address : 0x2E" }, 321 { 34, 1, 1, "SuperIO configuration address : 0x4E" }, 322 { 35, 1, 0, "Enable LPC to decode SuperIO" }, 323 { 35, 1, 1, "Disable LPC to decode SuperIO" }, 324 { 36, 1, 0, "Enable debug interfaces 1" }, 325 { 36, 1, 1, "Disable debug interfaces 1" }, 326 { 37, 1, 0, "Disable ACPI function" }, 327 { 37, 1, 1, "Enable ACPI function" }, 328 { 38, 1, 0, "Enable eSPI mode" }, 329 { 38, 1, 1, "Enable LPC mode" }, 330 { 39, 1, 0, "Enable SAFS mode" }, 331 { 39, 1, 1, "Enable SAFS mode" }, 332 { 40, 2, OTP_REG_RESERVED, "" }, 333 { 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" }, 334 { 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" }, 335 { 43, 1, 0, "Disable boot SPI ABR" }, 336 { 43, 1, 1, "Enable boot SPI ABR" }, 337 { 44, 1, 0, "Boot SPI ABR mode : dual SPI flash" }, 338 { 44, 1, 1, "Boot SPI ABR mode : single SPI flash" }, 339 { 45, 3, 0, "Boot SPI flash size : no define size" }, 340 { 45, 3, 1, "Boot SPI flash size : 2MB" }, 341 { 45, 3, 2, "Boot SPI flash size : 4MB" }, 342 { 45, 3, 3, "Boot SPI flash size : 8MB" }, 343 { 45, 3, 4, "Boot SPI flash size : 16MB" }, 344 { 45, 3, 5, "Boot SPI flash size : 32MB" }, 345 { 45, 3, 6, "Boot SPI flash size : 64MB" }, 346 { 45, 3, 7, "Boot SPI flash size : 128MB" }, 347 { 48, 1, 0, "Disable host SPI ABR" }, 348 { 48, 1, 1, "Enable host SPI ABR" }, 349 { 49, 1, 0, "Disable host SPI ABR mode select pin" }, 350 { 49, 1, 1, "Enable host SPI ABR mode select pin" }, 351 { 50, 1, 0, "Host SPI ABR mode : dual SPI flash" }, 352 { 50, 1, 1, "Host SPI ABR mode : single SPI flash" }, 353 { 51, 3, 0, "Host SPI flash size : no define size" }, 354 { 51, 3, 1, "Host SPI flash size : 2MB" }, 355 { 51, 3, 2, "Host SPI flash size : 4MB" }, 356 { 51, 3, 3, "Host SPI flash size : 8MB" }, 357 { 51, 3, 4, "Host SPI flash size : 16MB" }, 358 { 51, 3, 5, "Host SPI flash size : 32MB" }, 359 { 51, 3, 6, "Host SPI flash size : 64MB" }, 360 { 51, 3, 7, "Host SPI flash size : 128MB" }, 361 { 54, 1, 0, "Disable boot SPI auxiliary control pins" }, 362 { 54, 1, 1, "Enable boot SPI auxiliary control pins" }, 363 { 55, 2, 0, "Boot SPI CRTM size : disable CRTM" }, 364 { 55, 2, 1, "Boot SPI CRTM size : 256KB" }, 365 { 55, 2, 2, "Boot SPI CRTM size : 512KB" }, 366 { 55, 2, 3, "Boot SPI CRTM size : 1MB" }, 367 { 57, 2, 0, "Host SPI CRTM size : disable CRTM" }, 368 { 57, 2, 1, "Host SPI CRTM size : 256KB" }, 369 { 57, 2, 2, "Host SPI CRTM size : 512KB" }, 370 { 57, 2, 3, "Host SPI CRTM size : 1MB" }, 371 { 59, 1, 0, "Disable host SPI auxiliary control pins" }, 372 { 59, 1, 1, "Enable host SPI auxiliary control pins" }, 373 { 60, 1, 0, "Disable GPIO pass through" }, 374 { 60, 1, 1, "Enable GPIO pass through" }, 375 { 61, 1, 0, "Enable low security secure boot key" }, 376 { 61, 1, 1, "Disable low security secure boot key" }, 377 { 62, 1, 0, "Disable dedicate GPIO strap pins" }, 378 { 62, 1, 1, "Enable dedicate GPIO strap pins" }, 379 { 63, 1, OTP_REG_RESERVED, "" } 380 }; 381 382 static const struct otpstrap_info a2_strap_info[] = { 383 { 0, 1, 0, "Disable secure boot" }, 384 { 0, 1, 1, "Enable secure boot" }, 385 { 1, 1, 0, "Disable boot from eMMC" }, 386 { 1, 1, 1, "Enable boot from eMMC" }, 387 { 2, 1, 0, "Disable Boot from debug SPI" }, 388 { 2, 1, 1, "Enable Boot from debug SPI" }, 389 { 3, 1, 0, "Enable ARM CM3" }, 390 { 3, 1, 1, "Disable ARM CM3" }, 391 { 4, 1, 0, "No VGA BIOS ROM, VGA BIOS is merged in the system BIOS" }, 392 { 4, 1, 1, "Enable dedicated VGA BIOS ROM" }, 393 { 5, 1, 0, "MAC 1 : RMII/NCSI" }, 394 { 5, 1, 1, "MAC 1 : RGMII" }, 395 { 6, 1, 0, "MAC 2 : RMII/NCSI" }, 396 { 6, 1, 1, "MAC 2 : RGMII" }, 397 { 7, 3, 0, "CPU Frequency : 1.2GHz" }, 398 { 7, 3, 1, "CPU Frequency : 1.6MHz" }, 399 { 7, 3, 2, "CPU Frequency : 1.2GHz" }, 400 { 7, 3, 3, "CPU Frequency : 1.6GHz" }, 401 { 7, 3, 4, "CPU Frequency : 800MHz" }, 402 { 7, 3, 5, "CPU Frequency : 800MHz" }, 403 { 7, 3, 6, "CPU Frequency : 800MHz" }, 404 { 7, 3, 7, "CPU Frequency : 800MHz" }, 405 { 10, 2, 0, "HCLK ratio AXI:AHB = 2:1" }, 406 { 10, 2, 1, "HCLK ratio AXI:AHB = 2:1" }, 407 { 10, 2, 2, "HCLK ratio AXI:AHB = 3:1" }, 408 { 10, 2, 3, "HCLK ratio AXI:AHB = 4:1" }, 409 { 12, 2, 0, "VGA memory size : 8MB" }, 410 { 12, 2, 1, "VGA memory size : 16MB" }, 411 { 12, 2, 2, "VGA memory size : 32MB" }, 412 { 12, 2, 3, "VGA memory size : 64MB" }, 413 { 14, 3, OTP_REG_RESERVED, "" }, 414 { 17, 1, 0, "VGA class code : Class Code for video device" }, 415 { 17, 1, 1, "VGA class code : Class Code for VGA device" }, 416 { 18, 1, 0, "Enable debug interfaces 0" }, 417 { 18, 1, 1, "Disable debug interfaces 0" }, 418 { 19, 1, 0, "Boot from emmc mode : High eMMC speed" }, 419 { 19, 1, 1, "Boot from emmc mode : Normal eMMC speed" }, 420 { 20, 1, 0, "Disable Pcie EHCI device" }, 421 { 20, 1, 1, "Enable Pcie EHCI device" }, 422 { 21, 1, 0, "Enable VGA XDMA function" }, 423 { 21, 1, 1, "Disable VGA XDMA function" }, 424 { 22, 1, 0, "Normal BMC mode" }, 425 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" }, 426 { 23, 1, 0, "SSPRST# pin is for secondary processor dedicated reset pin" }, 427 { 23, 1, 1, "SSPRST# pin is for PCIE root complex dedicated reset pin" }, 428 { 24, 1, 0, "Enable watchdog to reset full chip" }, 429 { 24, 1, 1, "Disable watchdog to reset full chip" }, 430 { 25, 5, OTP_REG_RESERVED, "" }, 431 { 30, 2, OTP_REG_RESERVED, "" }, 432 { 32, 1, 0, "MAC 3 : RMII/NCSI" }, 433 { 32, 1, 1, "MAC 3 : RGMII" }, 434 { 33, 1, 0, "MAC 4 : RMII/NCSI" }, 435 { 33, 1, 1, "MAC 4 : RGMII" }, 436 { 34, 1, 0, "SuperIO configuration address : 0x2E" }, 437 { 34, 1, 1, "SuperIO configuration address : 0x4E" }, 438 { 35, 1, 0, "Enable LPC to decode SuperIO" }, 439 { 35, 1, 1, "Disable LPC to decode SuperIO" }, 440 { 36, 1, 0, "Enable debug interfaces 1" }, 441 { 36, 1, 1, "Disable debug interfaces 1" }, 442 { 37, 1, 0, "Disable ACPI function" }, 443 { 37, 1, 1, "Enable ACPI function" }, 444 { 38, 1, 0, "Enable eSPI mode" }, 445 { 38, 1, 1, "Enable LPC mode" }, 446 { 39, 1, 0, "Enable SAFS mode" }, 447 { 39, 1, 1, "Enable SAFS mode" }, 448 { 40, 2, OTP_REG_RESERVED, "" }, 449 { 42, 1, 0, "Disable boot SPI 3B/4B address mode auto detection" }, 450 { 42, 1, 1, "Enable boot SPI 3B/4B address mode auto detection" }, 451 { 43, 1, 0, "Disable boot SPI ABR" }, 452 { 43, 1, 1, "Enable boot SPI ABR" }, 453 { 44, 1, 0, "Boot SPI ABR mode : dual SPI flash" }, 454 { 44, 1, 1, "Boot SPI ABR mode : single SPI flash" }, 455 { 45, 3, 0, "Boot SPI flash size : no define size" }, 456 { 45, 3, 1, "Boot SPI flash size : 2MB" }, 457 { 45, 3, 2, "Boot SPI flash size : 4MB" }, 458 { 45, 3, 3, "Boot SPI flash size : 8MB" }, 459 { 45, 3, 4, "Boot SPI flash size : 16MB" }, 460 { 45, 3, 5, "Boot SPI flash size : 32MB" }, 461 { 45, 3, 6, "Boot SPI flash size : 64MB" }, 462 { 45, 3, 7, "Boot SPI flash size : 128MB" }, 463 { 48, 1, 0, "Disable host SPI ABR" }, 464 { 48, 1, 1, "Enable host SPI ABR" }, 465 { 49, 1, 0, "Disable host SPI ABR mode select pin" }, 466 { 49, 1, 1, "Enable host SPI ABR mode select pin" }, 467 { 50, 1, 0, "Host SPI ABR mode : dual SPI flash" }, 468 { 50, 1, 1, "Host SPI ABR mode : single SPI flash" }, 469 { 51, 3, 0, "Host SPI flash size : no define size" }, 470 { 51, 3, 1, "Host SPI flash size : 2MB" }, 471 { 51, 3, 2, "Host SPI flash size : 4MB" }, 472 { 51, 3, 3, "Host SPI flash size : 8MB" }, 473 { 51, 3, 4, "Host SPI flash size : 16MB" }, 474 { 51, 3, 5, "Host SPI flash size : 32MB" }, 475 { 51, 3, 6, "Host SPI flash size : 64MB" }, 476 { 51, 3, 7, "Host SPI flash size : 128MB" }, 477 { 54, 1, 0, "Disable boot SPI auxiliary control pins" }, 478 { 54, 1, 1, "Enable boot SPI auxiliary control pins" }, 479 { 55, 2, 0, "Boot SPI CRTM size : disable CRTM" }, 480 { 55, 2, 1, "Boot SPI CRTM size : 256KB" }, 481 { 55, 2, 2, "Boot SPI CRTM size : 512KB" }, 482 { 55, 2, 3, "Boot SPI CRTM size : 1MB" }, 483 { 57, 2, 0, "Host SPI CRTM size : disable CRTM" }, 484 { 57, 2, 1, "Host SPI CRTM size : 256KB" }, 485 { 57, 2, 2, "Host SPI CRTM size : 512KB" }, 486 { 57, 2, 3, "Host SPI CRTM size : 1MB" }, 487 { 59, 1, 0, "Disable host SPI auxiliary control pins" }, 488 { 59, 1, 1, "Enable host SPI auxiliary control pins" }, 489 { 60, 1, 0, "Disable GPIO pass through" }, 490 { 60, 1, 1, "Enable GPIO pass through" }, 491 { 61, 1, 0, "Enable low security secure boot key" }, 492 { 61, 1, 1, "Disable low security secure boot key" }, 493 { 62, 1, 0, "Disable dedicate GPIO strap pins" }, 494 { 62, 1, 1, "Enable dedicate GPIO strap pins" }, 495 { 63, 1, OTP_REG_RESERVED, "" } 496 }; 497 498 static const struct otpconf_info a0_conf_info[] = { 499 { 0, 0, 1, 0, "Enable Secure Region programming" }, 500 { 0, 0, 1, 1, "Disable Secure Region programming" }, 501 { 0, 1, 1, 0, "Disable Secure Boot" }, 502 { 0, 1, 1, 1, "Enable Secure Boot" }, 503 { 0, 2, 1, 0, "Initialization programming not done" }, 504 { 0, 2, 1, 1, "Initialization programming done" }, 505 { 0, 3, 1, 0, "User region ECC disable" }, 506 { 0, 3, 1, 1, "User region ECC enable" }, 507 { 0, 4, 1, 0, "Secure Region ECC disable" }, 508 { 0, 4, 1, 1, "Secure Region ECC enable" }, 509 { 0, 5, 1, 0, "Enable low security key" }, 510 { 0, 5, 1, 1, "Disable low security key" }, 511 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" }, 512 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" }, 513 { 0, 7, 1, 0, "Secure Boot Mode: 1" }, 514 { 0, 7, 1, 1, "Secure Boot Mode: 2" }, 515 { 0, 8, 2, 0, "Single cell mode (recommended)" }, 516 { 0, 8, 2, 1, "Differential mode" }, 517 { 0, 8, 2, 2, "Differential-redundant mode" }, 518 { 0, 10, 2, 0, "RSA mode : RSA1024" }, 519 { 0, 10, 2, 1, "RSA mode : RSA2048" }, 520 { 0, 10, 2, 2, "RSA mode : RSA3072" }, 521 { 0, 10, 2, 3, "RSA mode : RSA4096" }, 522 { 0, 12, 2, 0, "SHA mode : SHA224" }, 523 { 0, 12, 2, 1, "SHA mode : SHA256" }, 524 { 0, 12, 2, 2, "SHA mode : SHA384" }, 525 { 0, 12, 2, 3, "SHA mode : SHA512" }, 526 { 0, 14, 2, OTP_REG_RESERVED, "" }, 527 { 0, 16, 6, OTP_REG_VALUE, "Secure Region size (DW): 0x%x" }, 528 { 0, 22, 1, 0, "Secure Region : Writable" }, 529 { 0, 22, 1, 1, "Secure Region : Write Protect" }, 530 { 0, 23, 1, 0, "User Region : Writable" }, 531 { 0, 23, 1, 1, "User Region : Write Protect" }, 532 { 0, 24, 1, 0, "Configure Region : Writable" }, 533 { 0, 24, 1, 1, "Configure Region : Write Protect" }, 534 { 0, 25, 1, 0, "OTP strap Region : Writable" }, 535 { 0, 25, 1, 1, "OTP strap Region : Write Protect" }, 536 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" }, 537 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" }, 538 { 0, 27, 1, 0, "Disable image encryption" }, 539 { 0, 27, 1, 1, "Enable image encryption" }, 540 { 0, 28, 1, OTP_REG_RESERVED, "" }, 541 { 0, 29, 1, 0, "OTP key retire Region : Writable" }, 542 { 0, 29, 1, 1, "OTP key retire Region : Write Protect" }, 543 { 0, 30, 1, 0, "Data region redundancy repair disable" }, 544 { 0, 30, 1, 1, "Data region redundancy repair enable" }, 545 { 0, 31, 1, 0, "OTP memory lock disable" }, 546 { 0, 31, 1, 1, "OTP memory lock enable" }, 547 { 2, 0, 16, OTP_REG_VALUE, "Vender ID : 0x%x" }, 548 { 2, 16, 16, OTP_REG_VALUE, "Key Revision : 0x%x" }, 549 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" }, 550 { 4, 0, 8, OTP_REG_VALID_BIT, "Keys valid : %s" }, 551 { 4, 16, 8, OTP_REG_VALID_BIT, "Keys retire : %s" }, 552 { 5, 0, 32, OTP_REG_VALUE, "User define data, random number low : 0x%x" }, 553 { 6, 0, 32, OTP_REG_VALUE, "User define data, random number high : 0x%x" }, 554 { 7, 0, 1, 0, "Force enable PCI bus to AHB bus bridge" }, 555 { 7, 0, 1, 1, "Force disable PCI bus to AHB bus bridge" }, 556 { 7, 1, 1, 0, "Force enable UART5 debug port function" }, 557 { 7, 1, 1, 1, "Force disable UART5 debug port function" }, 558 { 7, 2, 1, 0, "Force enable XDMA function" }, 559 { 7, 2, 1, 1, "Force disable XDMA function" }, 560 { 7, 3, 1, 0, "Force enable APB to PCIE device bridge" }, 561 { 7, 3, 1, 1, "Force disable APB to PCIE device bridge" }, 562 { 7, 4, 1, 0, "Force enable APB to PCIE bridge config access" }, 563 { 7, 4, 1, 1, "Force disable APB to PCIE bridge config access" }, 564 { 7, 5, 1, 0, "Force enable PCIE bus trace buffer" }, 565 { 7, 5, 1, 1, "Force disable PCIE bus trace buffer" }, 566 { 7, 6, 1, 0, "Force enable the capability for PCIE device port as a Root Complex" }, 567 { 7, 6, 1, 1, "Force disable the capability for PCIE device port as a Root Complex" }, 568 { 7, 16, 1, 0, "Force enable ESPI bus to AHB bus bridge" }, 569 { 7, 16, 1, 1, "Force disable ESPI bus to AHB bus bridge" }, 570 { 7, 17, 1, 0, "Force enable LPC bus to AHB bus bridge1" }, 571 { 7, 17, 1, 1, "Force disable LPC bus to AHB bus bridge1" }, 572 { 7, 18, 1, 0, "Force enable LPC bus to AHB bus bridge2" }, 573 { 7, 18, 1, 1, "Force disable LPC bus to AHB bus bridge2" }, 574 { 7, 19, 1, 0, "Force enable UART1 debug port function" }, 575 { 7, 19, 1, 1, "Force disable UART1 debug port function" }, 576 { 7, 31, 1, 0, "Disable chip security setting" }, 577 { 7, 31, 1, 1, "Enable chip security setting" }, 578 { 8, 0, 32, OTP_REG_VALUE, "Redundancy Repair : 0x%x" }, 579 { 10, 0, 32, OTP_REG_VALUE, "Manifest ID low : 0x%x" }, 580 { 11, 0, 32, OTP_REG_VALUE, "Manifest ID high : 0x%x" } 581 }; 582 583 static const struct otpconf_info a1_conf_info[] = { 584 { 0, 0, 1, OTP_REG_RESERVED, "" }, 585 { 0, 1, 1, 0, "Disable Secure Boot" }, 586 { 0, 1, 1, 1, "Enable Secure Boot" }, 587 { 0, 2, 1, 0, "Initialization programming not done" }, 588 { 0, 2, 1, 1, "Initialization programming done" }, 589 { 0, 3, 1, 0, "User region ECC disable" }, 590 { 0, 3, 1, 1, "User region ECC enable" }, 591 { 0, 4, 1, 0, "Secure Region ECC disable" }, 592 { 0, 4, 1, 1, "Secure Region ECC enable" }, 593 { 0, 5, 1, 0, "Enable low security key" }, 594 { 0, 5, 1, 1, "Disable low security key" }, 595 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" }, 596 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" }, 597 { 0, 7, 1, 0, "Secure Boot Mode: GCM" }, 598 { 0, 7, 1, 1, "Secure Boot Mode: 2" }, 599 { 0, 8, 2, 0, "Single cell mode (recommended)" }, 600 { 0, 8, 2, 1, "Differential mode" }, 601 { 0, 8, 2, 2, "Differential-redundant mode" }, 602 { 0, 10, 2, 0, "RSA mode : RSA1024" }, 603 { 0, 10, 2, 1, "RSA mode : RSA2048" }, 604 { 0, 10, 2, 2, "RSA mode : RSA3072" }, 605 { 0, 10, 2, 3, "RSA mode : RSA4096" }, 606 { 0, 12, 2, 0, "SHA mode : SHA224" }, 607 { 0, 12, 2, 1, "SHA mode : SHA256" }, 608 { 0, 12, 2, 2, "SHA mode : SHA384" }, 609 { 0, 12, 2, 3, "SHA mode : SHA512" }, 610 { 0, 14, 1, 0, "Disable Patch code" }, 611 { 0, 14, 1, 1, "Enable Patch code" }, 612 { 0, 15, 1, OTP_REG_RESERVED, "" }, 613 { 0, 16, 6, OTP_REG_VALUE, "Secure Region size (DW): 0x%x" }, 614 { 0, 22, 1, 0, "Secure Region : Writable" }, 615 { 0, 22, 1, 1, "Secure Region : Write Protect" }, 616 { 0, 23, 1, 0, "User Region : Writable" }, 617 { 0, 23, 1, 1, "User Region : Write Protect" }, 618 { 0, 24, 1, 0, "Configure Region : Writable" }, 619 { 0, 24, 1, 1, "Configure Region : Write Protect" }, 620 { 0, 25, 1, 0, "OTP strap Region : Writable" }, 621 { 0, 25, 1, 1, "OTP strap Region : Write Protect" }, 622 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" }, 623 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" }, 624 { 0, 27, 1, 0, "Disable image encryption" }, 625 { 0, 27, 1, 1, "Enable image encryption" }, 626 { 0, 28, 1, OTP_REG_RESERVED, "" }, 627 { 0, 29, 1, 0, "OTP key retire Region : Writable" }, 628 { 0, 29, 1, 1, "OTP key retire Region : Write Protect" }, 629 { 0, 30, 1, 0, "Data region redundancy repair disable" }, 630 { 0, 30, 1, 1, "Data region redundancy repair enable" }, 631 { 0, 31, 1, 0, "OTP memory lock disable" }, 632 { 0, 31, 1, 1, "OTP memory lock enable" }, 633 { 2, 0, 16, OTP_REG_VALUE, "Vender ID : 0x%x" }, 634 { 2, 16, 16, OTP_REG_VALUE, "Key Revision : 0x%x" }, 635 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" }, 636 { 4, 0, 8, OTP_REG_VALID_BIT, "Keys valid : %s" }, 637 { 4, 16, 8, OTP_REG_VALID_BIT, "Keys retire : %s" }, 638 { 5, 0, 32, OTP_REG_VALUE, "User define data, random number low : 0x%x" }, 639 { 6, 0, 32, OTP_REG_VALUE, "User define data, random number high : 0x%x" }, 640 { 7, 0, 1, 0, "Force enable PCI bus to AHB bus bridge" }, 641 { 7, 0, 1, 1, "Force disable PCI bus to AHB bus bridge" }, 642 { 7, 1, 1, 0, "Force enable UART5 debug port function" }, 643 { 7, 1, 1, 1, "Force disable UART5 debug port function" }, 644 { 7, 2, 1, 0, "Force enable XDMA function" }, 645 { 7, 2, 1, 1, "Force disable XDMA function" }, 646 { 7, 3, 1, 0, "Force enable APB to PCIE device bridge" }, 647 { 7, 3, 1, 1, "Force disable APB to PCIE device bridge" }, 648 { 7, 4, 1, 0, "Force enable APB to PCIE bridge config access" }, 649 { 7, 4, 1, 1, "Force disable APB to PCIE bridge config access" }, 650 { 7, 5, 1, 0, "Force enable PCIE bus trace buffer" }, 651 { 7, 5, 1, 1, "Force disable PCIE bus trace buffer" }, 652 { 7, 6, 1, 0, "Force enable the capability for PCIE device port as a Root Complex" }, 653 { 7, 6, 1, 1, "Force disable the capability for PCIE device port as a Root Complex" }, 654 { 7, 16, 1, 0, "Force enable ESPI bus to AHB bus bridge" }, 655 { 7, 16, 1, 1, "Force disable ESPI bus to AHB bus bridge" }, 656 { 7, 17, 1, 0, "Force enable LPC bus to AHB bus bridge1" }, 657 { 7, 17, 1, 1, "Force disable LPC bus to AHB bus bridge1" }, 658 { 7, 18, 1, 0, "Force enable LPC bus to AHB bus bridge2" }, 659 { 7, 18, 1, 1, "Force disable LPC bus to AHB bus bridge2" }, 660 { 7, 19, 1, 0, "Force enable UART1 debug port function" }, 661 { 7, 19, 1, 1, "Force disable UART1 debug port function" }, 662 { 7, 31, 1, 0, "Disable chip security setting" }, 663 { 7, 31, 1, 1, "Enable chip security setting" }, 664 { 8, 0, 32, OTP_REG_VALUE, "Redundancy Repair : 0x%x" }, 665 { 10, 0, 32, OTP_REG_VALUE, "Manifest ID low : 0x%x" }, 666 { 11, 0, 32, OTP_REG_VALUE, "Manifest ID high : 0x%x" }, 667 { 14, 0, 11, OTP_REG_VALUE, "Patch code location (DW): 0x%x" }, 668 { 14, 11, 6, OTP_REG_VALUE, "Patch code size (DW): 0x%x" } 669 }; 670 671 static const struct otpconf_info a2_conf_info[] = { 672 { 0, 0, 1, OTP_REG_RESERVED, "" }, 673 { 0, 1, 1, 0, "Disable Secure Boot" }, 674 { 0, 1, 1, 1, "Enable Secure Boot" }, 675 { 0, 2, 1, 0, "Initialization programming not done" }, 676 { 0, 2, 1, 1, "Initialization programming done" }, 677 { 0, 3, 1, 0, "User region ECC disable" }, 678 { 0, 3, 1, 1, "User region ECC enable" }, 679 { 0, 4, 1, 0, "Secure Region ECC disable" }, 680 { 0, 4, 1, 1, "Secure Region ECC enable" }, 681 { 0, 5, 1, 0, "Enable low security key" }, 682 { 0, 5, 1, 1, "Disable low security key" }, 683 { 0, 6, 1, 0, "Do not ignore Secure Boot hardware strap" }, 684 { 0, 6, 1, 1, "Ignore Secure Boot hardware strap" }, 685 { 0, 7, 1, 0, "Secure Boot Mode: GCM" }, 686 { 0, 7, 1, 1, "Secure Boot Mode: 2" }, 687 { 0, 8, 2, 0, "Single cell mode (recommended)" }, 688 { 0, 8, 2, 1, "Differential mode" }, 689 { 0, 8, 2, 2, "Differential-redundant mode" }, 690 { 0, 10, 2, 0, "RSA mode : RSA1024" }, 691 { 0, 10, 2, 1, "RSA mode : RSA2048" }, 692 { 0, 10, 2, 2, "RSA mode : RSA3072" }, 693 { 0, 10, 2, 3, "RSA mode : RSA4096" }, 694 { 0, 12, 2, 0, "SHA mode : SHA224" }, 695 { 0, 12, 2, 1, "SHA mode : SHA256" }, 696 { 0, 12, 2, 2, "SHA mode : SHA384" }, 697 { 0, 12, 2, 3, "SHA mode : SHA512" }, 698 { 0, 14, 1, 0, "Disable Patch code" }, 699 { 0, 14, 1, 1, "Enable Patch code" }, 700 { 0, 15, 1, OTP_REG_RESERVED, "" }, 701 { 0, 16, 6, OTP_REG_VALUE, "Secure Region size (DW): 0x%x" }, 702 { 0, 22, 1, 0, "Secure Region : Writable" }, 703 { 0, 22, 1, 1, "Secure Region : Write Protect" }, 704 { 0, 23, 1, 0, "User Region : Writable" }, 705 { 0, 23, 1, 1, "User Region : Write Protect" }, 706 { 0, 24, 1, 0, "Configure Region : Writable" }, 707 { 0, 24, 1, 1, "Configure Region : Write Protect" }, 708 { 0, 25, 1, 0, "OTP strap Region : Writable" }, 709 { 0, 25, 1, 1, "OTP strap Region : Write Protect" }, 710 { 0, 26, 1, 0, "Disable Copy Boot Image to Internal SRAM" }, 711 { 0, 26, 1, 1, "Copy Boot Image to Internal SRAM" }, 712 { 0, 27, 1, 0, "Disable image encryption" }, 713 { 0, 27, 1, 1, "Enable image encryption" }, 714 { 0, 28, 1, OTP_REG_RESERVED, "" }, 715 { 0, 29, 1, 0, "OTP key retire Region : Writable" }, 716 { 0, 29, 1, 1, "OTP key retire Region : Write Protect" }, 717 { 0, 30, 1, 0, "Data region redundancy repair disable" }, 718 { 0, 30, 1, 1, "Data region redundancy repair enable" }, 719 { 0, 31, 1, 0, "OTP memory lock disable" }, 720 { 0, 31, 1, 1, "OTP memory lock enable" }, 721 { 2, 0, 16, OTP_REG_VALUE, "Vender ID : 0x%x" }, 722 { 2, 16, 16, OTP_REG_VALUE, "Key Revision : 0x%x" }, 723 { 3, 0, 16, OTP_REG_VALUE, "Secure boot header offset : 0x%x" }, 724 { 4, 0, 8, OTP_REG_VALID_BIT, "Keys valid : %s" }, 725 { 4, 16, 8, OTP_REG_VALID_BIT, "Keys retire : %s" }, 726 { 5, 0, 32, OTP_REG_VALUE, "User define data, random number low : 0x%x" }, 727 { 6, 0, 32, OTP_REG_VALUE, "User define data, random number high : 0x%x" }, 728 { 7, 0, 1, 0, "Force enable PCI bus to AHB bus bridge" }, 729 { 7, 0, 1, 1, "Force disable PCI bus to AHB bus bridge" }, 730 { 7, 1, 1, 0, "Force enable UART5 debug port function" }, 731 { 7, 1, 1, 1, "Force disable UART5 debug port function" }, 732 { 7, 2, 1, 0, "Force enable XDMA function" }, 733 { 7, 2, 1, 1, "Force disable XDMA function" }, 734 { 7, 3, 1, 0, "Force enable APB to PCIE device bridge" }, 735 { 7, 3, 1, 1, "Force disable APB to PCIE device bridge" }, 736 { 7, 4, 1, 0, "Force enable APB to PCIE bridge config access" }, 737 { 7, 4, 1, 1, "Force disable APB to PCIE bridge config access" }, 738 { 7, 5, 1, 0, "Force enable PCIE bus trace buffer" }, 739 { 7, 5, 1, 1, "Force disable PCIE bus trace buffer" }, 740 { 7, 6, 1, 0, "Force enable the capability for PCIE device port as a Root Complex" }, 741 { 7, 6, 1, 1, "Force disable the capability for PCIE device port as a Root Complex" }, 742 { 7, 16, 1, 0, "Force enable ESPI bus to AHB bus bridge" }, 743 { 7, 16, 1, 1, "Force disable ESPI bus to AHB bus bridge" }, 744 { 7, 17, 1, 0, "Force enable LPC bus to AHB bus bridge1" }, 745 { 7, 17, 1, 1, "Force disable LPC bus to AHB bus bridge1" }, 746 { 7, 18, 1, 0, "Force enable LPC bus to AHB bus bridge2" }, 747 { 7, 18, 1, 1, "Force disable LPC bus to AHB bus bridge2" }, 748 { 7, 19, 1, 0, "Force enable UART1 debug port function" }, 749 { 7, 19, 1, 1, "Force disable UART1 debug port function" }, 750 { 7, 31, 1, 0, "Disable chip security setting" }, 751 { 7, 31, 1, 1, "Enable chip security setting" }, 752 { 8, 0, 32, OTP_REG_VALUE, "Redundancy Repair : 0x%x" }, 753 { 10, 0, 32, OTP_REG_VALUE, "Manifest ID low : 0x%x" }, 754 { 11, 0, 32, OTP_REG_VALUE, "Manifest ID high : 0x%x" }, 755 { 14, 0, 11, OTP_REG_VALUE, "Patch code location (DW): 0x%x" }, 756 { 14, 11, 6, OTP_REG_VALUE, "Patch code size (DW): 0x%x" } 757 }; 758 759 static const struct otpkey_type a0_key_type[] = { 760 {0, OTP_KEY_TYPE_AES, 0, "AES-256 as OEM platform key for image encryption/decryption"}, 761 {1, OTP_KEY_TYPE_VAULT, 0, "AES-256 as secret vault key"}, 762 {4, OTP_KEY_TYPE_HMAC, 1, "HMAC as encrypted OEM HMAC keys in Mode 1"}, 763 {8, OTP_KEY_TYPE_RSA, 1, "RSA-public as OEM DSS public keys in Mode 2"}, 764 {9, OTP_KEY_TYPE_RSA, 0, "RSA-public as SOC public key"}, 765 {10, OTP_KEY_TYPE_RSA, 0, "RSA-public as AES key decryption key"}, 766 {13, OTP_KEY_TYPE_RSA, 0, "RSA-private as SOC private key"}, 767 {14, OTP_KEY_TYPE_RSA, 0, "RSA-private as AES key decryption key"}, 768 }; 769 770 static const struct otpkey_type a1_key_type[] = { 771 {1, OTP_KEY_TYPE_VAULT, 0, "AES-256 as secret vault key"}, 772 {2, OTP_KEY_TYPE_AES, 1, "AES-256 as OEM platform key for image encryption/decryption in Mode 2 or AES-256 as OEM DSS keys for Mode GCM"}, 773 {8, OTP_KEY_TYPE_RSA, 1, "RSA-public as OEM DSS public keys in Mode 2"}, 774 {10, OTP_KEY_TYPE_RSA, 0, "RSA-public as AES key decryption key"}, 775 {14, OTP_KEY_TYPE_RSA, 0, "RSA-private as AES key decryption key"}, 776 }; 777 778 static const struct otpkey_type a2_key_type[] = { 779 {1, OTP_KEY_TYPE_VAULT, 0, "AES-256 as secret vault key"}, 780 {2, OTP_KEY_TYPE_AES, 1, "AES-256 as OEM platform key for image encryption/decryption in Mode 2 or AES-256 as OEM DSS keys for Mode GCM"}, 781 {8, OTP_KEY_TYPE_RSA, 1, "RSA-public as OEM DSS public keys in Mode 2"}, 782 {10, OTP_KEY_TYPE_RSA, 0, "RSA-public as AES key decryption key"}, 783 {14, OTP_KEY_TYPE_RSA, 0, "RSA-private as AES key decryption key"}, 784 }; 785 786 static uint32_t chip_version(void) 787 { 788 uint32_t rev_id; 789 790 rev_id = readl(0x1e6e2014); 791 792 if ((rev_id >> 24) & 0xf != 0x5) 793 return -1; 794 795 return (rev_id >> 16) & 0xf; 796 } 797 798 static void wait_complete(void) 799 { 800 int reg; 801 802 do { 803 reg = readl(OTP_STATUS); 804 } while ((reg & 0x6) != 0x6); 805 } 806 807 static void otp_read_data(uint32_t offset, uint32_t *data) 808 { 809 writel(offset, OTP_ADDR); //Read address 810 writel(0x23b1e361, OTP_COMMAND); //trigger read 811 wait_complete(); 812 data[0] = readl(OTP_COMPARE_1); 813 data[1] = readl(OTP_COMPARE_2); 814 } 815 816 static void otp_read_config(uint32_t offset, uint32_t *data) 817 { 818 int config_offset; 819 820 config_offset = 0x800; 821 config_offset |= (offset / 8) * 0x200; 822 config_offset |= (offset % 8) * 0x2; 823 824 writel(config_offset, OTP_ADDR); //Read address 825 writel(0x23b1e361, OTP_COMMAND); //trigger read 826 wait_complete(); 827 data[0] = readl(OTP_COMPARE_1); 828 } 829 830 static int otp_print_config(uint32_t offset, int dw_count) 831 { 832 int i; 833 uint32_t ret[1]; 834 835 if (offset + dw_count > 32) 836 return OTP_USAGE; 837 for (i = offset; i < offset + dw_count; i ++) { 838 otp_read_config(i, ret); 839 printf("OTPCFG%X: %08X\n", i, ret[0]); 840 } 841 printf("\n"); 842 return OTP_SUCCESS; 843 } 844 845 static int otp_print_data(uint32_t offset, int dw_count) 846 { 847 int i; 848 uint32_t ret[2]; 849 850 if (offset + dw_count > 2048 || offset % 4 != 0) 851 return OTP_USAGE; 852 for (i = offset; i < offset + dw_count; i += 2) { 853 otp_read_data(i, ret); 854 if (i % 4 == 0) 855 printf("%03X: %08X %08X ", i * 4, ret[0], ret[1]); 856 else 857 printf("%08X %08X\n", ret[0], ret[1]); 858 859 } 860 printf("\n"); 861 return OTP_SUCCESS; 862 } 863 864 static int otp_compare(uint32_t otp_addr, uint32_t addr) 865 { 866 uint32_t ret; 867 uint32_t *buf; 868 869 buf = map_physmem(addr, 16, MAP_WRBACK); 870 printf("%08X\n", buf[0]); 871 printf("%08X\n", buf[1]); 872 printf("%08X\n", buf[2]); 873 printf("%08X\n", buf[3]); 874 writel(otp_addr, OTP_ADDR); //Compare address 875 writel(buf[0], OTP_COMPARE_1); //Compare data 1 876 writel(buf[1], OTP_COMPARE_2); //Compare data 2 877 writel(buf[2], OTP_COMPARE_3); //Compare data 3 878 writel(buf[3], OTP_COMPARE_4); //Compare data 4 879 writel(0x23b1e363, OTP_COMMAND); //Compare command 880 wait_complete(); 881 ret = readl(OTP_STATUS); //Compare command 882 if (ret & 0x1) 883 return 0; 884 else 885 return -1; 886 } 887 888 static void otp_write(uint32_t otp_addr, uint32_t data) 889 { 890 writel(otp_addr, OTP_ADDR); //write address 891 writel(data, OTP_COMPARE_1); //write data 892 writel(0x23b1e362, OTP_COMMAND); //write command 893 wait_complete(); 894 } 895 896 static int verify_bit(uint32_t otp_addr, int bit_offset, int value) 897 { 898 uint32_t ret[2]; 899 900 if (otp_addr % 2 == 0) 901 writel(otp_addr, OTP_ADDR); //Read address 902 else 903 writel(otp_addr - 1, OTP_ADDR); //Read address 904 905 writel(0x23b1e361, OTP_COMMAND); //trigger read 906 wait_complete(); 907 ret[0] = readl(OTP_COMPARE_1); 908 ret[1] = readl(OTP_COMPARE_2); 909 910 if (otp_addr % 2 == 0) { 911 if (((ret[0] >> bit_offset) & 1) == value) 912 return 0; 913 else 914 return -1; 915 } else { 916 if (((ret[1] >> bit_offset) & 1) == value) 917 return 0; 918 else 919 return -1; 920 } 921 922 } 923 924 static uint32_t verify_dw(uint32_t otp_addr, uint32_t *value, uint32_t *ignore, uint32_t *compare, int size) 925 { 926 uint32_t ret[2]; 927 928 otp_addr &= ~(1 << 15); 929 930 if (otp_addr % 2 == 0) 931 writel(otp_addr, OTP_ADDR); //Read address 932 else 933 writel(otp_addr - 1, OTP_ADDR); //Read address 934 writel(0x23b1e361, OTP_COMMAND); //trigger read 935 wait_complete(); 936 ret[0] = readl(OTP_COMPARE_1); 937 ret[1] = readl(OTP_COMPARE_2); 938 if (size == 1) { 939 if (otp_addr % 2 == 0) { 940 // printf("check %x : %x = %x\n", otp_addr, ret[0], value[0]); 941 if ((value[0] & ~ignore[0]) == (ret[0] & ~ignore[0])) { 942 compare[0] = 0; 943 return 0; 944 } else { 945 compare[0] = value[0] ^ ret[0]; 946 return -1; 947 } 948 949 } else { 950 // printf("check %x : %x = %x\n", otp_addr, ret[1], value[0]); 951 if ((value[0] & ~ignore[0]) == (ret[1] & ~ignore[0])) { 952 compare[0] = ~0; 953 return 0; 954 } else { 955 compare[0] = ~(value[0] ^ ret[1]); 956 return -1; 957 } 958 } 959 } else if (size == 2) { 960 // otp_addr should be even 961 if ((value[0] & ~ignore[0]) == (ret[0] & ~ignore[0]) && (value[1] & ~ignore[1]) == (ret[1] & ~ignore[1])) { 962 // printf("check[0] %x : %x = %x\n", otp_addr, ret[0], value[0]); 963 // printf("check[1] %x : %x = %x\n", otp_addr, ret[1], value[1]); 964 compare[0] = 0; 965 compare[1] = ~0; 966 return 0; 967 } else { 968 // printf("check[0] %x : %x = %x\n", otp_addr, ret[0], value[0]); 969 // printf("check[1] %x : %x = %x\n", otp_addr, ret[1], value[1]); 970 compare[0] = value[0] ^ ret[0]; 971 compare[1] = ~(value[1] ^ ret[1]); 972 return -1; 973 } 974 } else { 975 return -1; 976 } 977 } 978 979 static void otp_soak(int soak) 980 { 981 switch (soak) { 982 case 0: //default 983 otp_write(0x3000, 0x0); // Write MRA 984 otp_write(0x5000, 0x0); // Write MRB 985 otp_write(0x1000, 0x0); // Write MR 986 break; 987 case 1: //normal program 988 otp_write(0x3000, 0x4021); // Write MRA 989 otp_write(0x5000, 0x302f); // Write MRB 990 otp_write(0x1000, 0x4020); // Write MR 991 writel(0x04190760, OTP_TIMING); 992 break; 993 case 2: //soak program 994 otp_write(0x3000, 0x4021); // Write MRA 995 otp_write(0x5000, 0x1027); // Write MRB 996 otp_write(0x1000, 0x4820); // Write MR 997 writel(0x041930d4, OTP_TIMING); 998 break; 999 } 1000 1001 wait_complete(); 1002 } 1003 1004 static void otp_prog(uint32_t otp_addr, uint32_t prog_bit) 1005 { 1006 writel(otp_addr, OTP_ADDR); //write address 1007 writel(prog_bit, OTP_COMPARE_1); //write data 1008 writel(0x23b1e364, OTP_COMMAND); //write command 1009 wait_complete(); 1010 } 1011 1012 static void _otp_prog_bit(uint32_t value, uint32_t prog_address, uint32_t bit_offset) 1013 { 1014 int prog_bit; 1015 1016 if (prog_address % 2 == 0) { 1017 if (value) 1018 prog_bit = ~(0x1 << bit_offset); 1019 else 1020 return; 1021 } else { 1022 prog_address |= 1 << 15; 1023 if (!value) 1024 prog_bit = 0x1 << bit_offset; 1025 else 1026 return; 1027 } 1028 otp_prog(prog_address, prog_bit); 1029 } 1030 1031 static int otp_prog_bit(uint32_t value, uint32_t prog_address, uint32_t bit_offset) 1032 { 1033 int pass; 1034 int i; 1035 1036 otp_soak(1); 1037 _otp_prog_bit(value, prog_address, bit_offset); 1038 pass = 0; 1039 1040 for (i = 0; i < RETRY; i++) { 1041 if (verify_bit(prog_address, bit_offset, value) != 0) { 1042 otp_soak(2); 1043 _otp_prog_bit(value, prog_address, bit_offset); 1044 if (verify_bit(prog_address, bit_offset, value) != 0) { 1045 otp_soak(1); 1046 } else { 1047 pass = 1; 1048 break; 1049 } 1050 } else { 1051 pass = 1; 1052 break; 1053 } 1054 } 1055 1056 return pass; 1057 } 1058 1059 static void otp_prog_dw(uint32_t value, uint32_t ignore, uint32_t prog_address) 1060 { 1061 int j, bit_value, prog_bit; 1062 1063 for (j = 0; j < 32; j++) { 1064 if ((ignore >> j) & 0x1) 1065 continue; 1066 bit_value = (value >> j) & 0x1; 1067 if (prog_address % 2 == 0) { 1068 if (bit_value) 1069 prog_bit = ~(0x1 << j); 1070 else 1071 continue; 1072 } else { 1073 prog_address |= 1 << 15; 1074 if (bit_value) 1075 continue; 1076 else 1077 prog_bit = 0x1 << j; 1078 } 1079 otp_prog(prog_address, prog_bit); 1080 } 1081 } 1082 1083 static int otp_prog_verify_2dw(uint32_t *data, uint32_t *buf, uint32_t *ignore_mask, uint32_t prog_address) 1084 { 1085 int pass; 1086 int i; 1087 uint32_t data0_masked; 1088 uint32_t data1_masked; 1089 uint32_t buf0_masked; 1090 uint32_t buf1_masked; 1091 uint32_t compare[2]; 1092 1093 data0_masked = data[0] & ~ignore_mask[0]; 1094 buf0_masked = buf[0] & ~ignore_mask[0]; 1095 data1_masked = data[1] & ~ignore_mask[1]; 1096 buf1_masked = buf[1] & ~ignore_mask[1]; 1097 if ((data0_masked == buf0_masked) && (data1_masked == buf1_masked)) 1098 return 0; 1099 1100 otp_soak(1); 1101 if (data0_masked != buf0_masked) 1102 otp_prog_dw(buf[0], ignore_mask[0], prog_address); 1103 if (data1_masked != buf1_masked) 1104 otp_prog_dw(buf[1], ignore_mask[1], prog_address + 1); 1105 1106 pass = 0; 1107 for (i = 0; i < RETRY; i++) { 1108 if (verify_dw(prog_address, buf, ignore_mask, compare, 2) != 0) { 1109 otp_soak(2); 1110 if (compare[0] != 0) { 1111 otp_prog_dw(compare[0], ignore_mask[0], prog_address); 1112 } 1113 if (compare[1] != ~0) { 1114 otp_prog_dw(compare[1], ignore_mask[0], prog_address + 1); 1115 } 1116 if (verify_dw(prog_address, buf, ignore_mask, compare, 2) != 0) { 1117 otp_soak(1); 1118 } else { 1119 pass = 1; 1120 break; 1121 } 1122 } else { 1123 pass = 1; 1124 break; 1125 } 1126 } 1127 1128 if (!pass) { 1129 otp_soak(0); 1130 return OTP_FAILURE; 1131 } 1132 return OTP_SUCCESS; 1133 } 1134 1135 static void otp_strap_status(struct otpstrap_status *otpstrap) 1136 { 1137 uint32_t OTPSTRAP_RAW[2]; 1138 int strap_end; 1139 int i, j; 1140 1141 if (info_cb.version == OTP_AST2600A0) { 1142 for (j = 0; j < 64; j++) { 1143 otpstrap[j].value = 0; 1144 otpstrap[j].remain_times = 7; 1145 otpstrap[j].writeable_option = -1; 1146 otpstrap[j].protected = 0; 1147 } 1148 strap_end = 30; 1149 } else { 1150 for (j = 0; j < 64; j++) { 1151 otpstrap[j].value = 0; 1152 otpstrap[j].remain_times = 6; 1153 otpstrap[j].writeable_option = -1; 1154 otpstrap[j].reg_protected = 0; 1155 otpstrap[j].protected = 0; 1156 } 1157 strap_end = 28; 1158 } 1159 1160 for (i = 16; i < strap_end; i += 2) { 1161 int option = (i - 16) / 2; 1162 otp_read_config(i, &OTPSTRAP_RAW[0]); 1163 otp_read_config(i + 1, &OTPSTRAP_RAW[1]); 1164 for (j = 0; j < 32; j++) { 1165 char bit_value = ((OTPSTRAP_RAW[0] >> j) & 0x1); 1166 if ((bit_value == 0) && (otpstrap[j].writeable_option == -1)) { 1167 otpstrap[j].writeable_option = option; 1168 } 1169 if (bit_value == 1) 1170 otpstrap[j].remain_times --; 1171 otpstrap[j].value ^= bit_value; 1172 otpstrap[j].option_array[option] = bit_value; 1173 } 1174 for (j = 32; j < 64; j++) { 1175 char bit_value = ((OTPSTRAP_RAW[1] >> (j - 32)) & 0x1); 1176 if ((bit_value == 0) && (otpstrap[j].writeable_option == -1)) { 1177 otpstrap[j].writeable_option = option; 1178 } 1179 if (bit_value == 1) 1180 otpstrap[j].remain_times --; 1181 otpstrap[j].value ^= bit_value; 1182 otpstrap[j].option_array[option] = bit_value; 1183 } 1184 } 1185 1186 if (info_cb.version != OTP_AST2600A0) { 1187 otp_read_config(28, &OTPSTRAP_RAW[0]); 1188 otp_read_config(29, &OTPSTRAP_RAW[1]); 1189 for (j = 0; j < 32; j++) { 1190 if (((OTPSTRAP_RAW[0] >> j) & 0x1) == 1) 1191 otpstrap[j].reg_protected = 1; 1192 } 1193 for (j = 32; j < 64; j++) { 1194 if (((OTPSTRAP_RAW[1] >> (j - 32)) & 0x1) == 1) 1195 otpstrap[j].reg_protected = 1; 1196 } 1197 1198 } 1199 1200 otp_read_config(30, &OTPSTRAP_RAW[0]); 1201 otp_read_config(31, &OTPSTRAP_RAW[1]); 1202 for (j = 0; j < 32; j++) { 1203 if (((OTPSTRAP_RAW[0] >> j) & 0x1) == 1) 1204 otpstrap[j].protected = 1; 1205 } 1206 for (j = 32; j < 64; j++) { 1207 if (((OTPSTRAP_RAW[1] >> (j - 32)) & 0x1) == 1) 1208 otpstrap[j].protected = 1; 1209 } 1210 } 1211 1212 static int otp_print_conf_image(struct otp_image_layout *image_layout) 1213 { 1214 const struct otpconf_info *conf_info = info_cb.conf_info; 1215 uint32_t *OTPCFG = (uint32_t *)image_layout->conf; 1216 uint32_t *OTPCFG_IGNORE = (uint32_t *)image_layout->conf_ignore; 1217 uint32_t mask; 1218 uint32_t dw_offset; 1219 uint32_t bit_offset; 1220 uint32_t otp_value; 1221 uint32_t otp_ignore; 1222 int fail = 0; 1223 char valid_bit[20]; 1224 int i; 1225 int j; 1226 1227 printf("DW BIT Value Description\n"); 1228 printf("__________________________________________________________________________\n"); 1229 for (i = 0; i < info_cb.conf_info_len; i++) { 1230 dw_offset = conf_info[i].dw_offset; 1231 bit_offset = conf_info[i].bit_offset; 1232 mask = BIT(conf_info[i].length) - 1; 1233 otp_value = (OTPCFG[dw_offset] >> bit_offset) & mask; 1234 otp_ignore = (OTPCFG_IGNORE[dw_offset] >> bit_offset) & mask; 1235 1236 if (otp_ignore == mask) { 1237 continue; 1238 } else if (otp_ignore != 0) { 1239 fail = 1; 1240 } 1241 1242 if ((otp_value != conf_info[i].value) && 1243 conf_info[i].value != OTP_REG_RESERVED && 1244 conf_info[i].value != OTP_REG_VALUE && 1245 conf_info[i].value != OTP_REG_VALID_BIT) 1246 continue; 1247 printf("0x%-4X", dw_offset); 1248 1249 if (conf_info[i].length == 1) { 1250 printf("0x%-9X", conf_info[i].bit_offset); 1251 } else { 1252 printf("0x%-2X:0x%-4X", 1253 conf_info[i].bit_offset + conf_info[i].length - 1, 1254 conf_info[i].bit_offset); 1255 } 1256 printf("0x%-10x", otp_value); 1257 1258 if (fail) { 1259 printf("Ignore mask error\n"); 1260 } else { 1261 if (conf_info[i].value == OTP_REG_RESERVED) { 1262 printf("Reserved\n"); 1263 } else if (conf_info[i].value == OTP_REG_VALUE) { 1264 printf(conf_info[i].information, otp_value); 1265 printf("\n"); 1266 } else if (conf_info[i].value == OTP_REG_VALID_BIT) { 1267 if (otp_value != 0) { 1268 for (j = 0; j < 7; j++) { 1269 if (otp_value == (1 << j)) { 1270 valid_bit[j * 2] = '1'; 1271 } else { 1272 valid_bit[j * 2] = '0'; 1273 } 1274 valid_bit[j * 2 + 1] = ' '; 1275 } 1276 valid_bit[15] = 0; 1277 } else { 1278 strcpy(valid_bit, "0 0 0 0 0 0 0 0\0"); 1279 } 1280 printf(conf_info[i].information, valid_bit); 1281 printf("\n"); 1282 } else { 1283 printf("%s\n", conf_info[i].information); 1284 } 1285 } 1286 } 1287 1288 if (fail) 1289 return OTP_FAILURE; 1290 1291 return OTP_SUCCESS; 1292 } 1293 1294 static int otp_print_conf_info(int input_offset) 1295 { 1296 const struct otpconf_info *conf_info = info_cb.conf_info; 1297 uint32_t OTPCFG[16]; 1298 uint32_t mask; 1299 uint32_t dw_offset; 1300 uint32_t bit_offset; 1301 uint32_t otp_value; 1302 char valid_bit[20]; 1303 int i; 1304 int j; 1305 1306 for (i = 0; i < 16; i++) 1307 otp_read_config(i, &OTPCFG[i]); 1308 1309 1310 printf("DW BIT Value Description\n"); 1311 printf("__________________________________________________________________________\n"); 1312 for (i = 0; i < info_cb.conf_info_len; i++) { 1313 if (input_offset != -1 && input_offset != conf_info[i].dw_offset) 1314 continue; 1315 dw_offset = conf_info[i].dw_offset; 1316 bit_offset = conf_info[i].bit_offset; 1317 mask = BIT(conf_info[i].length) - 1; 1318 otp_value = (OTPCFG[dw_offset] >> bit_offset) & mask; 1319 1320 if ((otp_value != conf_info[i].value) && 1321 conf_info[i].value != OTP_REG_RESERVED && 1322 conf_info[i].value != OTP_REG_VALUE && 1323 conf_info[i].value != OTP_REG_VALID_BIT) 1324 continue; 1325 printf("0x%-4X", dw_offset); 1326 1327 if (conf_info[i].length == 1) { 1328 printf("0x%-9X", conf_info[i].bit_offset); 1329 } else { 1330 printf("0x%-2X:0x%-4X", 1331 conf_info[i].bit_offset + conf_info[i].length - 1, 1332 conf_info[i].bit_offset); 1333 } 1334 printf("0x%-10x", otp_value); 1335 1336 if (conf_info[i].value == OTP_REG_RESERVED) { 1337 printf("Reserved\n"); 1338 } else if (conf_info[i].value == OTP_REG_VALUE) { 1339 printf(conf_info[i].information, otp_value); 1340 printf("\n"); 1341 } else if (conf_info[i].value == OTP_REG_VALID_BIT) { 1342 if (otp_value != 0) { 1343 for (j = 0; j < 7; j++) { 1344 if (otp_value == (1 << j)) { 1345 valid_bit[j * 2] = '1'; 1346 } else { 1347 valid_bit[j * 2] = '0'; 1348 } 1349 valid_bit[j * 2 + 1] = ' '; 1350 } 1351 valid_bit[15] = 0; 1352 } else { 1353 strcpy(valid_bit, "0 0 0 0 0 0 0 0\0"); 1354 } 1355 printf(conf_info[i].information, valid_bit); 1356 printf("\n"); 1357 } else { 1358 printf("%s\n", conf_info[i].information); 1359 } 1360 } 1361 return OTP_SUCCESS; 1362 } 1363 1364 static int otp_print_strap_image(struct otp_image_layout *image_layout) 1365 { 1366 const struct otpstrap_info *strap_info = info_cb.strap_info; 1367 uint32_t *OTPSTRAP; 1368 uint32_t *OTPSTRAP_REG_PRO; 1369 uint32_t *OTPSTRAP_PRO; 1370 uint32_t *OTPSTRAP_IGNORE; 1371 int i; 1372 int fail = 0; 1373 uint32_t bit_offset; 1374 uint32_t dw_offset; 1375 uint32_t mask; 1376 uint32_t otp_value; 1377 uint32_t otp_reg_protect; 1378 uint32_t otp_protect; 1379 uint32_t otp_ignore; 1380 1381 OTPSTRAP = (uint32_t *)image_layout->strap; 1382 OTPSTRAP_PRO = (uint32_t *)image_layout->strap_pro; 1383 OTPSTRAP_IGNORE = (uint32_t *)image_layout->strap_ignore; 1384 if (info_cb.version == OTP_AST2600A0) { 1385 OTPSTRAP_REG_PRO = NULL; 1386 printf("BIT(hex) Value Protect Description\n"); 1387 } else { 1388 OTPSTRAP_REG_PRO = (uint32_t *)image_layout->strap_reg_pro; 1389 printf("BIT(hex) Value Reg_Protect Protect Description\n"); 1390 } 1391 printf("__________________________________________________________________________________________\n"); 1392 1393 for (i = 0; i < info_cb.strap_info_len; i++) { 1394 if (strap_info[i].bit_offset > 31) { 1395 dw_offset = 1; 1396 bit_offset = strap_info[i].bit_offset - 32; 1397 } else { 1398 dw_offset = 0; 1399 bit_offset = strap_info[i].bit_offset; 1400 } 1401 1402 mask = BIT(strap_info[i].length) - 1; 1403 otp_value = (OTPSTRAP[dw_offset] >> bit_offset) & mask; 1404 otp_protect = (OTPSTRAP_PRO[dw_offset] >> bit_offset) & mask; 1405 otp_ignore = (OTPSTRAP_IGNORE[dw_offset] >> bit_offset) & mask; 1406 1407 if (info_cb.version != OTP_AST2600A0) 1408 otp_reg_protect = (OTPSTRAP_REG_PRO[dw_offset] >> bit_offset) & mask; 1409 else 1410 otp_reg_protect = 0; 1411 1412 if (otp_ignore == mask) { 1413 continue; 1414 } else if (otp_ignore != 0) { 1415 fail = 1; 1416 } 1417 1418 if ((otp_value != strap_info[i].value) && 1419 strap_info[i].value != OTP_REG_RESERVED) 1420 continue; 1421 1422 if (strap_info[i].length == 1) { 1423 printf("0x%-9X", strap_info[i].bit_offset); 1424 } else { 1425 printf("0x%-2X:0x%-4X", 1426 strap_info[i].bit_offset + strap_info[i].length - 1, 1427 strap_info[i].bit_offset); 1428 } 1429 printf("0x%-10x", otp_value); 1430 if (info_cb.version != OTP_AST2600A0) 1431 printf("0x%-10x", otp_reg_protect); 1432 printf("0x%-10x", otp_protect); 1433 1434 if (fail) { 1435 printf("Ignore mask error\n"); 1436 } else { 1437 if (strap_info[i].value != OTP_REG_RESERVED) 1438 printf("%s\n", strap_info[i].information); 1439 else 1440 printf("Reserved\n"); 1441 } 1442 } 1443 1444 if (fail) 1445 return OTP_FAILURE; 1446 1447 return OTP_SUCCESS; 1448 } 1449 1450 static int otp_print_strap_info(int view) 1451 { 1452 const struct otpstrap_info *strap_info = info_cb.strap_info; 1453 struct otpstrap_status strap_status[64]; 1454 int i, j; 1455 int fail = 0; 1456 uint32_t bit_offset; 1457 uint32_t length; 1458 uint32_t otp_value; 1459 uint32_t otp_protect; 1460 1461 otp_strap_status(strap_status); 1462 1463 if (view) { 1464 if (info_cb.version == OTP_AST2600A0) 1465 printf("BIT(hex) Value Remains Protect Description\n"); 1466 else 1467 printf("BIT(hex) Value Remains Reg_Protect Protect Description\n"); 1468 printf("___________________________________________________________________________________________________\n"); 1469 } else { 1470 printf("BIT(hex) Value Description\n"); 1471 printf("________________________________________________________________________________\n"); 1472 } 1473 for (i = 0; i < info_cb.strap_info_len; i++) { 1474 otp_value = 0; 1475 bit_offset = strap_info[i].bit_offset; 1476 length = strap_info[i].length; 1477 for (j = 0; j < length; j++) { 1478 otp_value |= strap_status[bit_offset + j].value << j; 1479 otp_protect |= strap_status[bit_offset + j].protected << j; 1480 } 1481 if ((otp_value != strap_info[i].value) && 1482 strap_info[i].value != OTP_REG_RESERVED) 1483 continue; 1484 if (view) { 1485 for (j = 0; j < length; j++) { 1486 printf("0x%-7X", strap_info[i].bit_offset + j); 1487 printf("0x%-5X", strap_status[bit_offset + j].value); 1488 printf("%-9d", strap_status[bit_offset + j].remain_times); 1489 if (info_cb.version != OTP_AST2600A0) 1490 printf("0x%-10X", strap_status[bit_offset + j].reg_protected); 1491 printf("0x%-7X", strap_status[bit_offset + j].protected); 1492 if (strap_info[i].value == OTP_REG_RESERVED) { 1493 printf(" Reserved\n"); 1494 continue; 1495 } 1496 if (length == 1) { 1497 printf(" %s\n", strap_info[i].information); 1498 continue; 1499 } 1500 1501 if (j == 0) 1502 printf("/%s\n", strap_info[i].information); 1503 else if (j == length - 1) 1504 printf("\\ \"\n"); 1505 else 1506 printf("| \"\n"); 1507 } 1508 } else { 1509 if (length == 1) { 1510 printf("0x%-9X", strap_info[i].bit_offset); 1511 } else { 1512 printf("0x%-2X:0x%-4X", 1513 bit_offset + length - 1, bit_offset); 1514 } 1515 1516 printf("0x%-10X", otp_value); 1517 1518 if (strap_info[i].value != OTP_REG_RESERVED) 1519 printf("%s\n", strap_info[i].information); 1520 else 1521 printf("Reserved\n"); 1522 } 1523 } 1524 1525 if (fail) 1526 return OTP_FAILURE; 1527 1528 return OTP_SUCCESS; 1529 } 1530 1531 static void buf_print(uint8_t *buf, int len) 1532 { 1533 int i; 1534 printf(" 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F\n"); 1535 for (i = 0; i < len; i++) { 1536 if (i % 16 == 0) { 1537 printf("%04X: ", i); 1538 } 1539 printf("%02X ", buf[i]); 1540 if ((i + 1) % 16 == 0) { 1541 printf("\n"); 1542 } 1543 } 1544 } 1545 1546 static int otp_print_data_info(struct otp_image_layout *image_layout) 1547 { 1548 int key_id, key_offset, last, key_type, key_length, exp_length; 1549 const struct otpkey_type *key_info_array = info_cb.key_info; 1550 struct otpkey_type key_info; 1551 uint32_t *buf; 1552 uint8_t *byte_buf; 1553 char empty = 1; 1554 int i = 0, len = 0; 1555 int j; 1556 1557 byte_buf = image_layout->data; 1558 buf = (uint32_t *)byte_buf; 1559 1560 for (i = 0; i < 16; i++) { 1561 if (buf[i] != 0) { 1562 empty = 0; 1563 } 1564 } 1565 if (empty) 1566 return 0; 1567 1568 i = 0; 1569 while (1) { 1570 key_id = buf[i] & 0x7; 1571 key_offset = buf[i] & 0x1ff8; 1572 last = (buf[i] >> 13) & 1; 1573 key_type = (buf[i] >> 14) & 0xf; 1574 key_length = (buf[i] >> 18) & 0x3; 1575 exp_length = (buf[i] >> 20) & 0xfff; 1576 1577 for (j = 0; j < info_cb.key_info_len; j++) { 1578 if (key_type == key_info_array[j].value) { 1579 key_info = key_info_array[j]; 1580 break; 1581 } 1582 } 1583 1584 printf("\nKey[%d]:\n", i); 1585 printf("Key Type: "); 1586 printf("%s\n", key_info.information); 1587 1588 if (key_info.key_type == OTP_KEY_TYPE_HMAC) { 1589 printf("HMAC SHA Type: "); 1590 switch (key_length) { 1591 case 0: 1592 printf("HMAC(SHA224)\n"); 1593 break; 1594 case 1: 1595 printf("HMAC(SHA256)\n"); 1596 break; 1597 case 2: 1598 printf("HMAC(SHA384)\n"); 1599 break; 1600 case 3: 1601 printf("HMAC(SHA512)\n"); 1602 break; 1603 } 1604 } else if (key_info.key_type == OTP_KEY_TYPE_RSA) { 1605 printf("RSA SHA Type: "); 1606 switch (key_length) { 1607 case 0: 1608 printf("RSA1024\n"); 1609 len = 0x100; 1610 break; 1611 case 1: 1612 printf("RSA2048\n"); 1613 len = 0x200; 1614 break; 1615 case 2: 1616 printf("RSA3072\n"); 1617 len = 0x300; 1618 break; 1619 case 3: 1620 printf("RSA4096\n"); 1621 len = 0x400; 1622 break; 1623 } 1624 printf("RSA exponent bit length: %d\n", exp_length); 1625 } 1626 if (key_info.need_id) 1627 printf("Key Number ID: %d\n", key_id); 1628 printf("Key Value:\n"); 1629 if (key_info.key_type == OTP_KEY_TYPE_HMAC) { 1630 buf_print(&byte_buf[key_offset], 0x40); 1631 } else if (key_info.key_type == OTP_KEY_TYPE_AES) { 1632 printf("AES Key:\n"); 1633 buf_print(&byte_buf[key_offset], 0x20); 1634 if (info_cb.version == OTP_AST2600A0) { 1635 printf("AES IV:\n"); 1636 buf_print(&byte_buf[key_offset + 0x20], 0x10); 1637 } 1638 1639 } else if (key_info.key_type == OTP_KEY_TYPE_VAULT) { 1640 if (info_cb.version == OTP_AST2600A0) { 1641 printf("AES Key:\n"); 1642 buf_print(&byte_buf[key_offset], 0x20); 1643 printf("AES IV:\n"); 1644 buf_print(&byte_buf[key_offset + 0x20], 0x10); 1645 } else { 1646 printf("AES Key 1:\n"); 1647 buf_print(&byte_buf[key_offset], 0x20); 1648 printf("AES Key 2:\n"); 1649 buf_print(&byte_buf[key_offset + 0x20], 0x20); 1650 } 1651 1652 } else if (key_info.key_type == OTP_KEY_TYPE_RSA) { 1653 printf("RSA mod:\n"); 1654 buf_print(&byte_buf[key_offset], len / 2); 1655 printf("RSA exp:\n"); 1656 buf_print(&byte_buf[key_offset + (len / 2)], len / 2); 1657 } 1658 if (last) 1659 break; 1660 i++; 1661 } 1662 return 0; 1663 } 1664 1665 static int otp_prog_conf(struct otp_image_layout *image_layout) 1666 { 1667 int i, k; 1668 int pass = 0; 1669 uint32_t prog_address; 1670 uint32_t data[16]; 1671 uint32_t compare[2]; 1672 uint32_t *conf = (uint32_t *)image_layout->conf; 1673 uint32_t *conf_ignore = (uint32_t *)image_layout->conf_ignore; 1674 uint32_t data_masked; 1675 uint32_t buf_masked; 1676 1677 printf("Read OTP Config Region:\n"); 1678 1679 for (i = 0; i < 16 ; i ++) { 1680 prog_address = 0x800; 1681 prog_address |= (i / 8) * 0x200; 1682 prog_address |= (i % 8) * 0x2; 1683 otp_read_data(prog_address, &data[i]); 1684 } 1685 1686 printf("Check writable...\n"); 1687 for (i = 0; i < 16; i++) { 1688 data_masked = data[i] & ~conf_ignore[i]; 1689 buf_masked = conf[i] & ~conf_ignore[i]; 1690 if (data_masked == buf_masked) 1691 continue; 1692 if ((data_masked | buf_masked) == buf_masked) { 1693 continue; 1694 } else { 1695 printf("Input image can't program into OTP, please check.\n"); 1696 printf("OTPCFG[%X] = %x\n", i, data[i]); 1697 printf("Input [%X] = %x\n", i, conf[i]); 1698 printf("Mask [%X] = %x\n", i, ~conf_ignore[i]); 1699 return OTP_FAILURE; 1700 } 1701 } 1702 1703 printf("Start Programing...\n"); 1704 otp_soak(0); 1705 for (i = 0; i < 16; i++) { 1706 data_masked = data[i] & ~conf_ignore[i]; 1707 buf_masked = conf[i] & ~conf_ignore[i]; 1708 prog_address = 0x800; 1709 prog_address |= (i / 8) * 0x200; 1710 prog_address |= (i % 8) * 0x2; 1711 if (data_masked == buf_masked) { 1712 pass = 1; 1713 continue; 1714 } 1715 1716 1717 otp_soak(1); 1718 otp_prog_dw(conf[i], conf_ignore[i], prog_address); 1719 1720 pass = 0; 1721 for (k = 0; k < RETRY; k++) { 1722 if (verify_dw(prog_address, &conf[i], &conf_ignore[i], compare, 1) != 0) { 1723 otp_soak(2); 1724 otp_prog_dw(compare[0], prog_address, 1); 1725 if (verify_dw(prog_address, &conf[i], &conf_ignore[i], compare, 1) != 0) { 1726 otp_soak(1); 1727 } else { 1728 pass = 1; 1729 break; 1730 } 1731 } else { 1732 pass = 1; 1733 break; 1734 } 1735 } 1736 if (pass == 0) { 1737 printf("address: %08x, data: %08x, buffer: %08x, mask: %08x\n", 1738 i, data[i], conf[i], conf_ignore[i]); 1739 break; 1740 } 1741 } 1742 1743 otp_soak(0); 1744 if (!pass) 1745 return OTP_FAILURE; 1746 1747 return OTP_SUCCESS; 1748 1749 } 1750 1751 static int otp_strap_bit_confirm(struct otpstrap_status *otpstrap, int offset, int ibit, int bit, int pbit, int rpbit) 1752 { 1753 if (ibit == 1) { 1754 return OTP_SUCCESS; 1755 } else { 1756 printf("OTPSTRAP[%X]:\n", offset); 1757 } 1758 if (bit == otpstrap->value) { 1759 printf(" The value is same as before, skip it.\n"); 1760 return OTP_PROG_SKIP; 1761 } 1762 if (otpstrap->protected == 1) { 1763 printf(" This bit is protected and is not writable\n"); 1764 return OTP_FAILURE; 1765 } 1766 if (otpstrap->remain_times == 0) { 1767 printf(" This bit is no remaining times to write.\n"); 1768 return OTP_FAILURE; 1769 } 1770 if (pbit == 1) { 1771 printf(" This bit will be protected and become non-writable.\n"); 1772 } 1773 if (rpbit == 1 && info_cb.version != OTP_AST2600A0) { 1774 printf(" The relative register will be protected.\n"); 1775 } 1776 printf(" Write 1 to OTPSTRAP[%X] OPTION[%X], that value becomes from %d to %d.\n", offset, otpstrap->writeable_option + 1, otpstrap->value, otpstrap->value ^ 1); 1777 return OTP_SUCCESS; 1778 } 1779 1780 static int otp_strap_image_confirm(struct otp_image_layout *image_layout) 1781 { 1782 int i; 1783 uint32_t *strap; 1784 uint32_t *strap_ignore; 1785 uint32_t *strap_reg_protect; 1786 uint32_t *strap_pro; 1787 int bit, pbit, ibit, rpbit; 1788 int fail = 0; 1789 int skip = -1; 1790 int ret; 1791 struct otpstrap_status otpstrap[64]; 1792 1793 strap = (uint32_t *)image_layout->strap; 1794 strap_pro = (uint32_t *)image_layout->strap_pro; 1795 strap_ignore = (uint32_t *)image_layout->strap_ignore; 1796 strap_reg_protect = (uint32_t *)image_layout->strap_reg_pro; 1797 1798 otp_strap_status(otpstrap); 1799 for (i = 0; i < 64; i++) { 1800 if (i < 32) { 1801 bit = (strap[0] >> i) & 0x1; 1802 ibit = (strap_ignore[0] >> i) & 0x1; 1803 pbit = (strap_pro[0] >> i) & 0x1; 1804 } else { 1805 bit = (strap[1] >> (i - 32)) & 0x1; 1806 ibit = (strap_ignore[1] >> (i - 32)) & 0x1; 1807 pbit = (strap_pro[1] >> (i - 32)) & 0x1; 1808 } 1809 1810 if (info_cb.version != OTP_AST2600A0) { 1811 if (i < 32) { 1812 rpbit = (strap_reg_protect[0] >> i) & 0x1; 1813 } else { 1814 rpbit = (strap_reg_protect[1] >> (i - 32)) & 0x1; 1815 } 1816 } else { 1817 rpbit = 0; 1818 } 1819 ret = otp_strap_bit_confirm(&otpstrap[i], i, ibit, bit, pbit, rpbit); 1820 if (ret == OTP_PROG_SKIP) { 1821 if (skip == -1) 1822 skip = 1; 1823 continue; 1824 } else { 1825 skip = 1; 1826 } 1827 1828 if (ret == OTP_FAILURE) 1829 fail = 1; 1830 } 1831 if (fail == 1) 1832 return OTP_FAILURE; 1833 else if (skip == 1) 1834 return OTP_PROG_SKIP; 1835 1836 return OTP_SUCCESS; 1837 } 1838 1839 static int otp_print_strap(int start, int count) 1840 { 1841 int i, j; 1842 int remains; 1843 struct otpstrap_status otpstrap[64]; 1844 1845 if (start < 0 || start > 64) 1846 return OTP_USAGE; 1847 1848 if ((start + count) < 0 || (start + count) > 64) 1849 return OTP_USAGE; 1850 1851 otp_strap_status(otpstrap); 1852 1853 if (info_cb.version == OTP_AST2600A0) { 1854 remains = 7; 1855 printf("BIT(hex) Value Option Status\n"); 1856 } else { 1857 remains = 6; 1858 printf("BIT(hex) Value Option Reg_Protect Status\n"); 1859 } 1860 printf("______________________________________________________________________________\n"); 1861 1862 for (i = start; i < start + count; i++) { 1863 printf("0x%-8X", i); 1864 printf("%-7d", otpstrap[i].value); 1865 for (j = 0; j < remains; j++) 1866 printf("%d ", otpstrap[i].option_array[j]); 1867 printf(" "); 1868 if (info_cb.version != OTP_AST2600A0) { 1869 printf("%d ", otpstrap[i].reg_protected); 1870 } 1871 if (otpstrap[i].protected == 1) { 1872 printf("protected and not writable"); 1873 } else { 1874 printf("not protected "); 1875 if (otpstrap[i].remain_times == 0) { 1876 printf("and no remaining times to write."); 1877 } else { 1878 printf("and still can write %d times", otpstrap[i].remain_times); 1879 } 1880 } 1881 printf("\n"); 1882 } 1883 1884 return OTP_SUCCESS; 1885 } 1886 1887 static int otp_prog_strap_bit(int bit_offset, int value) 1888 { 1889 struct otpstrap_status otpstrap[64]; 1890 uint32_t prog_address; 1891 int offset; 1892 int ret; 1893 1894 1895 otp_strap_status(otpstrap); 1896 1897 ret = otp_strap_bit_confirm(&otpstrap[bit_offset], bit_offset, 0, value, 0, 0); 1898 1899 if (ret != OTP_SUCCESS) { 1900 return ret; 1901 } 1902 1903 prog_address = 0x800; 1904 if (bit_offset < 32) { 1905 offset = bit_offset; 1906 prog_address |= ((otpstrap[bit_offset].writeable_option * 2 + 16) / 8) * 0x200; 1907 prog_address |= ((otpstrap[bit_offset].writeable_option * 2 + 16) % 8) * 0x2; 1908 1909 } else { 1910 offset = (bit_offset - 32); 1911 prog_address |= ((otpstrap[bit_offset].writeable_option * 2 + 17) / 8) * 0x200; 1912 prog_address |= ((otpstrap[bit_offset].writeable_option * 2 + 17) % 8) * 0x2; 1913 } 1914 1915 1916 return otp_prog_bit(1, prog_address, offset); 1917 } 1918 1919 static int otp_prog_strap(struct otp_image_layout *image_layout) 1920 { 1921 uint32_t *strap; 1922 uint32_t *strap_ignore; 1923 uint32_t *strap_pro; 1924 uint32_t *strap_reg_protect; 1925 uint32_t prog_address; 1926 int i; 1927 int bit, pbit, ibit, offset, rpbit; 1928 int fail = 0; 1929 int ret; 1930 struct otpstrap_status otpstrap[64]; 1931 1932 strap = (uint32_t *)image_layout->strap; 1933 strap_pro = (uint32_t *)image_layout->strap_pro; 1934 strap_ignore = (uint32_t *)image_layout->strap_ignore; 1935 strap_reg_protect = (uint32_t *)image_layout->strap_reg_pro; 1936 1937 printf("Read OTP Strap Region:\n"); 1938 otp_strap_status(otpstrap); 1939 1940 printf("Check writable...\n"); 1941 if (otp_strap_image_confirm(image_layout) == OTP_FAILURE) { 1942 printf("Input image can't program into OTP, please check.\n"); 1943 return OTP_FAILURE; 1944 } 1945 1946 for (i = 0; i < 64; i++) { 1947 prog_address = 0x800; 1948 if (i < 32) { 1949 offset = i; 1950 bit = (strap[0] >> offset) & 0x1; 1951 ibit = (strap_ignore[0] >> offset) & 0x1; 1952 pbit = (strap_pro[0] >> offset) & 0x1; 1953 prog_address |= ((otpstrap[i].writeable_option * 2 + 16) / 8) * 0x200; 1954 prog_address |= ((otpstrap[i].writeable_option * 2 + 16) % 8) * 0x2; 1955 1956 } else { 1957 offset = (i - 32); 1958 bit = (strap[1] >> offset) & 0x1; 1959 ibit = (strap_ignore[1] >> offset) & 0x1; 1960 pbit = (strap_pro[1] >> offset) & 0x1; 1961 prog_address |= ((otpstrap[i].writeable_option * 2 + 17) / 8) * 0x200; 1962 prog_address |= ((otpstrap[i].writeable_option * 2 + 17) % 8) * 0x2; 1963 } 1964 if (info_cb.version != OTP_AST2600A0) { 1965 if (i < 32) { 1966 rpbit = (strap_reg_protect[0] >> i) & 0x1; 1967 } else { 1968 rpbit = (strap_reg_protect[1] >> (i - 32)) & 0x1; 1969 } 1970 } else { 1971 rpbit = 0; 1972 } 1973 1974 if (ibit == 1) { 1975 continue; 1976 } 1977 if (bit == otpstrap[i].value) { 1978 continue; 1979 } 1980 if (otpstrap[i].protected == 1) { 1981 fail = 1; 1982 continue; 1983 } 1984 if (otpstrap[i].remain_times == 0) { 1985 fail = 1; 1986 continue; 1987 } 1988 1989 ret = otp_prog_bit(1, prog_address, offset); 1990 if (!ret) 1991 return OTP_FAILURE; 1992 1993 if (rpbit == 1 && info_cb.version != OTP_AST2600A0) { 1994 prog_address = 0x800; 1995 if (i < 32) 1996 prog_address |= 0x608; 1997 else 1998 prog_address |= 0x60a; 1999 2000 ret = otp_prog_bit(1, prog_address, offset); 2001 if (!ret) 2002 return OTP_FAILURE; 2003 } 2004 2005 if (pbit != 0) { 2006 prog_address = 0x800; 2007 if (i < 32) 2008 prog_address |= 0x60c; 2009 else 2010 prog_address |= 0x60e; 2011 2012 ret = otp_prog_bit(1, prog_address, offset); 2013 if (!ret) 2014 return OTP_FAILURE; 2015 } 2016 2017 } 2018 otp_soak(0); 2019 if (fail == 1) 2020 return OTP_FAILURE; 2021 else 2022 return OTP_SUCCESS; 2023 2024 } 2025 2026 static int otp_prog_data(struct otp_image_layout *image_layout) 2027 { 2028 int i; 2029 int ret; 2030 int data_dw; 2031 uint32_t data[2048]; 2032 uint32_t *buf; 2033 uint32_t *buf_ignore; 2034 2035 uint32_t data_masked; 2036 uint32_t buf_masked; 2037 2038 buf = (uint32_t *)image_layout->data; 2039 buf_ignore = (uint32_t *)image_layout->data_ignore; 2040 2041 data_dw = image_layout->data_length / 4; 2042 2043 printf("Read OTP Data:\n"); 2044 2045 for (i = 0; i < data_dw - 2 ; i += 2) { 2046 otp_read_data(i, &data[i]); 2047 } 2048 2049 printf("Check writable...\n"); 2050 // ignore last two dw, the last two dw is used for slt otp write check. 2051 for (i = 0; i < data_dw - 2; i++) { 2052 data_masked = data[i] & ~buf_ignore[i]; 2053 buf_masked = buf[i] & ~buf_ignore[i]; 2054 if (data_masked == buf_masked) 2055 continue; 2056 if (i % 2 == 0) { 2057 if ((data_masked | buf_masked) == buf_masked) { 2058 continue; 2059 } else { 2060 printf("Input image can't program into OTP, please check.\n"); 2061 printf("OTP_ADDR[%x] = %x\n", i, data[i]); 2062 printf("Input [%x] = %x\n", i, buf[i]); 2063 printf("Mask [%x] = %x\n", i, ~buf_ignore[i]); 2064 return OTP_FAILURE; 2065 } 2066 } else { 2067 if ((data_masked & buf_masked) == buf_masked) { 2068 continue; 2069 } else { 2070 printf("Input image can't program into OTP, please check.\n"); 2071 printf("OTP_ADDR[%x] = %x\n", i, data[i]); 2072 printf("Input [%x] = %x\n", i, buf[i]); 2073 printf("Mask [%x] = %x\n", i, ~buf_ignore[i]); 2074 return OTP_FAILURE; 2075 } 2076 } 2077 } 2078 2079 printf("Start Programing...\n"); 2080 2081 // programing ecc region first 2082 for (i = 1792; i < 2046; i += 2) { 2083 ret = otp_prog_verify_2dw(&data[i], &buf[i], &buf_ignore[i], i); 2084 if (ret != OTP_SUCCESS) { 2085 printf("address: %08x, data: %08x %08x, buffer: %08x %08x, mask: %08x %08x\n", 2086 i, data[i], data[i + 1], buf[i], buf[i + 1], buf_ignore[i], buf_ignore[i + 1]); 2087 return ret; 2088 } 2089 } 2090 2091 for (i = 0; i < 1792; i += 2) { 2092 ret = otp_prog_verify_2dw(&data[i], &buf[i], &buf_ignore[i], i); 2093 if (ret != OTP_SUCCESS) { 2094 printf("address: %08x, data: %08x %08x, buffer: %08x %08x, mask: %08x %08x\n", 2095 i, data[i], data[i + 1], buf[i], buf[i + 1], buf_ignore[i], buf_ignore[i + 1]); 2096 return ret; 2097 } 2098 } 2099 otp_soak(0); 2100 return OTP_SUCCESS; 2101 2102 } 2103 2104 static int otp_image_verify(uint8_t *src_buf, uint32_t length, uint8_t *digest_buf) 2105 { 2106 sha256_context ctx; 2107 u8 digest_ret[CHECKSUM_LEN]; 2108 2109 sha256_starts(&ctx); 2110 sha256_update(&ctx, src_buf, length); 2111 sha256_finish(&ctx, digest_ret); 2112 2113 if (!memcmp(digest_buf, digest_ret, CHECKSUM_LEN)) 2114 return 0; 2115 else 2116 return -1; 2117 2118 } 2119 2120 static int do_otp_prog(int addr, int nconfirm) 2121 { 2122 int ret; 2123 int image_version = 0; 2124 struct otp_header *otp_header; 2125 struct otp_image_layout image_layout; 2126 int image_size; 2127 uint8_t *buf; 2128 uint8_t *checksum; 2129 2130 otp_header = map_physmem(addr, sizeof(struct otp_header), MAP_WRBACK); 2131 if (!otp_header) { 2132 puts("Failed to map physical memory\n"); 2133 return OTP_FAILURE; 2134 } 2135 2136 image_size = OTP_IMAGE_SIZE(otp_header->image_info); 2137 unmap_physmem(otp_header, MAP_WRBACK); 2138 2139 buf = map_physmem(addr, image_size + CHECKSUM_LEN, MAP_WRBACK); 2140 2141 if (!buf) { 2142 puts("Failed to map physical memory\n"); 2143 return OTP_FAILURE; 2144 } 2145 otp_header = (struct otp_header *) buf; 2146 checksum = buf + otp_header->checksum_offset; 2147 2148 if (strcmp(OTP_MAGIC, (char *)otp_header->otp_magic) != 0) { 2149 puts("Image is invalid\n"); 2150 return OTP_FAILURE; 2151 } 2152 2153 2154 image_layout.data_length = (int)(OTP_REGION_SIZE(otp_header->data_info) / 2); 2155 image_layout.data = buf + OTP_REGION_OFFSET(otp_header->data_info); 2156 image_layout.data_ignore = image_layout.data + image_layout.data_length; 2157 2158 image_layout.conf_length = (int)(OTP_REGION_SIZE(otp_header->config_info) / 2); 2159 image_layout.conf = buf + OTP_REGION_OFFSET(otp_header->config_info); 2160 image_layout.conf_ignore = image_layout.conf + image_layout.conf_length; 2161 2162 image_layout.strap = buf + OTP_REGION_OFFSET(otp_header->strap_info); 2163 2164 if (!strcmp("A0", (char *)otp_header->otp_version)) { 2165 image_version = OTP_AST2600A0; 2166 image_layout.strap_length = (int)(OTP_REGION_SIZE(otp_header->strap_info) / 3); 2167 image_layout.strap_pro = image_layout.strap + image_layout.strap_length; 2168 image_layout.strap_ignore = image_layout.strap + 2 * image_layout.strap_length; 2169 } else if (!strcmp("A1", (char *)otp_header->otp_version)) { 2170 image_version = OTP_AST2600A1; 2171 image_layout.strap_length = (int)(OTP_REGION_SIZE(otp_header->strap_info) / 4); 2172 image_layout.strap_reg_pro = image_layout.strap + image_layout.strap_length; 2173 image_layout.strap_pro = image_layout.strap + 2 * image_layout.strap_length; 2174 image_layout.strap_ignore = image_layout.strap + 3 * image_layout.strap_length; 2175 } else if (!strcmp("A2", (char *)otp_header->otp_version)) { 2176 image_version = OTP_AST2600A2; 2177 image_layout.strap_length = (int)(OTP_REGION_SIZE(otp_header->strap_info) / 4); 2178 image_layout.strap_reg_pro = image_layout.strap + image_layout.strap_length; 2179 image_layout.strap_pro = image_layout.strap + 2 * image_layout.strap_length; 2180 image_layout.strap_ignore = image_layout.strap + 3 * image_layout.strap_length; 2181 } else { 2182 puts("Version is not supported\n"); 2183 return OTP_FAILURE; 2184 } 2185 2186 if (image_version != info_cb.version) { 2187 puts("Version is not match\n"); 2188 return OTP_FAILURE; 2189 } 2190 2191 if (otp_image_verify(buf, image_size, checksum)) { 2192 puts("checksum is invalid\n"); 2193 return OTP_FAILURE; 2194 } 2195 2196 if (!nconfirm) { 2197 if (otp_header->image_info & OTP_INC_DATA) { 2198 printf("\nOTP data region :\n"); 2199 if (otp_print_data_info(&image_layout) < 0) { 2200 printf("OTP data error, please check.\n"); 2201 return OTP_FAILURE; 2202 } 2203 } 2204 if (otp_header->image_info & OTP_INC_STRAP) { 2205 printf("\nOTP strap region :\n"); 2206 if (otp_print_strap_image(&image_layout) < 0) { 2207 printf("OTP strap error, please check.\n"); 2208 return OTP_FAILURE; 2209 } 2210 } 2211 if (otp_header->image_info & OTP_INC_CONFIG) { 2212 printf("\nOTP configuration region :\n"); 2213 if (otp_print_conf_image(&image_layout) < 0) { 2214 printf("OTP config error, please check.\n"); 2215 return OTP_FAILURE; 2216 } 2217 } 2218 2219 printf("type \"YES\" (no quotes) to continue:\n"); 2220 if (!confirm_yesno()) { 2221 printf(" Aborting\n"); 2222 return OTP_FAILURE; 2223 } 2224 } 2225 2226 if (otp_header->image_info & OTP_INC_DATA) { 2227 printf("programing data region ...\n"); 2228 ret = otp_prog_data(&image_layout); 2229 if (ret != 0) { 2230 printf("Error\n"); 2231 return ret; 2232 } else { 2233 printf("Done\n"); 2234 } 2235 } 2236 if (otp_header->image_info & OTP_INC_STRAP) { 2237 printf("programing strap region ...\n"); 2238 ret = otp_prog_strap(&image_layout); 2239 if (ret != 0) { 2240 printf("Error\n"); 2241 return ret; 2242 } else { 2243 printf("Done\n"); 2244 } 2245 } 2246 if (otp_header->image_info & OTP_INC_CONFIG) { 2247 printf("programing configuration region ...\n"); 2248 ret = otp_prog_conf(&image_layout); 2249 if (ret != 0) { 2250 printf("Error\n"); 2251 return ret; 2252 } 2253 printf("Done\n"); 2254 } 2255 2256 return OTP_SUCCESS; 2257 } 2258 2259 static int do_otp_prog_bit(int mode, int otp_dw_offset, int bit_offset, int value, int nconfirm) 2260 { 2261 uint32_t read[2]; 2262 uint32_t prog_address = 0; 2263 struct otpstrap_status otpstrap[64]; 2264 int otp_bit; 2265 int ret = 0; 2266 2267 switch (mode) { 2268 case OTP_REGION_CONF: 2269 otp_read_config(otp_dw_offset, read); 2270 prog_address = 0x800; 2271 prog_address |= (otp_dw_offset / 8) * 0x200; 2272 prog_address |= (otp_dw_offset % 8) * 0x2; 2273 otp_bit = (read[0] >> bit_offset) & 0x1; 2274 if (otp_bit == value) { 2275 printf("OTPCFG%X[%X] = %d\n", otp_dw_offset, bit_offset, value); 2276 printf("No need to program\n"); 2277 return OTP_SUCCESS; 2278 } 2279 if (otp_bit == 1 && value == 0) { 2280 printf("OTPCFG%X[%X] = 1\n", otp_dw_offset, bit_offset); 2281 printf("OTP is programed, which can't be clean\n"); 2282 return OTP_FAILURE; 2283 } 2284 printf("Program OTPCFG%X[%X] to 1\n", otp_dw_offset, bit_offset); 2285 break; 2286 case OTP_REGION_DATA: 2287 prog_address = otp_dw_offset; 2288 2289 if (otp_dw_offset % 2 == 0) { 2290 otp_read_data(otp_dw_offset, read); 2291 otp_bit = (read[0] >> bit_offset) & 0x1; 2292 2293 if (otp_bit == 1 && value == 0) { 2294 printf("OTPDATA%X[%X] = 1\n", otp_dw_offset, bit_offset); 2295 printf("OTP is programed, which can't be cleaned\n"); 2296 return OTP_FAILURE; 2297 } 2298 } else { 2299 otp_read_data(otp_dw_offset - 1, read); 2300 otp_bit = (read[1] >> bit_offset) & 0x1; 2301 2302 if (otp_bit == 0 && value == 1) { 2303 printf("OTPDATA%X[%X] = 1\n", otp_dw_offset, bit_offset); 2304 printf("OTP is programed, which can't be writen\n"); 2305 return OTP_FAILURE; 2306 } 2307 } 2308 if (otp_bit == value) { 2309 printf("OTPDATA%X[%X] = %d\n", otp_dw_offset, bit_offset, value); 2310 printf("No need to program\n"); 2311 return OTP_SUCCESS; 2312 } 2313 2314 printf("Program OTPDATA%X[%X] to 1\n", otp_dw_offset, bit_offset); 2315 break; 2316 case OTP_REGION_STRAP: 2317 otp_strap_status(otpstrap); 2318 otp_print_strap(bit_offset, 1); 2319 ret = otp_strap_bit_confirm(&otpstrap[bit_offset], bit_offset, 0, value, 0, 0); 2320 if (ret == OTP_FAILURE) 2321 return OTP_FAILURE; 2322 else if (ret == OTP_PROG_SKIP) 2323 return OTP_SUCCESS; 2324 2325 break; 2326 } 2327 2328 if (!nconfirm) { 2329 printf("type \"YES\" (no quotes) to continue:\n"); 2330 if (!confirm_yesno()) { 2331 printf(" Aborting\n"); 2332 return OTP_FAILURE; 2333 } 2334 } 2335 2336 switch (mode) { 2337 case OTP_REGION_STRAP: 2338 ret = otp_prog_strap_bit(bit_offset, value); 2339 break; 2340 case OTP_REGION_CONF: 2341 case OTP_REGION_DATA: 2342 ret = otp_prog_bit(value, prog_address, bit_offset); 2343 break; 2344 } 2345 otp_soak(0); 2346 if (ret) { 2347 printf("SUCCESS\n"); 2348 return OTP_SUCCESS; 2349 } else { 2350 printf("OTP cannot be programed\n"); 2351 printf("FAILED\n"); 2352 return OTP_FAILURE; 2353 } 2354 2355 return OTP_USAGE; 2356 } 2357 2358 static int do_otpread(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) 2359 { 2360 uint32_t offset, count; 2361 int ret; 2362 2363 if (argc == 4) { 2364 offset = simple_strtoul(argv[2], NULL, 16); 2365 count = simple_strtoul(argv[3], NULL, 16); 2366 } else if (argc == 3) { 2367 offset = simple_strtoul(argv[2], NULL, 16); 2368 count = 1; 2369 } else { 2370 return CMD_RET_USAGE; 2371 } 2372 2373 2374 if (!strcmp(argv[1], "conf")) { 2375 writel(OTP_PASSWD, OTP_PROTECT_KEY); //password 2376 ret = otp_print_config(offset, count); 2377 } else if (!strcmp(argv[1], "data")) { 2378 writel(OTP_PASSWD, OTP_PROTECT_KEY); //password 2379 ret = otp_print_data(offset, count); 2380 } else if (!strcmp(argv[1], "strap")) { 2381 writel(OTP_PASSWD, OTP_PROTECT_KEY); //password 2382 ret = otp_print_strap(offset, count); 2383 } else { 2384 return CMD_RET_USAGE; 2385 } 2386 2387 if (ret == OTP_SUCCESS) 2388 return CMD_RET_SUCCESS; 2389 else 2390 return CMD_RET_USAGE; 2391 2392 } 2393 2394 static int do_otpprog(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) 2395 { 2396 phys_addr_t addr; 2397 int ret; 2398 2399 if (argc == 3) { 2400 if (strcmp(argv[1], "o")) 2401 return CMD_RET_USAGE; 2402 addr = simple_strtoul(argv[2], NULL, 16); 2403 writel(OTP_PASSWD, OTP_PROTECT_KEY); //password 2404 ret = do_otp_prog(addr, 1); 2405 } else if (argc == 2) { 2406 addr = simple_strtoul(argv[1], NULL, 16); 2407 writel(OTP_PASSWD, OTP_PROTECT_KEY); //password 2408 ret = do_otp_prog(addr, 0); 2409 } else { 2410 return CMD_RET_USAGE; 2411 } 2412 2413 if (ret == OTP_SUCCESS) 2414 return CMD_RET_SUCCESS; 2415 else if (ret == OTP_FAILURE) 2416 return CMD_RET_FAILURE; 2417 else 2418 return CMD_RET_USAGE; 2419 } 2420 2421 static int do_otppb(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) 2422 { 2423 int mode = 0; 2424 int nconfirm = 0; 2425 int otp_addr = 0; 2426 int bit_offset; 2427 int value; 2428 int ret; 2429 2430 if (argc != 4 && argc != 5 && argc != 6) 2431 return CMD_RET_USAGE; 2432 2433 /* Drop the pb cmd */ 2434 argc--; 2435 argv++; 2436 2437 if (!strcmp(argv[0], "conf")) 2438 mode = OTP_REGION_CONF; 2439 else if (!strcmp(argv[0], "strap")) 2440 mode = OTP_REGION_STRAP; 2441 else if (!strcmp(argv[0], "data")) 2442 mode = OTP_REGION_DATA; 2443 else 2444 return CMD_RET_USAGE; 2445 2446 /* Drop the region cmd */ 2447 argc--; 2448 argv++; 2449 2450 if (!strcmp(argv[0], "o")) { 2451 nconfirm = 1; 2452 /* Drop the force option */ 2453 argc--; 2454 argv++; 2455 } 2456 2457 if (mode == OTP_REGION_STRAP) { 2458 bit_offset = simple_strtoul(argv[0], NULL, 16); 2459 value = simple_strtoul(argv[1], NULL, 16); 2460 if (bit_offset >= 64 || (value != 0 && value != 1)) 2461 return CMD_RET_USAGE; 2462 } else { 2463 otp_addr = simple_strtoul(argv[0], NULL, 16); 2464 bit_offset = simple_strtoul(argv[1], NULL, 16); 2465 value = simple_strtoul(argv[2], NULL, 16); 2466 if (bit_offset >= 32 || (value != 0 && value != 1)) 2467 return CMD_RET_USAGE; 2468 if (mode == OTP_REGION_DATA) { 2469 if (otp_addr >= 0x800) 2470 return CMD_RET_USAGE; 2471 } else { 2472 if (otp_addr >= 0x20) 2473 return CMD_RET_USAGE; 2474 } 2475 } 2476 if (value != 0 && value != 1) 2477 return CMD_RET_USAGE; 2478 2479 writel(OTP_PASSWD, OTP_PROTECT_KEY); //password 2480 ret = do_otp_prog_bit(mode, otp_addr, bit_offset, value, nconfirm); 2481 2482 if (ret == OTP_SUCCESS) 2483 return CMD_RET_SUCCESS; 2484 else if (ret == OTP_FAILURE) 2485 return CMD_RET_FAILURE; 2486 else 2487 return CMD_RET_USAGE; 2488 } 2489 2490 static int do_otpcmp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) 2491 { 2492 phys_addr_t addr; 2493 int otp_addr = 0; 2494 2495 if (argc != 3) 2496 return CMD_RET_USAGE; 2497 2498 writel(OTP_PASSWD, OTP_PROTECT_KEY); //password 2499 addr = simple_strtoul(argv[1], NULL, 16); 2500 otp_addr = simple_strtoul(argv[2], NULL, 16); 2501 if (otp_compare(otp_addr, addr) == 0) { 2502 printf("Compare pass\n"); 2503 return CMD_RET_SUCCESS; 2504 } else { 2505 printf("Compare fail\n"); 2506 return CMD_RET_FAILURE; 2507 } 2508 } 2509 2510 static int do_otpinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) 2511 { 2512 int view = 0; 2513 int input; 2514 2515 if (argc != 2 && argc != 3) 2516 return CMD_RET_USAGE; 2517 2518 if (!strcmp(argv[1], "conf")) { 2519 2520 writel(OTP_PASSWD, OTP_PROTECT_KEY); //password 2521 if (argc == 3) { 2522 input = simple_strtoul(argv[2], NULL, 16); 2523 otp_print_conf_info(input); 2524 } else { 2525 otp_print_conf_info(-1); 2526 } 2527 } else if (!strcmp(argv[1], "strap")) { 2528 if (!strcmp(argv[2], "v")) { 2529 view = 1; 2530 /* Drop the view option */ 2531 argc--; 2532 argv++; 2533 } 2534 writel(OTP_PASSWD, OTP_PROTECT_KEY); //password 2535 otp_print_strap_info(view); 2536 } else { 2537 return CMD_RET_USAGE; 2538 } 2539 2540 return CMD_RET_SUCCESS; 2541 } 2542 2543 static int do_otpprotect(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) 2544 { 2545 int input; 2546 int bit_offset; 2547 int prog_address; 2548 int ret; 2549 if (argc != 3 && argc != 2) 2550 return CMD_RET_USAGE; 2551 2552 if (!strcmp(argv[0], "o")) { 2553 input = simple_strtoul(argv[2], NULL, 16); 2554 } else { 2555 input = simple_strtoul(argv[1], NULL, 16); 2556 printf("OTPSTRAP[%d] will be protected\n", input); 2557 printf("type \"YES\" (no quotes) to continue:\n"); 2558 if (!confirm_yesno()) { 2559 printf(" Aborting\n"); 2560 return CMD_RET_FAILURE; 2561 } 2562 } 2563 2564 prog_address = 0x800; 2565 if (input < 32) { 2566 bit_offset = input; 2567 prog_address |= 0x60c; 2568 } else if (input < 64) { 2569 bit_offset = input - 32; 2570 prog_address |= 0x60e; 2571 } else { 2572 return CMD_RET_USAGE; 2573 } 2574 2575 if (verify_bit(prog_address, bit_offset, 1) == 0) { 2576 printf("OTPSTRAP[%d] already protected\n", input); 2577 } 2578 2579 ret = otp_prog_bit(1, prog_address, bit_offset); 2580 otp_soak(0); 2581 2582 if (ret) { 2583 printf("OTPSTRAP[%d] is protected\n", input); 2584 return CMD_RET_SUCCESS; 2585 } 2586 2587 printf("Protect OTPSTRAP[%d] fail\n", input); 2588 return CMD_RET_FAILURE; 2589 2590 } 2591 2592 static cmd_tbl_t cmd_otp[] = { 2593 U_BOOT_CMD_MKENT(read, 4, 0, do_otpread, "", ""), 2594 U_BOOT_CMD_MKENT(info, 3, 0, do_otpinfo, "", ""), 2595 U_BOOT_CMD_MKENT(prog, 3, 0, do_otpprog, "", ""), 2596 U_BOOT_CMD_MKENT(pb, 6, 0, do_otppb, "", ""), 2597 U_BOOT_CMD_MKENT(protect, 3, 0, do_otpprotect, "", ""), 2598 U_BOOT_CMD_MKENT(cmp, 3, 0, do_otpcmp, "", ""), 2599 }; 2600 2601 static int do_ast_otp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) 2602 { 2603 cmd_tbl_t *cp; 2604 2605 cp = find_cmd_tbl(argv[1], cmd_otp, ARRAY_SIZE(cmd_otp)); 2606 2607 /* Drop the otp command */ 2608 argc--; 2609 argv++; 2610 2611 if (cp == NULL || argc > cp->maxargs) 2612 return CMD_RET_USAGE; 2613 if (flag == CMD_FLAG_REPEAT && !cmd_is_repeatable(cp)) 2614 return CMD_RET_SUCCESS; 2615 2616 if (chip_version() == OTP_AST2600A0) { 2617 info_cb.version = OTP_AST2600A0; 2618 info_cb.conf_info = a0_conf_info; 2619 info_cb.conf_info_len = ARRAY_SIZE(a0_conf_info); 2620 info_cb.strap_info = a0_strap_info; 2621 info_cb.strap_info_len = ARRAY_SIZE(a0_strap_info); 2622 info_cb.key_info = a0_key_type; 2623 info_cb.key_info_len = ARRAY_SIZE(a0_key_type); 2624 } else if (chip_version() == OTP_AST2600A1) { 2625 info_cb.version = OTP_AST2600A1; 2626 info_cb.conf_info = a1_conf_info; 2627 info_cb.conf_info_len = ARRAY_SIZE(a1_conf_info); 2628 info_cb.strap_info = a1_strap_info; 2629 info_cb.strap_info_len = ARRAY_SIZE(a1_strap_info); 2630 info_cb.key_info = a1_key_type; 2631 info_cb.key_info_len = ARRAY_SIZE(a1_key_type); 2632 } else if (chip_version() == OTP_AST2600A2) { 2633 info_cb.version = OTP_AST2600A2; 2634 info_cb.conf_info = a2_conf_info; 2635 info_cb.conf_info_len = ARRAY_SIZE(a2_conf_info); 2636 info_cb.strap_info = a2_strap_info; 2637 info_cb.strap_info_len = ARRAY_SIZE(a2_strap_info); 2638 info_cb.key_info = a2_key_type; 2639 info_cb.key_info_len = ARRAY_SIZE(a2_key_type); 2640 } 2641 2642 return cp->cmd(cmdtp, flag, argc, argv); 2643 } 2644 2645 U_BOOT_CMD( 2646 otp, 7, 0, do_ast_otp, 2647 "ASPEED One-Time-Programmable sub-system", 2648 "read conf|data <otp_dw_offset> <dw_count>\n" 2649 "otp read strap <strap_bit_offset> <bit_count>\n" 2650 "otp info strap [v]\n" 2651 "otp info conf [otp_dw_offset]\n" 2652 "otp prog [o] <addr>\n" 2653 "otp pb conf|data [o] <otp_dw_offset> <bit_offset> <value>\n" 2654 "otp pb strap [o] <bit_offset> <value>\n" 2655 "otp protect [o] <bit_offset>\n" 2656 "otp cmp <addr> <otp_dw_offset>\n" 2657 ); 2658