1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) Xilinx, Inc.
4 */
5
6 #include <asm/arch/ps7_init_gpl.h>
7
8 unsigned long ps7_pll_init_data_3_0[] = {
9 /* START: top */
10 /* .. START: SLCR SETTINGS */
11 /* .. UNLOCK_KEY = 0XDF0D */
12 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
13 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
14 /* .. */
15 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
16 /* .. FINISH: SLCR SETTINGS */
17 /* .. START: PLL SLCR REGISTERS */
18 /* .. .. START: ARM PLL INIT */
19 /* .. .. PLL_RES = 0xc */
20 /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
21 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
22 /* .. .. PLL_CP = 0x2 */
23 /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
24 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
25 /* .. .. LOCK_CNT = 0x177 */
26 /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
27 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
28 /* .. .. */
29 EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
30 /* .. .. .. START: UPDATE FB_DIV */
31 /* .. .. .. PLL_FDIV = 0x1a */
32 /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
33 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
34 /* .. .. .. */
35 EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
36 /* .. .. .. FINISH: UPDATE FB_DIV */
37 /* .. .. .. START: BY PASS PLL */
38 /* .. .. .. PLL_BYPASS_FORCE = 1 */
39 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
40 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
41 /* .. .. .. */
42 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
43 /* .. .. .. FINISH: BY PASS PLL */
44 /* .. .. .. START: ASSERT RESET */
45 /* .. .. .. PLL_RESET = 1 */
46 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
47 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
48 /* .. .. .. */
49 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
50 /* .. .. .. FINISH: ASSERT RESET */
51 /* .. .. .. START: DEASSERT RESET */
52 /* .. .. .. PLL_RESET = 0 */
53 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
54 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
55 /* .. .. .. */
56 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
57 /* .. .. .. FINISH: DEASSERT RESET */
58 /* .. .. .. START: CHECK PLL STATUS */
59 /* .. .. .. ARM_PLL_LOCK = 1 */
60 /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
61 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
62 /* .. .. .. */
63 EMIT_MASKPOLL(0XF800010C, 0x00000001U),
64 /* .. .. .. FINISH: CHECK PLL STATUS */
65 /* .. .. .. START: REMOVE PLL BY PASS */
66 /* .. .. .. PLL_BYPASS_FORCE = 0 */
67 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
68 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
69 /* .. .. .. */
70 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
71 /* .. .. .. FINISH: REMOVE PLL BY PASS */
72 /* .. .. .. SRCSEL = 0x0 */
73 /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
74 /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
75 /* .. .. .. DIVISOR = 0x2 */
76 /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
77 /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
78 /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
79 /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
80 /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
81 /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
82 /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
83 /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
84 /* .. .. .. CPU_2XCLKACT = 0x1 */
85 /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
86 /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
87 /* .. .. .. CPU_1XCLKACT = 0x1 */
88 /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
89 /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
90 /* .. .. .. CPU_PERI_CLKACT = 0x1 */
91 /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
92 /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
93 /* .. .. .. */
94 EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
95 /* .. .. FINISH: ARM PLL INIT */
96 /* .. .. START: DDR PLL INIT */
97 /* .. .. PLL_RES = 0xc */
98 /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
99 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
100 /* .. .. PLL_CP = 0x2 */
101 /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
102 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
103 /* .. .. LOCK_CNT = 0x1db */
104 /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
105 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
106 /* .. .. */
107 EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
108 /* .. .. .. START: UPDATE FB_DIV */
109 /* .. .. .. PLL_FDIV = 0x15 */
110 /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
111 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
112 /* .. .. .. */
113 EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
114 /* .. .. .. FINISH: UPDATE FB_DIV */
115 /* .. .. .. START: BY PASS PLL */
116 /* .. .. .. PLL_BYPASS_FORCE = 1 */
117 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
118 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
119 /* .. .. .. */
120 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
121 /* .. .. .. FINISH: BY PASS PLL */
122 /* .. .. .. START: ASSERT RESET */
123 /* .. .. .. PLL_RESET = 1 */
124 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
125 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
126 /* .. .. .. */
127 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
128 /* .. .. .. FINISH: ASSERT RESET */
129 /* .. .. .. START: DEASSERT RESET */
130 /* .. .. .. PLL_RESET = 0 */
131 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
132 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
133 /* .. .. .. */
134 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
135 /* .. .. .. FINISH: DEASSERT RESET */
136 /* .. .. .. START: CHECK PLL STATUS */
137 /* .. .. .. DDR_PLL_LOCK = 1 */
138 /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
139 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
140 /* .. .. .. */
141 EMIT_MASKPOLL(0XF800010C, 0x00000002U),
142 /* .. .. .. FINISH: CHECK PLL STATUS */
143 /* .. .. .. START: REMOVE PLL BY PASS */
144 /* .. .. .. PLL_BYPASS_FORCE = 0 */
145 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
146 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
147 /* .. .. .. */
148 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
149 /* .. .. .. FINISH: REMOVE PLL BY PASS */
150 /* .. .. .. DDR_3XCLKACT = 0x1 */
151 /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
152 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
153 /* .. .. .. DDR_2XCLKACT = 0x1 */
154 /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
155 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
156 /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
157 /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
158 /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
159 /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
160 /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
161 /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
162 /* .. .. .. */
163 EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
164 /* .. .. FINISH: DDR PLL INIT */
165 /* .. .. START: IO PLL INIT */
166 /* .. .. PLL_RES = 0xc */
167 /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
168 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
169 /* .. .. PLL_CP = 0x2 */
170 /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
171 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
172 /* .. .. LOCK_CNT = 0x1f4 */
173 /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
174 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
175 /* .. .. */
176 EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
177 /* .. .. .. START: UPDATE FB_DIV */
178 /* .. .. .. PLL_FDIV = 0x14 */
179 /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
180 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
181 /* .. .. .. */
182 EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
183 /* .. .. .. FINISH: UPDATE FB_DIV */
184 /* .. .. .. START: BY PASS PLL */
185 /* .. .. .. PLL_BYPASS_FORCE = 1 */
186 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
187 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
188 /* .. .. .. */
189 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
190 /* .. .. .. FINISH: BY PASS PLL */
191 /* .. .. .. START: ASSERT RESET */
192 /* .. .. .. PLL_RESET = 1 */
193 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
194 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
195 /* .. .. .. */
196 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
197 /* .. .. .. FINISH: ASSERT RESET */
198 /* .. .. .. START: DEASSERT RESET */
199 /* .. .. .. PLL_RESET = 0 */
200 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
201 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
202 /* .. .. .. */
203 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
204 /* .. .. .. FINISH: DEASSERT RESET */
205 /* .. .. .. START: CHECK PLL STATUS */
206 /* .. .. .. IO_PLL_LOCK = 1 */
207 /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
208 /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
209 /* .. .. .. */
210 EMIT_MASKPOLL(0XF800010C, 0x00000004U),
211 /* .. .. .. FINISH: CHECK PLL STATUS */
212 /* .. .. .. START: REMOVE PLL BY PASS */
213 /* .. .. .. PLL_BYPASS_FORCE = 0 */
214 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
215 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
216 /* .. .. .. */
217 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
218 /* .. .. .. FINISH: REMOVE PLL BY PASS */
219 /* .. .. FINISH: IO PLL INIT */
220 /* .. FINISH: PLL SLCR REGISTERS */
221 /* .. START: LOCK IT BACK */
222 /* .. LOCK_KEY = 0X767B */
223 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
224 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
225 /* .. */
226 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
227 /* .. FINISH: LOCK IT BACK */
228 /* FINISH: top */
229 /* */
230 EMIT_EXIT(),
231
232 /* */
233 };
234
235 unsigned long ps7_clock_init_data_3_0[] = {
236 /* START: top */
237 /* .. START: SLCR SETTINGS */
238 /* .. UNLOCK_KEY = 0XDF0D */
239 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
240 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
241 /* .. */
242 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
243 /* .. FINISH: SLCR SETTINGS */
244 /* .. START: CLOCK CONTROL SLCR REGISTERS */
245 /* .. CLKACT = 0x1 */
246 /* .. ==> 0XF8000128[0:0] = 0x00000001U */
247 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
248 /* .. DIVISOR0 = 0x34 */
249 /* .. ==> 0XF8000128[13:8] = 0x00000034U */
250 /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
251 /* .. DIVISOR1 = 0x2 */
252 /* .. ==> 0XF8000128[25:20] = 0x00000002U */
253 /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
254 /* .. */
255 EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
256 /* .. CLKACT = 0x1 */
257 /* .. ==> 0XF8000138[0:0] = 0x00000001U */
258 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
259 /* .. SRCSEL = 0x0 */
260 /* .. ==> 0XF8000138[4:4] = 0x00000000U */
261 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
262 /* .. */
263 EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
264 /* .. CLKACT = 0x1 */
265 /* .. ==> 0XF8000140[0:0] = 0x00000001U */
266 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
267 /* .. SRCSEL = 0x0 */
268 /* .. ==> 0XF8000140[6:4] = 0x00000000U */
269 /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
270 /* .. DIVISOR = 0x8 */
271 /* .. ==> 0XF8000140[13:8] = 0x00000008U */
272 /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
273 /* .. DIVISOR1 = 0x1 */
274 /* .. ==> 0XF8000140[25:20] = 0x00000001U */
275 /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
276 /* .. */
277 EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
278 /* .. CLKACT = 0x1 */
279 /* .. ==> 0XF800014C[0:0] = 0x00000001U */
280 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
281 /* .. SRCSEL = 0x0 */
282 /* .. ==> 0XF800014C[5:4] = 0x00000000U */
283 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
284 /* .. DIVISOR = 0x5 */
285 /* .. ==> 0XF800014C[13:8] = 0x00000005U */
286 /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
287 /* .. */
288 EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
289 /* .. CLKACT0 = 0x1 */
290 /* .. ==> 0XF8000150[0:0] = 0x00000001U */
291 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
292 /* .. CLKACT1 = 0x0 */
293 /* .. ==> 0XF8000150[1:1] = 0x00000000U */
294 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
295 /* .. SRCSEL = 0x0 */
296 /* .. ==> 0XF8000150[5:4] = 0x00000000U */
297 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
298 /* .. DIVISOR = 0x14 */
299 /* .. ==> 0XF8000150[13:8] = 0x00000014U */
300 /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
301 /* .. */
302 EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
303 /* .. CLKACT0 = 0x0 */
304 /* .. ==> 0XF8000154[0:0] = 0x00000000U */
305 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
306 /* .. CLKACT1 = 0x1 */
307 /* .. ==> 0XF8000154[1:1] = 0x00000001U */
308 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
309 /* .. SRCSEL = 0x0 */
310 /* .. ==> 0XF8000154[5:4] = 0x00000000U */
311 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
312 /* .. DIVISOR = 0xa */
313 /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
314 /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
315 /* .. */
316 EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
317 /* .. .. START: TRACE CLOCK */
318 /* .. .. FINISH: TRACE CLOCK */
319 /* .. .. CLKACT = 0x1 */
320 /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
321 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
322 /* .. .. SRCSEL = 0x0 */
323 /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
324 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
325 /* .. .. DIVISOR = 0x5 */
326 /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
327 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
328 /* .. .. */
329 EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
330 /* .. .. SRCSEL = 0x0 */
331 /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
332 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
333 /* .. .. DIVISOR0 = 0xa */
334 /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
335 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
336 /* .. .. DIVISOR1 = 0x1 */
337 /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
338 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
339 /* .. .. */
340 EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
341 /* .. .. SRCSEL = 0x0 */
342 /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
343 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
344 /* .. .. DIVISOR0 = 0x7 */
345 /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
346 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
347 /* .. .. DIVISOR1 = 0x1 */
348 /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
349 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
350 /* .. .. */
351 EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
352 /* .. .. SRCSEL = 0x0 */
353 /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
354 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
355 /* .. .. DIVISOR0 = 0x5 */
356 /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
357 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
358 /* .. .. DIVISOR1 = 0x1 */
359 /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
360 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
361 /* .. .. */
362 EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
363 /* .. .. SRCSEL = 0x0 */
364 /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
365 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
366 /* .. .. DIVISOR0 = 0x14 */
367 /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
368 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
369 /* .. .. DIVISOR1 = 0x1 */
370 /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
371 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
372 /* .. .. */
373 EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
374 /* .. .. CLK_621_TRUE = 0x1 */
375 /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
376 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
377 /* .. .. */
378 EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
379 /* .. .. DMA_CPU_2XCLKACT = 0x1 */
380 /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
381 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
382 /* .. .. USB0_CPU_1XCLKACT = 0x1 */
383 /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
384 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
385 /* .. .. USB1_CPU_1XCLKACT = 0x1 */
386 /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
387 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
388 /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
389 /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
390 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
391 /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
392 /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
393 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
394 /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
395 /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
396 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
397 /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
398 /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
399 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
400 /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
401 /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
402 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
403 /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
404 /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
405 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
406 /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
407 /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
408 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
409 /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
410 /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
411 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
412 /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
413 /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
414 /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
415 /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
416 /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
417 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
418 /* .. .. UART0_CPU_1XCLKACT = 0x0 */
419 /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
420 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
421 /* .. .. UART1_CPU_1XCLKACT = 0x1 */
422 /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
423 /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
424 /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
425 /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
426 /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
427 /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
428 /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
429 /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
430 /* .. .. SMC_CPU_1XCLKACT = 0x1 */
431 /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
432 /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
433 /* .. .. */
434 EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
435 /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
436 /* .. START: THIS SHOULD BE BLANK */
437 /* .. FINISH: THIS SHOULD BE BLANK */
438 /* .. START: LOCK IT BACK */
439 /* .. LOCK_KEY = 0X767B */
440 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
441 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
442 /* .. */
443 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
444 /* .. FINISH: LOCK IT BACK */
445 /* FINISH: top */
446 /* */
447 EMIT_EXIT(),
448
449 /* */
450 };
451
452 unsigned long ps7_ddr_init_data_3_0[] = {
453 /* START: top */
454 /* .. START: DDR INITIALIZATION */
455 /* .. .. START: LOCK DDR */
456 /* .. .. reg_ddrc_soft_rstb = 0 */
457 /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
458 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
459 /* .. .. reg_ddrc_powerdown_en = 0x0 */
460 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
461 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
462 /* .. .. reg_ddrc_data_bus_width = 0x0 */
463 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
464 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
465 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
466 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
467 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
468 /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
469 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
470 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
471 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
472 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
473 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
474 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
475 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
476 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
477 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
478 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
479 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
480 /* .. .. */
481 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
482 /* .. .. FINISH: LOCK DDR */
483 /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
484 /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
485 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
486 /* .. .. reserved_reg_ddrc_active_ranks = 0x1 */
487 /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
488 /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
489 /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
490 /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
491 /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
492 /* .. .. */
493 EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x0000107FU),
494 /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
495 /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
496 /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
497 /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
498 /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
499 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
500 /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
501 /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
502 /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
503 /* .. .. */
504 EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
505 /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
506 /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
507 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
508 /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
509 /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
510 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
511 /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
512 /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
513 /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
514 /* .. .. */
515 EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
516 /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
517 /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
518 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
519 /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
520 /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
521 /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
522 /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
523 /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
524 /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
525 /* .. .. */
526 EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
527 /* .. .. reg_ddrc_t_rc = 0x1a */
528 /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
529 /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
530 /* .. .. reg_ddrc_t_rfc_min = 0x54 */
531 /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
532 /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
533 /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
534 /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
535 /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
536 /* .. .. */
537 EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
538 /* .. .. reg_ddrc_wr2pre = 0x12 */
539 /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
540 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
541 /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
542 /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
543 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
544 /* .. .. reg_ddrc_t_faw = 0x15 */
545 /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
546 /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
547 /* .. .. reg_ddrc_t_ras_max = 0x23 */
548 /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
549 /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
550 /* .. .. reg_ddrc_t_ras_min = 0x13 */
551 /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
552 /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
553 /* .. .. reg_ddrc_t_cke = 0x4 */
554 /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
555 /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
556 /* .. .. */
557 EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
558 /* .. .. reg_ddrc_write_latency = 0x5 */
559 /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
560 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
561 /* .. .. reg_ddrc_rd2wr = 0x7 */
562 /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
563 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
564 /* .. .. reg_ddrc_wr2rd = 0xe */
565 /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
566 /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
567 /* .. .. reg_ddrc_t_xp = 0x4 */
568 /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
569 /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
570 /* .. .. reg_ddrc_pad_pd = 0x0 */
571 /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
572 /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
573 /* .. .. reg_ddrc_rd2pre = 0x4 */
574 /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
575 /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
576 /* .. .. reg_ddrc_t_rcd = 0x7 */
577 /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
578 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
579 /* .. .. */
580 EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
581 /* .. .. reg_ddrc_t_ccd = 0x4 */
582 /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
583 /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
584 /* .. .. reg_ddrc_t_rrd = 0x6 */
585 /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
586 /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
587 /* .. .. reg_ddrc_refresh_margin = 0x2 */
588 /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
589 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
590 /* .. .. reg_ddrc_t_rp = 0x7 */
591 /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
592 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
593 /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
594 /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
595 /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
596 /* .. .. reg_ddrc_mobile = 0x0 */
597 /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
598 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
599 /* .. .. reg_ddrc_en_dfi_dram_clk_disable = 0x0 */
600 /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
601 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
602 /* .. .. reg_ddrc_read_latency = 0x7 */
603 /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
604 /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
605 /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
606 /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
607 /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
608 /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
609 /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
610 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
611 /* .. .. */
612 EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
613 /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
614 /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
615 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
616 /* .. .. reg_ddrc_prefer_write = 0x0 */
617 /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
618 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
619 /* .. .. reg_ddrc_mr_wr = 0x0 */
620 /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
621 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
622 /* .. .. reg_ddrc_mr_addr = 0x0 */
623 /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
624 /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
625 /* .. .. reg_ddrc_mr_data = 0x0 */
626 /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
627 /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
628 /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
629 /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
630 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
631 /* .. .. reg_ddrc_mr_type = 0x0 */
632 /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
633 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
634 /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
635 /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
636 /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
637 /* .. .. */
638 EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
639 /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
640 /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
641 /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
642 /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
643 /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
644 /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
645 /* .. .. reg_ddrc_t_mrd = 0x4 */
646 /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
647 /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
648 /* .. .. */
649 EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
650 /* .. .. reg_ddrc_emr2 = 0x8 */
651 /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
652 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
653 /* .. .. reg_ddrc_emr3 = 0x0 */
654 /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
655 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
656 /* .. .. */
657 EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
658 /* .. .. reg_ddrc_mr = 0x930 */
659 /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
660 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
661 /* .. .. reg_ddrc_emr = 0x4 */
662 /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
663 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
664 /* .. .. */
665 EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
666 /* .. .. reg_ddrc_burst_rdwr = 0x4 */
667 /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
668 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
669 /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
670 /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
671 /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
672 /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
673 /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
674 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
675 /* .. .. reg_ddrc_burstchop = 0x0 */
676 /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
677 /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
678 /* .. .. */
679 EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
680 /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
681 /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
682 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
683 /* .. .. reg_ddrc_dis_dq = 0x0 */
684 /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
685 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
686 /* .. .. */
687 EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
688 /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
689 /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
690 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
691 /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
692 /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
693 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
694 /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
695 /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
696 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
697 /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
698 /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
699 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
700 /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
701 /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
702 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
703 /* .. .. */
704 EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
705 /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
706 /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
707 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
708 /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
709 /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
710 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
711 /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
712 /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
713 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
714 /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
715 /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
716 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
717 /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
718 /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
719 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
720 /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
721 /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
722 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
723 /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
724 /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
725 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
726 /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
727 /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
728 /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
729 /* .. .. */
730 EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
731 /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
732 /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
733 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
734 /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
735 /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
736 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
737 /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
738 /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
739 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
740 /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
741 /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
742 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
743 /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
744 /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
745 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
746 /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
747 /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
748 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
749 /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
750 /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
751 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
752 /* .. .. */
753 EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
754 /* .. .. reg_phy_rd_local_odt = 0x0 */
755 /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
756 /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
757 /* .. .. reg_phy_wr_local_odt = 0x3 */
758 /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
759 /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
760 /* .. .. reg_phy_idle_local_odt = 0x3 */
761 /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
762 /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
763 /* .. .. reserved_reg_ddrc_rank0_wr_odt = 0x1 */
764 /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
765 /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
766 /* .. .. reserved_reg_ddrc_rank0_rd_odt = 0x0 */
767 /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
768 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
769 /* .. .. */
770 EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
771 /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
772 /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
773 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
774 /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
775 /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
776 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
777 /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
778 /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
779 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
780 /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
781 /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
782 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
783 /* .. .. reg_phy_use_fixed_re = 0x1 */
784 /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
785 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
786 /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
787 /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
788 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
789 /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
790 /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
791 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
792 /* .. .. reg_phy_clk_stall_level = 0x0 */
793 /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
794 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
795 /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
796 /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
797 /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
798 /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
799 /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
800 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
801 /* .. .. */
802 EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
803 /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
804 /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
805 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
806 /* .. .. */
807 EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
808 /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
809 /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
810 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
811 /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
812 /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
813 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
814 /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
815 /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
816 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
817 /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
818 /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
819 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
820 /* .. .. */
821 EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
822 /* .. .. reg_ddrc_pageclose = 0x0 */
823 /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
824 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
825 /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
826 /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
827 /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
828 /* .. .. reg_ddrc_auto_pre_en = 0x0 */
829 /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
830 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
831 /* .. .. reg_ddrc_refresh_update_level = 0x0 */
832 /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
833 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
834 /* .. .. reg_ddrc_dis_wc = 0x0 */
835 /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
836 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
837 /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
838 /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
839 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
840 /* .. .. reg_ddrc_selfref_en = 0x0 */
841 /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
842 /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
843 /* .. .. */
844 EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
845 /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
846 /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
847 /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
848 /* .. .. reg_arb_go2critical_en = 0x1 */
849 /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
850 /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
851 /* .. .. */
852 EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
853 /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
854 /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
855 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
856 /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
857 /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
858 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
859 /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
860 /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
861 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
862 /* .. .. */
863 EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
864 /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
865 /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
866 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
867 /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
868 /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
869 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
870 /* .. .. */
871 EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
872 /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
873 /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
874 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
875 /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
876 /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
877 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
878 /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
879 /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
880 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
881 /* .. .. reg_ddrc_t_cksre = 0x6 */
882 /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
883 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
884 /* .. .. reg_ddrc_t_cksrx = 0x6 */
885 /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
886 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
887 /* .. .. reg_ddrc_t_ckesr = 0x4 */
888 /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
889 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
890 /* .. .. */
891 EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
892 /* .. .. reg_ddrc_t_ckpde = 0x2 */
893 /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
894 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
895 /* .. .. reg_ddrc_t_ckpdx = 0x2 */
896 /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
897 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
898 /* .. .. reg_ddrc_t_ckdpde = 0x2 */
899 /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
900 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
901 /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
902 /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
903 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
904 /* .. .. reg_ddrc_t_ckcsx = 0x3 */
905 /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
906 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
907 /* .. .. */
908 EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
909 /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
910 /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
911 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
912 /* .. .. reg_ddrc_ddr3 = 0x1 */
913 /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
914 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
915 /* .. .. reg_ddrc_t_mod = 0x200 */
916 /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
917 /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
918 /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
919 /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
920 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
921 /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
922 /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
923 /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
924 /* .. .. */
925 EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
926 /* .. .. t_zq_short_interval_x1024 = 0xc845 */
927 /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
928 /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
929 /* .. .. dram_rstn_x1024 = 0x67 */
930 /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
931 /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
932 /* .. .. */
933 EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
934 /* .. .. deeppowerdown_en = 0x0 */
935 /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
936 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
937 /* .. .. deeppowerdown_to_x1024 = 0xff */
938 /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
939 /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
940 /* .. .. */
941 EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
942 /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
943 /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
944 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
945 /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
946 /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
947 /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
948 /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
949 /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
950 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
951 /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
952 /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
953 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
954 /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
955 /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
956 /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
957 /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
958 /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
959 /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
960 /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
961 /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
962 /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
963 /* .. .. */
964 EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
965 /* .. .. reg_ddrc_skip_ocd = 0x1 */
966 /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
967 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
968 /* .. .. */
969 EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
970 /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
971 /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
972 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
973 /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
974 /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
975 /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
976 /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
977 /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
978 /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
979 /* .. .. */
980 EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
981 /* .. .. START: RESET ECC ERROR */
982 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
983 /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
984 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
985 /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
986 /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
987 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
988 /* .. .. */
989 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
990 /* .. .. FINISH: RESET ECC ERROR */
991 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
992 /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
993 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
994 /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
995 /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
996 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
997 /* .. .. */
998 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
999 /* .. .. CORR_ECC_LOG_VALID = 0x0 */
1000 /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
1001 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1002 /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
1003 /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
1004 /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
1005 /* .. .. */
1006 EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
1007 /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
1008 /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
1009 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1010 /* .. .. */
1011 EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
1012 /* .. .. STAT_NUM_CORR_ERR = 0x0 */
1013 /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
1014 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
1015 /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
1016 /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
1017 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
1018 /* .. .. */
1019 EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
1020 /* .. .. reg_ddrc_ecc_mode = 0x0 */
1021 /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
1022 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
1023 /* .. .. reg_ddrc_dis_scrub = 0x1 */
1024 /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
1025 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
1026 /* .. .. */
1027 EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
1028 /* .. .. reg_phy_dif_on = 0x0 */
1029 /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
1030 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
1031 /* .. .. reg_phy_dif_off = 0x0 */
1032 /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
1033 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
1034 /* .. .. */
1035 EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
1036 /* .. .. reg_phy_data_slice_in_use = 0x1 */
1037 /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
1038 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1039 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
1040 /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
1041 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1042 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
1043 /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
1044 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1045 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
1046 /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
1047 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1048 /* .. .. reg_phy_bist_shift_dq = 0x0 */
1049 /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
1050 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
1051 /* .. .. reg_phy_bist_err_clr = 0x0 */
1052 /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
1053 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
1054 /* .. .. reg_phy_dq_offset = 0x40 */
1055 /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
1056 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
1057 /* .. .. */
1058 EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
1059 /* .. .. reg_phy_data_slice_in_use = 0x1 */
1060 /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
1061 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1062 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
1063 /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
1064 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1065 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
1066 /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
1067 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1068 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
1069 /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
1070 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1071 /* .. .. reg_phy_bist_shift_dq = 0x0 */
1072 /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
1073 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
1074 /* .. .. reg_phy_bist_err_clr = 0x0 */
1075 /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
1076 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
1077 /* .. .. reg_phy_dq_offset = 0x40 */
1078 /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
1079 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
1080 /* .. .. */
1081 EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
1082 /* .. .. reg_phy_data_slice_in_use = 0x1 */
1083 /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
1084 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1085 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
1086 /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
1087 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1088 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
1089 /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
1090 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1091 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
1092 /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
1093 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1094 /* .. .. reg_phy_bist_shift_dq = 0x0 */
1095 /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
1096 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
1097 /* .. .. reg_phy_bist_err_clr = 0x0 */
1098 /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
1099 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
1100 /* .. .. reg_phy_dq_offset = 0x40 */
1101 /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
1102 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
1103 /* .. .. */
1104 EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
1105 /* .. .. reg_phy_data_slice_in_use = 0x1 */
1106 /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
1107 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1108 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
1109 /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
1110 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1111 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
1112 /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
1113 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1114 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
1115 /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
1116 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1117 /* .. .. reg_phy_bist_shift_dq = 0x0 */
1118 /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
1119 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
1120 /* .. .. reg_phy_bist_err_clr = 0x0 */
1121 /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
1122 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
1123 /* .. .. reg_phy_dq_offset = 0x40 */
1124 /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
1125 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
1126 /* .. .. */
1127 EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
1128 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
1129 /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
1130 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
1131 /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
1132 /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
1133 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
1134 /* .. .. */
1135 EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
1136 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
1137 /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
1138 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
1139 /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
1140 /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
1141 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
1142 /* .. .. */
1143 EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
1144 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
1145 /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
1146 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
1147 /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
1148 /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
1149 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
1150 /* .. .. */
1151 EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
1152 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
1153 /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
1154 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
1155 /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
1156 /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
1157 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
1158 /* .. .. */
1159 EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
1160 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
1161 /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
1162 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
1163 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
1164 /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
1165 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1166 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
1167 /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
1168 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1169 /* .. .. */
1170 EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
1171 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
1172 /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
1173 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
1174 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
1175 /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
1176 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1177 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
1178 /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
1179 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1180 /* .. .. */
1181 EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
1182 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
1183 /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
1184 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
1185 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
1186 /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
1187 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1188 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
1189 /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
1190 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1191 /* .. .. */
1192 EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
1193 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
1194 /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
1195 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
1196 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
1197 /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
1198 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1199 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
1200 /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
1201 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1202 /* .. .. */
1203 EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
1204 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
1205 /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
1206 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
1207 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
1208 /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
1209 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1210 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
1211 /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
1212 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1213 /* .. .. */
1214 EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
1215 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
1216 /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
1217 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
1218 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
1219 /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
1220 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1221 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
1222 /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
1223 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1224 /* .. .. */
1225 EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
1226 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
1227 /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
1228 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
1229 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
1230 /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
1231 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1232 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
1233 /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
1234 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1235 /* .. .. */
1236 EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
1237 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
1238 /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
1239 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
1240 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
1241 /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
1242 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1243 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
1244 /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
1245 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1246 /* .. .. */
1247 EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
1248 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
1249 /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
1250 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
1251 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
1252 /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
1253 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1254 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
1255 /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
1256 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
1257 /* .. .. */
1258 EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
1259 /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
1260 /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
1261 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
1262 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
1263 /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
1264 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1265 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
1266 /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
1267 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
1268 /* .. .. */
1269 EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
1270 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
1271 /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
1272 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
1273 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
1274 /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
1275 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1276 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
1277 /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
1278 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
1279 /* .. .. */
1280 EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
1281 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
1282 /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
1283 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
1284 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
1285 /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
1286 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1287 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
1288 /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
1289 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
1290 /* .. .. */
1291 EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
1292 /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
1293 /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
1294 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
1295 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
1296 /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
1297 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1298 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
1299 /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
1300 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1301 /* .. .. */
1302 EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
1303 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
1304 /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
1305 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
1306 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
1307 /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
1308 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1309 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
1310 /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
1311 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1312 /* .. .. */
1313 EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
1314 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
1315 /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
1316 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
1317 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
1318 /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
1319 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1320 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
1321 /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
1322 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1323 /* .. .. */
1324 EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
1325 /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
1326 /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
1327 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
1328 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
1329 /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
1330 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
1331 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
1332 /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
1333 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
1334 /* .. .. */
1335 EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
1336 /* .. .. reg_phy_bl2 = 0x0 */
1337 /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
1338 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1339 /* .. .. reg_phy_at_spd_atpg = 0x0 */
1340 /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
1341 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1342 /* .. .. reg_phy_bist_enable = 0x0 */
1343 /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
1344 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1345 /* .. .. reg_phy_bist_force_err = 0x0 */
1346 /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
1347 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
1348 /* .. .. reg_phy_bist_mode = 0x0 */
1349 /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
1350 /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
1351 /* .. .. reg_phy_invert_clkout = 0x1 */
1352 /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
1353 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
1354 /* .. .. reg_phy_sel_logic = 0x0 */
1355 /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
1356 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
1357 /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
1358 /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
1359 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
1360 /* .. .. reg_phy_ctrl_slave_force = 0x0 */
1361 /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
1362 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
1363 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
1364 /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
1365 /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
1366 /* .. .. reg_phy_lpddr = 0x0 */
1367 /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
1368 /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
1369 /* .. .. reg_phy_cmd_latency = 0x0 */
1370 /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
1371 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
1372 /* .. .. */
1373 EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
1374 /* .. .. reg_phy_wr_rl_delay = 0x2 */
1375 /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
1376 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
1377 /* .. .. reg_phy_rd_rl_delay = 0x4 */
1378 /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
1379 /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
1380 /* .. .. reg_phy_dll_lock_diff = 0xf */
1381 /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
1382 /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
1383 /* .. .. reg_phy_use_wr_level = 0x1 */
1384 /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
1385 /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
1386 /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
1387 /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
1388 /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
1389 /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
1390 /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
1391 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
1392 /* .. .. reg_phy_dis_calib_rst = 0x0 */
1393 /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
1394 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1395 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
1396 /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
1397 /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
1398 /* .. .. */
1399 EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
1400 /* .. .. reg_arb_page_addr_mask = 0x0 */
1401 /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
1402 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
1403 /* .. .. */
1404 EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
1405 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
1406 /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
1407 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1408 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
1409 /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
1410 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1411 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
1412 /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
1413 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1414 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
1415 /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
1416 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1417 /* .. .. */
1418 EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
1419 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
1420 /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
1421 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1422 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
1423 /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
1424 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1425 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
1426 /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
1427 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1428 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
1429 /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
1430 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1431 /* .. .. */
1432 EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
1433 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
1434 /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
1435 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1436 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
1437 /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
1438 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1439 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
1440 /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
1441 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1442 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
1443 /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
1444 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1445 /* .. .. */
1446 EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
1447 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
1448 /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
1449 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1450 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
1451 /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
1452 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1453 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
1454 /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
1455 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1456 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
1457 /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
1458 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1459 /* .. .. */
1460 EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
1461 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
1462 /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
1463 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1464 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
1465 /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
1466 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1467 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
1468 /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
1469 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1470 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
1471 /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
1472 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1473 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
1474 /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
1475 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
1476 /* .. .. */
1477 EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
1478 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
1479 /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
1480 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1481 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
1482 /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
1483 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1484 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
1485 /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
1486 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1487 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
1488 /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
1489 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1490 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
1491 /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
1492 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
1493 /* .. .. */
1494 EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
1495 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
1496 /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
1497 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1498 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
1499 /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
1500 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1501 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
1502 /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
1503 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1504 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
1505 /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
1506 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1507 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
1508 /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
1509 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
1510 /* .. .. */
1511 EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
1512 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
1513 /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
1514 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
1515 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
1516 /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
1517 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1518 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
1519 /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
1520 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
1521 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
1522 /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
1523 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
1524 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
1525 /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
1526 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
1527 /* .. .. */
1528 EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
1529 /* .. .. reg_ddrc_lpddr2 = 0x0 */
1530 /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
1531 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1532 /* .. .. reg_ddrc_derate_enable = 0x0 */
1533 /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
1534 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1535 /* .. .. reg_ddrc_mr4_margin = 0x0 */
1536 /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
1537 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
1538 /* .. .. */
1539 EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
1540 /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
1541 /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
1542 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
1543 /* .. .. */
1544 EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
1545 /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
1546 /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
1547 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
1548 /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
1549 /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
1550 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
1551 /* .. .. reg_ddrc_t_mrw = 0x5 */
1552 /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
1553 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
1554 /* .. .. */
1555 EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
1556 /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
1557 /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
1558 /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
1559 /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
1560 /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
1561 /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
1562 /* .. .. */
1563 EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
1564 /* .. .. START: POLL ON DCI STATUS */
1565 /* .. .. DONE = 1 */
1566 /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
1567 /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
1568 /* .. .. */
1569 EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
1570 /* .. .. FINISH: POLL ON DCI STATUS */
1571 /* .. .. START: UNLOCK DDR */
1572 /* .. .. reg_ddrc_soft_rstb = 0x1 */
1573 /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
1574 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1575 /* .. .. reg_ddrc_powerdown_en = 0x0 */
1576 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
1577 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
1578 /* .. .. reg_ddrc_data_bus_width = 0x0 */
1579 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
1580 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
1581 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
1582 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
1583 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
1584 /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
1585 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
1586 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
1587 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
1588 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
1589 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
1590 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
1591 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
1592 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
1593 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
1594 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
1595 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
1596 /* .. .. */
1597 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
1598 /* .. .. FINISH: UNLOCK DDR */
1599 /* .. .. START: CHECK DDR STATUS */
1600 /* .. .. ddrc_reg_operating_mode = 1 */
1601 /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
1602 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
1603 /* .. .. */
1604 EMIT_MASKPOLL(0XF8006054, 0x00000007U),
1605 /* .. .. FINISH: CHECK DDR STATUS */
1606 /* .. FINISH: DDR INITIALIZATION */
1607 /* FINISH: top */
1608 /* */
1609 EMIT_EXIT(),
1610
1611 /* */
1612 };
1613
1614 unsigned long ps7_mio_init_data_3_0[] = {
1615 /* START: top */
1616 /* .. START: SLCR SETTINGS */
1617 /* .. UNLOCK_KEY = 0XDF0D */
1618 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
1619 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
1620 /* .. */
1621 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
1622 /* .. FINISH: SLCR SETTINGS */
1623 /* .. START: OCM REMAPPING */
1624 /* .. VREF_EN = 0x1 */
1625 /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
1626 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1627 /* .. VREF_SEL = 0x0 */
1628 /* .. ==> 0XF8000B00[6:4] = 0x00000000U */
1629 /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
1630 /* .. */
1631 EMIT_MASKWRITE(0XF8000B00, 0x00000071U, 0x00000001U),
1632 /* .. FINISH: OCM REMAPPING */
1633 /* .. START: DDRIOB SETTINGS */
1634 /* .. reserved_INP_POWER = 0x0 */
1635 /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
1636 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1637 /* .. INP_TYPE = 0x0 */
1638 /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
1639 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
1640 /* .. DCI_UPDATE_B = 0x0 */
1641 /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
1642 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1643 /* .. TERM_EN = 0x0 */
1644 /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
1645 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
1646 /* .. DCI_TYPE = 0x0 */
1647 /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
1648 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
1649 /* .. IBUF_DISABLE_MODE = 0x0 */
1650 /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
1651 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1652 /* .. TERM_DISABLE_MODE = 0x0 */
1653 /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
1654 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1655 /* .. OUTPUT_EN = 0x3 */
1656 /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
1657 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1658 /* .. PULLUP_EN = 0x0 */
1659 /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
1660 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1661 /* .. */
1662 EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
1663 /* .. reserved_INP_POWER = 0x0 */
1664 /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
1665 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1666 /* .. INP_TYPE = 0x0 */
1667 /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
1668 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
1669 /* .. DCI_UPDATE_B = 0x0 */
1670 /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
1671 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1672 /* .. TERM_EN = 0x0 */
1673 /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
1674 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
1675 /* .. DCI_TYPE = 0x0 */
1676 /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
1677 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
1678 /* .. IBUF_DISABLE_MODE = 0x0 */
1679 /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
1680 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1681 /* .. TERM_DISABLE_MODE = 0x0 */
1682 /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
1683 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1684 /* .. OUTPUT_EN = 0x3 */
1685 /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
1686 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1687 /* .. PULLUP_EN = 0x0 */
1688 /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
1689 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1690 /* .. */
1691 EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
1692 /* .. reserved_INP_POWER = 0x0 */
1693 /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
1694 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1695 /* .. INP_TYPE = 0x1 */
1696 /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
1697 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
1698 /* .. DCI_UPDATE_B = 0x0 */
1699 /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
1700 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1701 /* .. TERM_EN = 0x1 */
1702 /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
1703 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
1704 /* .. DCI_TYPE = 0x3 */
1705 /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
1706 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
1707 /* .. IBUF_DISABLE_MODE = 0 */
1708 /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
1709 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1710 /* .. TERM_DISABLE_MODE = 0 */
1711 /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
1712 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1713 /* .. OUTPUT_EN = 0x3 */
1714 /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
1715 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1716 /* .. PULLUP_EN = 0x0 */
1717 /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
1718 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1719 /* .. */
1720 EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
1721 /* .. reserved_INP_POWER = 0x0 */
1722 /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
1723 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1724 /* .. INP_TYPE = 0x1 */
1725 /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
1726 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
1727 /* .. DCI_UPDATE_B = 0x0 */
1728 /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
1729 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1730 /* .. TERM_EN = 0x1 */
1731 /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
1732 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
1733 /* .. DCI_TYPE = 0x3 */
1734 /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
1735 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
1736 /* .. IBUF_DISABLE_MODE = 0 */
1737 /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
1738 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1739 /* .. TERM_DISABLE_MODE = 0 */
1740 /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
1741 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1742 /* .. OUTPUT_EN = 0x3 */
1743 /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
1744 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1745 /* .. PULLUP_EN = 0x0 */
1746 /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
1747 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1748 /* .. */
1749 EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
1750 /* .. reserved_INP_POWER = 0x0 */
1751 /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
1752 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1753 /* .. INP_TYPE = 0x2 */
1754 /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
1755 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
1756 /* .. DCI_UPDATE_B = 0x0 */
1757 /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
1758 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1759 /* .. TERM_EN = 0x1 */
1760 /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
1761 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
1762 /* .. DCI_TYPE = 0x3 */
1763 /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
1764 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
1765 /* .. IBUF_DISABLE_MODE = 0 */
1766 /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
1767 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1768 /* .. TERM_DISABLE_MODE = 0 */
1769 /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
1770 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1771 /* .. OUTPUT_EN = 0x3 */
1772 /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
1773 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1774 /* .. PULLUP_EN = 0x0 */
1775 /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
1776 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1777 /* .. */
1778 EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
1779 /* .. reserved_INP_POWER = 0x0 */
1780 /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
1781 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1782 /* .. INP_TYPE = 0x2 */
1783 /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
1784 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
1785 /* .. DCI_UPDATE_B = 0x0 */
1786 /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
1787 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1788 /* .. TERM_EN = 0x1 */
1789 /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
1790 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
1791 /* .. DCI_TYPE = 0x3 */
1792 /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
1793 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
1794 /* .. IBUF_DISABLE_MODE = 0 */
1795 /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
1796 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1797 /* .. TERM_DISABLE_MODE = 0 */
1798 /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
1799 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1800 /* .. OUTPUT_EN = 0x3 */
1801 /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
1802 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1803 /* .. PULLUP_EN = 0x0 */
1804 /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
1805 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1806 /* .. */
1807 EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
1808 /* .. reserved_INP_POWER = 0x0 */
1809 /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
1810 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1811 /* .. INP_TYPE = 0x0 */
1812 /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
1813 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
1814 /* .. DCI_UPDATE_B = 0x0 */
1815 /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
1816 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1817 /* .. TERM_EN = 0x0 */
1818 /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
1819 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
1820 /* .. DCI_TYPE = 0x0 */
1821 /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
1822 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
1823 /* .. IBUF_DISABLE_MODE = 0x0 */
1824 /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
1825 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
1826 /* .. TERM_DISABLE_MODE = 0x0 */
1827 /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
1828 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
1829 /* .. OUTPUT_EN = 0x3 */
1830 /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
1831 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
1832 /* .. PULLUP_EN = 0x0 */
1833 /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
1834 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
1835 /* .. */
1836 EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
1837 /* .. reserved_DRIVE_P = 0x1c */
1838 /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
1839 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
1840 /* .. reserved_DRIVE_N = 0xc */
1841 /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
1842 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
1843 /* .. reserved_SLEW_P = 0x3 */
1844 /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
1845 /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
1846 /* .. reserved_SLEW_N = 0x3 */
1847 /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
1848 /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
1849 /* .. reserved_GTL = 0x0 */
1850 /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
1851 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
1852 /* .. reserved_RTERM = 0x0 */
1853 /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
1854 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
1855 /* .. */
1856 EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
1857 /* .. reserved_DRIVE_P = 0x1c */
1858 /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
1859 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
1860 /* .. reserved_DRIVE_N = 0xc */
1861 /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
1862 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
1863 /* .. reserved_SLEW_P = 0x6 */
1864 /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
1865 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
1866 /* .. reserved_SLEW_N = 0x1f */
1867 /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
1868 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
1869 /* .. reserved_GTL = 0x0 */
1870 /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
1871 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
1872 /* .. reserved_RTERM = 0x0 */
1873 /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
1874 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
1875 /* .. */
1876 EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
1877 /* .. reserved_DRIVE_P = 0x1c */
1878 /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
1879 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
1880 /* .. reserved_DRIVE_N = 0xc */
1881 /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
1882 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
1883 /* .. reserved_SLEW_P = 0x6 */
1884 /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
1885 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
1886 /* .. reserved_SLEW_N = 0x1f */
1887 /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
1888 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
1889 /* .. reserved_GTL = 0x0 */
1890 /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
1891 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
1892 /* .. reserved_RTERM = 0x0 */
1893 /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
1894 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
1895 /* .. */
1896 EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
1897 /* .. reserved_DRIVE_P = 0x1c */
1898 /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
1899 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
1900 /* .. reserved_DRIVE_N = 0xc */
1901 /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
1902 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
1903 /* .. reserved_SLEW_P = 0x6 */
1904 /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
1905 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
1906 /* .. reserved_SLEW_N = 0x1f */
1907 /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
1908 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
1909 /* .. reserved_GTL = 0x0 */
1910 /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
1911 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
1912 /* .. reserved_RTERM = 0x0 */
1913 /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
1914 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
1915 /* .. */
1916 EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
1917 /* .. VREF_INT_EN = 0x0 */
1918 /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
1919 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1920 /* .. VREF_SEL = 0x0 */
1921 /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
1922 /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
1923 /* .. VREF_EXT_EN = 0x3 */
1924 /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
1925 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
1926 /* .. reserved_VREF_PULLUP_EN = 0x0 */
1927 /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
1928 /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
1929 /* .. REFIO_EN = 0x1 */
1930 /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
1931 /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
1932 /* .. reserved_REFIO_TEST = 0x0 */
1933 /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
1934 /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
1935 /* .. reserved_REFIO_PULLUP_EN = 0x0 */
1936 /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
1937 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
1938 /* .. reserved_DRST_B_PULLUP_EN = 0x0 */
1939 /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
1940 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
1941 /* .. reserved_CKE_PULLUP_EN = 0x0 */
1942 /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
1943 /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
1944 /* .. */
1945 EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
1946 /* .. .. START: ASSERT RESET */
1947 /* .. .. RESET = 1 */
1948 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
1949 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1950 /* .. .. */
1951 EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
1952 /* .. .. FINISH: ASSERT RESET */
1953 /* .. .. START: DEASSERT RESET */
1954 /* .. .. RESET = 0 */
1955 /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
1956 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
1957 /* .. .. reserved_VRN_OUT = 0x1 */
1958 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
1959 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
1960 /* .. .. */
1961 EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
1962 /* .. .. FINISH: DEASSERT RESET */
1963 /* .. .. RESET = 0x1 */
1964 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
1965 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
1966 /* .. .. ENABLE = 0x1 */
1967 /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
1968 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
1969 /* .. .. reserved_VRP_TRI = 0x0 */
1970 /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
1971 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
1972 /* .. .. reserved_VRN_TRI = 0x0 */
1973 /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
1974 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
1975 /* .. .. reserved_VRP_OUT = 0x0 */
1976 /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
1977 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
1978 /* .. .. reserved_VRN_OUT = 0x1 */
1979 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
1980 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
1981 /* .. .. NREF_OPT1 = 0x0 */
1982 /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
1983 /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
1984 /* .. .. NREF_OPT2 = 0x0 */
1985 /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
1986 /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
1987 /* .. .. NREF_OPT4 = 0x1 */
1988 /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
1989 /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
1990 /* .. .. PREF_OPT1 = 0x0 */
1991 /* .. .. ==> 0XF8000B70[15:14] = 0x00000000U */
1992 /* .. .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
1993 /* .. .. PREF_OPT2 = 0x0 */
1994 /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
1995 /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
1996 /* .. .. UPDATE_CONTROL = 0x0 */
1997 /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
1998 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
1999 /* .. .. reserved_INIT_COMPLETE = 0x0 */
2000 /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
2001 /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
2002 /* .. .. reserved_TST_CLK = 0x0 */
2003 /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
2004 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
2005 /* .. .. reserved_TST_HLN = 0x0 */
2006 /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
2007 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
2008 /* .. .. reserved_TST_HLP = 0x0 */
2009 /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
2010 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
2011 /* .. .. reserved_TST_RST = 0x0 */
2012 /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
2013 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
2014 /* .. .. reserved_INT_DCI_EN = 0x0 */
2015 /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
2016 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
2017 /* .. .. */
2018 EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
2019 /* .. FINISH: DDRIOB SETTINGS */
2020 /* .. START: MIO PROGRAMMING */
2021 /* .. TRI_ENABLE = 0 */
2022 /* .. ==> 0XF8000700[0:0] = 0x00000000U */
2023 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2024 /* .. L0_SEL = 0 */
2025 /* .. ==> 0XF8000700[1:1] = 0x00000000U */
2026 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2027 /* .. L1_SEL = 0 */
2028 /* .. ==> 0XF8000700[2:2] = 0x00000000U */
2029 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2030 /* .. L2_SEL = 0 */
2031 /* .. ==> 0XF8000700[4:3] = 0x00000000U */
2032 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2033 /* .. L3_SEL = 0 */
2034 /* .. ==> 0XF8000700[7:5] = 0x00000000U */
2035 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2036 /* .. Speed = 0 */
2037 /* .. ==> 0XF8000700[8:8] = 0x00000000U */
2038 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2039 /* .. IO_Type = 3 */
2040 /* .. ==> 0XF8000700[11:9] = 0x00000003U */
2041 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2042 /* .. PULLUP = 1 */
2043 /* .. ==> 0XF8000700[12:12] = 0x00000001U */
2044 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2045 /* .. DisableRcvr = 0 */
2046 /* .. ==> 0XF8000700[13:13] = 0x00000000U */
2047 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2048 /* .. */
2049 EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
2050 /* .. TRI_ENABLE = 0 */
2051 /* .. ==> 0XF8000704[0:0] = 0x00000000U */
2052 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2053 /* .. L0_SEL = 1 */
2054 /* .. ==> 0XF8000704[1:1] = 0x00000001U */
2055 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2056 /* .. L1_SEL = 0 */
2057 /* .. ==> 0XF8000704[2:2] = 0x00000000U */
2058 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2059 /* .. L2_SEL = 0 */
2060 /* .. ==> 0XF8000704[4:3] = 0x00000000U */
2061 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2062 /* .. L3_SEL = 0 */
2063 /* .. ==> 0XF8000704[7:5] = 0x00000000U */
2064 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2065 /* .. Speed = 1 */
2066 /* .. ==> 0XF8000704[8:8] = 0x00000001U */
2067 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2068 /* .. IO_Type = 3 */
2069 /* .. ==> 0XF8000704[11:9] = 0x00000003U */
2070 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2071 /* .. PULLUP = 0 */
2072 /* .. ==> 0XF8000704[12:12] = 0x00000000U */
2073 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2074 /* .. DisableRcvr = 0 */
2075 /* .. ==> 0XF8000704[13:13] = 0x00000000U */
2076 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2077 /* .. */
2078 EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
2079 /* .. TRI_ENABLE = 0 */
2080 /* .. ==> 0XF8000708[0:0] = 0x00000000U */
2081 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2082 /* .. L0_SEL = 1 */
2083 /* .. ==> 0XF8000708[1:1] = 0x00000001U */
2084 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2085 /* .. L1_SEL = 0 */
2086 /* .. ==> 0XF8000708[2:2] = 0x00000000U */
2087 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2088 /* .. L2_SEL = 0 */
2089 /* .. ==> 0XF8000708[4:3] = 0x00000000U */
2090 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2091 /* .. L3_SEL = 0 */
2092 /* .. ==> 0XF8000708[7:5] = 0x00000000U */
2093 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2094 /* .. Speed = 1 */
2095 /* .. ==> 0XF8000708[8:8] = 0x00000001U */
2096 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2097 /* .. IO_Type = 3 */
2098 /* .. ==> 0XF8000708[11:9] = 0x00000003U */
2099 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2100 /* .. PULLUP = 0 */
2101 /* .. ==> 0XF8000708[12:12] = 0x00000000U */
2102 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2103 /* .. DisableRcvr = 0 */
2104 /* .. ==> 0XF8000708[13:13] = 0x00000000U */
2105 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2106 /* .. */
2107 EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
2108 /* .. TRI_ENABLE = 0 */
2109 /* .. ==> 0XF800070C[0:0] = 0x00000000U */
2110 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2111 /* .. L0_SEL = 1 */
2112 /* .. ==> 0XF800070C[1:1] = 0x00000001U */
2113 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2114 /* .. L1_SEL = 0 */
2115 /* .. ==> 0XF800070C[2:2] = 0x00000000U */
2116 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2117 /* .. L2_SEL = 0 */
2118 /* .. ==> 0XF800070C[4:3] = 0x00000000U */
2119 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2120 /* .. L3_SEL = 0 */
2121 /* .. ==> 0XF800070C[7:5] = 0x00000000U */
2122 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2123 /* .. Speed = 1 */
2124 /* .. ==> 0XF800070C[8:8] = 0x00000001U */
2125 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2126 /* .. IO_Type = 3 */
2127 /* .. ==> 0XF800070C[11:9] = 0x00000003U */
2128 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2129 /* .. PULLUP = 0 */
2130 /* .. ==> 0XF800070C[12:12] = 0x00000000U */
2131 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2132 /* .. DisableRcvr = 0 */
2133 /* .. ==> 0XF800070C[13:13] = 0x00000000U */
2134 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2135 /* .. */
2136 EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
2137 /* .. TRI_ENABLE = 0 */
2138 /* .. ==> 0XF8000710[0:0] = 0x00000000U */
2139 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2140 /* .. L0_SEL = 1 */
2141 /* .. ==> 0XF8000710[1:1] = 0x00000001U */
2142 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2143 /* .. L1_SEL = 0 */
2144 /* .. ==> 0XF8000710[2:2] = 0x00000000U */
2145 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2146 /* .. L2_SEL = 0 */
2147 /* .. ==> 0XF8000710[4:3] = 0x00000000U */
2148 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2149 /* .. L3_SEL = 0 */
2150 /* .. ==> 0XF8000710[7:5] = 0x00000000U */
2151 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2152 /* .. Speed = 1 */
2153 /* .. ==> 0XF8000710[8:8] = 0x00000001U */
2154 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2155 /* .. IO_Type = 3 */
2156 /* .. ==> 0XF8000710[11:9] = 0x00000003U */
2157 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2158 /* .. PULLUP = 0 */
2159 /* .. ==> 0XF8000710[12:12] = 0x00000000U */
2160 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2161 /* .. DisableRcvr = 0 */
2162 /* .. ==> 0XF8000710[13:13] = 0x00000000U */
2163 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2164 /* .. */
2165 EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
2166 /* .. TRI_ENABLE = 0 */
2167 /* .. ==> 0XF8000714[0:0] = 0x00000000U */
2168 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2169 /* .. L0_SEL = 1 */
2170 /* .. ==> 0XF8000714[1:1] = 0x00000001U */
2171 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2172 /* .. L1_SEL = 0 */
2173 /* .. ==> 0XF8000714[2:2] = 0x00000000U */
2174 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2175 /* .. L2_SEL = 0 */
2176 /* .. ==> 0XF8000714[4:3] = 0x00000000U */
2177 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2178 /* .. L3_SEL = 0 */
2179 /* .. ==> 0XF8000714[7:5] = 0x00000000U */
2180 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2181 /* .. Speed = 1 */
2182 /* .. ==> 0XF8000714[8:8] = 0x00000001U */
2183 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2184 /* .. IO_Type = 3 */
2185 /* .. ==> 0XF8000714[11:9] = 0x00000003U */
2186 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2187 /* .. PULLUP = 0 */
2188 /* .. ==> 0XF8000714[12:12] = 0x00000000U */
2189 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2190 /* .. DisableRcvr = 0 */
2191 /* .. ==> 0XF8000714[13:13] = 0x00000000U */
2192 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2193 /* .. */
2194 EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
2195 /* .. TRI_ENABLE = 0 */
2196 /* .. ==> 0XF8000718[0:0] = 0x00000000U */
2197 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2198 /* .. L0_SEL = 1 */
2199 /* .. ==> 0XF8000718[1:1] = 0x00000001U */
2200 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2201 /* .. L1_SEL = 0 */
2202 /* .. ==> 0XF8000718[2:2] = 0x00000000U */
2203 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2204 /* .. L2_SEL = 0 */
2205 /* .. ==> 0XF8000718[4:3] = 0x00000000U */
2206 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2207 /* .. L3_SEL = 0 */
2208 /* .. ==> 0XF8000718[7:5] = 0x00000000U */
2209 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2210 /* .. Speed = 1 */
2211 /* .. ==> 0XF8000718[8:8] = 0x00000001U */
2212 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2213 /* .. IO_Type = 3 */
2214 /* .. ==> 0XF8000718[11:9] = 0x00000003U */
2215 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2216 /* .. PULLUP = 0 */
2217 /* .. ==> 0XF8000718[12:12] = 0x00000000U */
2218 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2219 /* .. DisableRcvr = 0 */
2220 /* .. ==> 0XF8000718[13:13] = 0x00000000U */
2221 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2222 /* .. */
2223 EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
2224 /* .. TRI_ENABLE = 0 */
2225 /* .. ==> 0XF800071C[0:0] = 0x00000000U */
2226 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2227 /* .. L0_SEL = 0 */
2228 /* .. ==> 0XF800071C[1:1] = 0x00000000U */
2229 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2230 /* .. L1_SEL = 0 */
2231 /* .. ==> 0XF800071C[2:2] = 0x00000000U */
2232 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2233 /* .. L2_SEL = 0 */
2234 /* .. ==> 0XF800071C[4:3] = 0x00000000U */
2235 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2236 /* .. L3_SEL = 0 */
2237 /* .. ==> 0XF800071C[7:5] = 0x00000000U */
2238 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2239 /* .. Speed = 0 */
2240 /* .. ==> 0XF800071C[8:8] = 0x00000000U */
2241 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2242 /* .. IO_Type = 3 */
2243 /* .. ==> 0XF800071C[11:9] = 0x00000003U */
2244 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2245 /* .. PULLUP = 0 */
2246 /* .. ==> 0XF800071C[12:12] = 0x00000000U */
2247 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2248 /* .. DisableRcvr = 0 */
2249 /* .. ==> 0XF800071C[13:13] = 0x00000000U */
2250 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2251 /* .. */
2252 EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
2253 /* .. TRI_ENABLE = 0 */
2254 /* .. ==> 0XF8000720[0:0] = 0x00000000U */
2255 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2256 /* .. L0_SEL = 1 */
2257 /* .. ==> 0XF8000720[1:1] = 0x00000001U */
2258 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2259 /* .. L1_SEL = 0 */
2260 /* .. ==> 0XF8000720[2:2] = 0x00000000U */
2261 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2262 /* .. L2_SEL = 0 */
2263 /* .. ==> 0XF8000720[4:3] = 0x00000000U */
2264 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2265 /* .. L3_SEL = 0 */
2266 /* .. ==> 0XF8000720[7:5] = 0x00000000U */
2267 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2268 /* .. Speed = 1 */
2269 /* .. ==> 0XF8000720[8:8] = 0x00000001U */
2270 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2271 /* .. IO_Type = 3 */
2272 /* .. ==> 0XF8000720[11:9] = 0x00000003U */
2273 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2274 /* .. PULLUP = 0 */
2275 /* .. ==> 0XF8000720[12:12] = 0x00000000U */
2276 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2277 /* .. DisableRcvr = 0 */
2278 /* .. ==> 0XF8000720[13:13] = 0x00000000U */
2279 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2280 /* .. */
2281 EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
2282 /* .. TRI_ENABLE = 0 */
2283 /* .. ==> 0XF8000724[0:0] = 0x00000000U */
2284 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2285 /* .. L0_SEL = 0 */
2286 /* .. ==> 0XF8000724[1:1] = 0x00000000U */
2287 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2288 /* .. L1_SEL = 0 */
2289 /* .. ==> 0XF8000724[2:2] = 0x00000000U */
2290 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2291 /* .. L2_SEL = 0 */
2292 /* .. ==> 0XF8000724[4:3] = 0x00000000U */
2293 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2294 /* .. L3_SEL = 0 */
2295 /* .. ==> 0XF8000724[7:5] = 0x00000000U */
2296 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2297 /* .. Speed = 0 */
2298 /* .. ==> 0XF8000724[8:8] = 0x00000000U */
2299 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2300 /* .. IO_Type = 3 */
2301 /* .. ==> 0XF8000724[11:9] = 0x00000003U */
2302 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2303 /* .. PULLUP = 1 */
2304 /* .. ==> 0XF8000724[12:12] = 0x00000001U */
2305 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2306 /* .. DisableRcvr = 0 */
2307 /* .. ==> 0XF8000724[13:13] = 0x00000000U */
2308 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2309 /* .. */
2310 EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
2311 /* .. TRI_ENABLE = 0 */
2312 /* .. ==> 0XF8000728[0:0] = 0x00000000U */
2313 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2314 /* .. L0_SEL = 0 */
2315 /* .. ==> 0XF8000728[1:1] = 0x00000000U */
2316 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2317 /* .. L1_SEL = 0 */
2318 /* .. ==> 0XF8000728[2:2] = 0x00000000U */
2319 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2320 /* .. L2_SEL = 0 */
2321 /* .. ==> 0XF8000728[4:3] = 0x00000000U */
2322 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2323 /* .. L3_SEL = 0 */
2324 /* .. ==> 0XF8000728[7:5] = 0x00000000U */
2325 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2326 /* .. Speed = 0 */
2327 /* .. ==> 0XF8000728[8:8] = 0x00000000U */
2328 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2329 /* .. IO_Type = 3 */
2330 /* .. ==> 0XF8000728[11:9] = 0x00000003U */
2331 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2332 /* .. PULLUP = 1 */
2333 /* .. ==> 0XF8000728[12:12] = 0x00000001U */
2334 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2335 /* .. DisableRcvr = 0 */
2336 /* .. ==> 0XF8000728[13:13] = 0x00000000U */
2337 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2338 /* .. */
2339 EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
2340 /* .. TRI_ENABLE = 0 */
2341 /* .. ==> 0XF800072C[0:0] = 0x00000000U */
2342 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2343 /* .. L0_SEL = 0 */
2344 /* .. ==> 0XF800072C[1:1] = 0x00000000U */
2345 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2346 /* .. L1_SEL = 0 */
2347 /* .. ==> 0XF800072C[2:2] = 0x00000000U */
2348 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2349 /* .. L2_SEL = 0 */
2350 /* .. ==> 0XF800072C[4:3] = 0x00000000U */
2351 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2352 /* .. L3_SEL = 0 */
2353 /* .. ==> 0XF800072C[7:5] = 0x00000000U */
2354 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2355 /* .. Speed = 0 */
2356 /* .. ==> 0XF800072C[8:8] = 0x00000000U */
2357 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2358 /* .. IO_Type = 3 */
2359 /* .. ==> 0XF800072C[11:9] = 0x00000003U */
2360 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2361 /* .. PULLUP = 1 */
2362 /* .. ==> 0XF800072C[12:12] = 0x00000001U */
2363 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2364 /* .. DisableRcvr = 0 */
2365 /* .. ==> 0XF800072C[13:13] = 0x00000000U */
2366 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2367 /* .. */
2368 EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
2369 /* .. TRI_ENABLE = 0 */
2370 /* .. ==> 0XF8000730[0:0] = 0x00000000U */
2371 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2372 /* .. L0_SEL = 0 */
2373 /* .. ==> 0XF8000730[1:1] = 0x00000000U */
2374 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2375 /* .. L1_SEL = 0 */
2376 /* .. ==> 0XF8000730[2:2] = 0x00000000U */
2377 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2378 /* .. L2_SEL = 0 */
2379 /* .. ==> 0XF8000730[4:3] = 0x00000000U */
2380 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2381 /* .. L3_SEL = 0 */
2382 /* .. ==> 0XF8000730[7:5] = 0x00000000U */
2383 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2384 /* .. Speed = 0 */
2385 /* .. ==> 0XF8000730[8:8] = 0x00000000U */
2386 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2387 /* .. IO_Type = 3 */
2388 /* .. ==> 0XF8000730[11:9] = 0x00000003U */
2389 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2390 /* .. PULLUP = 1 */
2391 /* .. ==> 0XF8000730[12:12] = 0x00000001U */
2392 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2393 /* .. DisableRcvr = 0 */
2394 /* .. ==> 0XF8000730[13:13] = 0x00000000U */
2395 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2396 /* .. */
2397 EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
2398 /* .. TRI_ENABLE = 0 */
2399 /* .. ==> 0XF8000734[0:0] = 0x00000000U */
2400 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2401 /* .. L0_SEL = 0 */
2402 /* .. ==> 0XF8000734[1:1] = 0x00000000U */
2403 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2404 /* .. L1_SEL = 0 */
2405 /* .. ==> 0XF8000734[2:2] = 0x00000000U */
2406 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2407 /* .. L2_SEL = 0 */
2408 /* .. ==> 0XF8000734[4:3] = 0x00000000U */
2409 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2410 /* .. L3_SEL = 0 */
2411 /* .. ==> 0XF8000734[7:5] = 0x00000000U */
2412 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2413 /* .. Speed = 0 */
2414 /* .. ==> 0XF8000734[8:8] = 0x00000000U */
2415 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2416 /* .. IO_Type = 3 */
2417 /* .. ==> 0XF8000734[11:9] = 0x00000003U */
2418 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2419 /* .. PULLUP = 1 */
2420 /* .. ==> 0XF8000734[12:12] = 0x00000001U */
2421 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2422 /* .. DisableRcvr = 0 */
2423 /* .. ==> 0XF8000734[13:13] = 0x00000000U */
2424 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2425 /* .. */
2426 EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
2427 /* .. TRI_ENABLE = 0 */
2428 /* .. ==> 0XF8000738[0:0] = 0x00000000U */
2429 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2430 /* .. L0_SEL = 0 */
2431 /* .. ==> 0XF8000738[1:1] = 0x00000000U */
2432 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2433 /* .. L1_SEL = 0 */
2434 /* .. ==> 0XF8000738[2:2] = 0x00000000U */
2435 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2436 /* .. L2_SEL = 0 */
2437 /* .. ==> 0XF8000738[4:3] = 0x00000000U */
2438 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2439 /* .. L3_SEL = 0 */
2440 /* .. ==> 0XF8000738[7:5] = 0x00000000U */
2441 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2442 /* .. Speed = 0 */
2443 /* .. ==> 0XF8000738[8:8] = 0x00000000U */
2444 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2445 /* .. IO_Type = 3 */
2446 /* .. ==> 0XF8000738[11:9] = 0x00000003U */
2447 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2448 /* .. PULLUP = 1 */
2449 /* .. ==> 0XF8000738[12:12] = 0x00000001U */
2450 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2451 /* .. DisableRcvr = 0 */
2452 /* .. ==> 0XF8000738[13:13] = 0x00000000U */
2453 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2454 /* .. */
2455 EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
2456 /* .. TRI_ENABLE = 0 */
2457 /* .. ==> 0XF800073C[0:0] = 0x00000000U */
2458 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2459 /* .. L0_SEL = 0 */
2460 /* .. ==> 0XF800073C[1:1] = 0x00000000U */
2461 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2462 /* .. L1_SEL = 0 */
2463 /* .. ==> 0XF800073C[2:2] = 0x00000000U */
2464 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2465 /* .. L2_SEL = 0 */
2466 /* .. ==> 0XF800073C[4:3] = 0x00000000U */
2467 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2468 /* .. L3_SEL = 0 */
2469 /* .. ==> 0XF800073C[7:5] = 0x00000000U */
2470 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2471 /* .. Speed = 0 */
2472 /* .. ==> 0XF800073C[8:8] = 0x00000000U */
2473 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
2474 /* .. IO_Type = 3 */
2475 /* .. ==> 0XF800073C[11:9] = 0x00000003U */
2476 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
2477 /* .. PULLUP = 1 */
2478 /* .. ==> 0XF800073C[12:12] = 0x00000001U */
2479 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
2480 /* .. DisableRcvr = 0 */
2481 /* .. ==> 0XF800073C[13:13] = 0x00000000U */
2482 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2483 /* .. */
2484 EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
2485 /* .. TRI_ENABLE = 0 */
2486 /* .. ==> 0XF8000740[0:0] = 0x00000000U */
2487 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2488 /* .. L0_SEL = 1 */
2489 /* .. ==> 0XF8000740[1:1] = 0x00000001U */
2490 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2491 /* .. L1_SEL = 0 */
2492 /* .. ==> 0XF8000740[2:2] = 0x00000000U */
2493 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2494 /* .. L2_SEL = 0 */
2495 /* .. ==> 0XF8000740[4:3] = 0x00000000U */
2496 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2497 /* .. L3_SEL = 0 */
2498 /* .. ==> 0XF8000740[7:5] = 0x00000000U */
2499 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2500 /* .. Speed = 1 */
2501 /* .. ==> 0XF8000740[8:8] = 0x00000001U */
2502 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2503 /* .. IO_Type = 4 */
2504 /* .. ==> 0XF8000740[11:9] = 0x00000004U */
2505 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2506 /* .. PULLUP = 0 */
2507 /* .. ==> 0XF8000740[12:12] = 0x00000000U */
2508 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2509 /* .. DisableRcvr = 1 */
2510 /* .. ==> 0XF8000740[13:13] = 0x00000001U */
2511 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2512 /* .. */
2513 EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
2514 /* .. TRI_ENABLE = 0 */
2515 /* .. ==> 0XF8000744[0:0] = 0x00000000U */
2516 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2517 /* .. L0_SEL = 1 */
2518 /* .. ==> 0XF8000744[1:1] = 0x00000001U */
2519 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2520 /* .. L1_SEL = 0 */
2521 /* .. ==> 0XF8000744[2:2] = 0x00000000U */
2522 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2523 /* .. L2_SEL = 0 */
2524 /* .. ==> 0XF8000744[4:3] = 0x00000000U */
2525 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2526 /* .. L3_SEL = 0 */
2527 /* .. ==> 0XF8000744[7:5] = 0x00000000U */
2528 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2529 /* .. Speed = 1 */
2530 /* .. ==> 0XF8000744[8:8] = 0x00000001U */
2531 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2532 /* .. IO_Type = 4 */
2533 /* .. ==> 0XF8000744[11:9] = 0x00000004U */
2534 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2535 /* .. PULLUP = 0 */
2536 /* .. ==> 0XF8000744[12:12] = 0x00000000U */
2537 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2538 /* .. DisableRcvr = 1 */
2539 /* .. ==> 0XF8000744[13:13] = 0x00000001U */
2540 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2541 /* .. */
2542 EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
2543 /* .. TRI_ENABLE = 0 */
2544 /* .. ==> 0XF8000748[0:0] = 0x00000000U */
2545 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2546 /* .. L0_SEL = 1 */
2547 /* .. ==> 0XF8000748[1:1] = 0x00000001U */
2548 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2549 /* .. L1_SEL = 0 */
2550 /* .. ==> 0XF8000748[2:2] = 0x00000000U */
2551 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2552 /* .. L2_SEL = 0 */
2553 /* .. ==> 0XF8000748[4:3] = 0x00000000U */
2554 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2555 /* .. L3_SEL = 0 */
2556 /* .. ==> 0XF8000748[7:5] = 0x00000000U */
2557 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2558 /* .. Speed = 1 */
2559 /* .. ==> 0XF8000748[8:8] = 0x00000001U */
2560 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2561 /* .. IO_Type = 4 */
2562 /* .. ==> 0XF8000748[11:9] = 0x00000004U */
2563 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2564 /* .. PULLUP = 0 */
2565 /* .. ==> 0XF8000748[12:12] = 0x00000000U */
2566 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2567 /* .. DisableRcvr = 1 */
2568 /* .. ==> 0XF8000748[13:13] = 0x00000001U */
2569 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2570 /* .. */
2571 EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
2572 /* .. TRI_ENABLE = 0 */
2573 /* .. ==> 0XF800074C[0:0] = 0x00000000U */
2574 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2575 /* .. L0_SEL = 1 */
2576 /* .. ==> 0XF800074C[1:1] = 0x00000001U */
2577 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2578 /* .. L1_SEL = 0 */
2579 /* .. ==> 0XF800074C[2:2] = 0x00000000U */
2580 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2581 /* .. L2_SEL = 0 */
2582 /* .. ==> 0XF800074C[4:3] = 0x00000000U */
2583 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2584 /* .. L3_SEL = 0 */
2585 /* .. ==> 0XF800074C[7:5] = 0x00000000U */
2586 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2587 /* .. Speed = 1 */
2588 /* .. ==> 0XF800074C[8:8] = 0x00000001U */
2589 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2590 /* .. IO_Type = 4 */
2591 /* .. ==> 0XF800074C[11:9] = 0x00000004U */
2592 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2593 /* .. PULLUP = 0 */
2594 /* .. ==> 0XF800074C[12:12] = 0x00000000U */
2595 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2596 /* .. DisableRcvr = 1 */
2597 /* .. ==> 0XF800074C[13:13] = 0x00000001U */
2598 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2599 /* .. */
2600 EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
2601 /* .. TRI_ENABLE = 0 */
2602 /* .. ==> 0XF8000750[0:0] = 0x00000000U */
2603 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2604 /* .. L0_SEL = 1 */
2605 /* .. ==> 0XF8000750[1:1] = 0x00000001U */
2606 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2607 /* .. L1_SEL = 0 */
2608 /* .. ==> 0XF8000750[2:2] = 0x00000000U */
2609 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2610 /* .. L2_SEL = 0 */
2611 /* .. ==> 0XF8000750[4:3] = 0x00000000U */
2612 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2613 /* .. L3_SEL = 0 */
2614 /* .. ==> 0XF8000750[7:5] = 0x00000000U */
2615 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2616 /* .. Speed = 1 */
2617 /* .. ==> 0XF8000750[8:8] = 0x00000001U */
2618 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2619 /* .. IO_Type = 4 */
2620 /* .. ==> 0XF8000750[11:9] = 0x00000004U */
2621 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2622 /* .. PULLUP = 0 */
2623 /* .. ==> 0XF8000750[12:12] = 0x00000000U */
2624 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2625 /* .. DisableRcvr = 1 */
2626 /* .. ==> 0XF8000750[13:13] = 0x00000001U */
2627 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2628 /* .. */
2629 EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
2630 /* .. TRI_ENABLE = 0 */
2631 /* .. ==> 0XF8000754[0:0] = 0x00000000U */
2632 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2633 /* .. L0_SEL = 1 */
2634 /* .. ==> 0XF8000754[1:1] = 0x00000001U */
2635 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2636 /* .. L1_SEL = 0 */
2637 /* .. ==> 0XF8000754[2:2] = 0x00000000U */
2638 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2639 /* .. L2_SEL = 0 */
2640 /* .. ==> 0XF8000754[4:3] = 0x00000000U */
2641 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2642 /* .. L3_SEL = 0 */
2643 /* .. ==> 0XF8000754[7:5] = 0x00000000U */
2644 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2645 /* .. Speed = 1 */
2646 /* .. ==> 0XF8000754[8:8] = 0x00000001U */
2647 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2648 /* .. IO_Type = 4 */
2649 /* .. ==> 0XF8000754[11:9] = 0x00000004U */
2650 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2651 /* .. PULLUP = 0 */
2652 /* .. ==> 0XF8000754[12:12] = 0x00000000U */
2653 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2654 /* .. DisableRcvr = 1 */
2655 /* .. ==> 0XF8000754[13:13] = 0x00000001U */
2656 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
2657 /* .. */
2658 EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
2659 /* .. TRI_ENABLE = 1 */
2660 /* .. ==> 0XF8000758[0:0] = 0x00000001U */
2661 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2662 /* .. L0_SEL = 1 */
2663 /* .. ==> 0XF8000758[1:1] = 0x00000001U */
2664 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2665 /* .. L1_SEL = 0 */
2666 /* .. ==> 0XF8000758[2:2] = 0x00000000U */
2667 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2668 /* .. L2_SEL = 0 */
2669 /* .. ==> 0XF8000758[4:3] = 0x00000000U */
2670 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2671 /* .. L3_SEL = 0 */
2672 /* .. ==> 0XF8000758[7:5] = 0x00000000U */
2673 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2674 /* .. Speed = 1 */
2675 /* .. ==> 0XF8000758[8:8] = 0x00000001U */
2676 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2677 /* .. IO_Type = 4 */
2678 /* .. ==> 0XF8000758[11:9] = 0x00000004U */
2679 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2680 /* .. PULLUP = 0 */
2681 /* .. ==> 0XF8000758[12:12] = 0x00000000U */
2682 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2683 /* .. DisableRcvr = 0 */
2684 /* .. ==> 0XF8000758[13:13] = 0x00000000U */
2685 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2686 /* .. */
2687 EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
2688 /* .. TRI_ENABLE = 1 */
2689 /* .. ==> 0XF800075C[0:0] = 0x00000001U */
2690 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2691 /* .. L0_SEL = 1 */
2692 /* .. ==> 0XF800075C[1:1] = 0x00000001U */
2693 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2694 /* .. L1_SEL = 0 */
2695 /* .. ==> 0XF800075C[2:2] = 0x00000000U */
2696 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2697 /* .. L2_SEL = 0 */
2698 /* .. ==> 0XF800075C[4:3] = 0x00000000U */
2699 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2700 /* .. L3_SEL = 0 */
2701 /* .. ==> 0XF800075C[7:5] = 0x00000000U */
2702 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2703 /* .. Speed = 1 */
2704 /* .. ==> 0XF800075C[8:8] = 0x00000001U */
2705 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2706 /* .. IO_Type = 4 */
2707 /* .. ==> 0XF800075C[11:9] = 0x00000004U */
2708 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2709 /* .. PULLUP = 0 */
2710 /* .. ==> 0XF800075C[12:12] = 0x00000000U */
2711 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2712 /* .. DisableRcvr = 0 */
2713 /* .. ==> 0XF800075C[13:13] = 0x00000000U */
2714 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2715 /* .. */
2716 EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
2717 /* .. TRI_ENABLE = 1 */
2718 /* .. ==> 0XF8000760[0:0] = 0x00000001U */
2719 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2720 /* .. L0_SEL = 1 */
2721 /* .. ==> 0XF8000760[1:1] = 0x00000001U */
2722 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2723 /* .. L1_SEL = 0 */
2724 /* .. ==> 0XF8000760[2:2] = 0x00000000U */
2725 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2726 /* .. L2_SEL = 0 */
2727 /* .. ==> 0XF8000760[4:3] = 0x00000000U */
2728 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2729 /* .. L3_SEL = 0 */
2730 /* .. ==> 0XF8000760[7:5] = 0x00000000U */
2731 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2732 /* .. Speed = 1 */
2733 /* .. ==> 0XF8000760[8:8] = 0x00000001U */
2734 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2735 /* .. IO_Type = 4 */
2736 /* .. ==> 0XF8000760[11:9] = 0x00000004U */
2737 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2738 /* .. PULLUP = 0 */
2739 /* .. ==> 0XF8000760[12:12] = 0x00000000U */
2740 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2741 /* .. DisableRcvr = 0 */
2742 /* .. ==> 0XF8000760[13:13] = 0x00000000U */
2743 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2744 /* .. */
2745 EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
2746 /* .. TRI_ENABLE = 1 */
2747 /* .. ==> 0XF8000764[0:0] = 0x00000001U */
2748 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2749 /* .. L0_SEL = 1 */
2750 /* .. ==> 0XF8000764[1:1] = 0x00000001U */
2751 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2752 /* .. L1_SEL = 0 */
2753 /* .. ==> 0XF8000764[2:2] = 0x00000000U */
2754 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2755 /* .. L2_SEL = 0 */
2756 /* .. ==> 0XF8000764[4:3] = 0x00000000U */
2757 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2758 /* .. L3_SEL = 0 */
2759 /* .. ==> 0XF8000764[7:5] = 0x00000000U */
2760 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2761 /* .. Speed = 1 */
2762 /* .. ==> 0XF8000764[8:8] = 0x00000001U */
2763 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2764 /* .. IO_Type = 4 */
2765 /* .. ==> 0XF8000764[11:9] = 0x00000004U */
2766 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2767 /* .. PULLUP = 0 */
2768 /* .. ==> 0XF8000764[12:12] = 0x00000000U */
2769 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2770 /* .. DisableRcvr = 0 */
2771 /* .. ==> 0XF8000764[13:13] = 0x00000000U */
2772 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2773 /* .. */
2774 EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
2775 /* .. TRI_ENABLE = 1 */
2776 /* .. ==> 0XF8000768[0:0] = 0x00000001U */
2777 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2778 /* .. L0_SEL = 1 */
2779 /* .. ==> 0XF8000768[1:1] = 0x00000001U */
2780 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2781 /* .. L1_SEL = 0 */
2782 /* .. ==> 0XF8000768[2:2] = 0x00000000U */
2783 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2784 /* .. L2_SEL = 0 */
2785 /* .. ==> 0XF8000768[4:3] = 0x00000000U */
2786 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2787 /* .. L3_SEL = 0 */
2788 /* .. ==> 0XF8000768[7:5] = 0x00000000U */
2789 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2790 /* .. Speed = 1 */
2791 /* .. ==> 0XF8000768[8:8] = 0x00000001U */
2792 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2793 /* .. IO_Type = 4 */
2794 /* .. ==> 0XF8000768[11:9] = 0x00000004U */
2795 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2796 /* .. PULLUP = 0 */
2797 /* .. ==> 0XF8000768[12:12] = 0x00000000U */
2798 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2799 /* .. DisableRcvr = 0 */
2800 /* .. ==> 0XF8000768[13:13] = 0x00000000U */
2801 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2802 /* .. */
2803 EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
2804 /* .. TRI_ENABLE = 1 */
2805 /* .. ==> 0XF800076C[0:0] = 0x00000001U */
2806 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2807 /* .. L0_SEL = 1 */
2808 /* .. ==> 0XF800076C[1:1] = 0x00000001U */
2809 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
2810 /* .. L1_SEL = 0 */
2811 /* .. ==> 0XF800076C[2:2] = 0x00000000U */
2812 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
2813 /* .. L2_SEL = 0 */
2814 /* .. ==> 0XF800076C[4:3] = 0x00000000U */
2815 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2816 /* .. L3_SEL = 0 */
2817 /* .. ==> 0XF800076C[7:5] = 0x00000000U */
2818 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2819 /* .. Speed = 1 */
2820 /* .. ==> 0XF800076C[8:8] = 0x00000001U */
2821 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2822 /* .. IO_Type = 4 */
2823 /* .. ==> 0XF800076C[11:9] = 0x00000004U */
2824 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
2825 /* .. PULLUP = 0 */
2826 /* .. ==> 0XF800076C[12:12] = 0x00000000U */
2827 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2828 /* .. DisableRcvr = 0 */
2829 /* .. ==> 0XF800076C[13:13] = 0x00000000U */
2830 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2831 /* .. */
2832 EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
2833 /* .. TRI_ENABLE = 0 */
2834 /* .. ==> 0XF8000770[0:0] = 0x00000000U */
2835 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2836 /* .. L0_SEL = 0 */
2837 /* .. ==> 0XF8000770[1:1] = 0x00000000U */
2838 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2839 /* .. L1_SEL = 1 */
2840 /* .. ==> 0XF8000770[2:2] = 0x00000001U */
2841 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2842 /* .. L2_SEL = 0 */
2843 /* .. ==> 0XF8000770[4:3] = 0x00000000U */
2844 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2845 /* .. L3_SEL = 0 */
2846 /* .. ==> 0XF8000770[7:5] = 0x00000000U */
2847 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2848 /* .. Speed = 1 */
2849 /* .. ==> 0XF8000770[8:8] = 0x00000001U */
2850 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2851 /* .. IO_Type = 1 */
2852 /* .. ==> 0XF8000770[11:9] = 0x00000001U */
2853 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
2854 /* .. PULLUP = 0 */
2855 /* .. ==> 0XF8000770[12:12] = 0x00000000U */
2856 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2857 /* .. DisableRcvr = 0 */
2858 /* .. ==> 0XF8000770[13:13] = 0x00000000U */
2859 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2860 /* .. */
2861 EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
2862 /* .. TRI_ENABLE = 1 */
2863 /* .. ==> 0XF8000774[0:0] = 0x00000001U */
2864 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2865 /* .. L0_SEL = 0 */
2866 /* .. ==> 0XF8000774[1:1] = 0x00000000U */
2867 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2868 /* .. L1_SEL = 1 */
2869 /* .. ==> 0XF8000774[2:2] = 0x00000001U */
2870 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2871 /* .. L2_SEL = 0 */
2872 /* .. ==> 0XF8000774[4:3] = 0x00000000U */
2873 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2874 /* .. L3_SEL = 0 */
2875 /* .. ==> 0XF8000774[7:5] = 0x00000000U */
2876 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2877 /* .. Speed = 1 */
2878 /* .. ==> 0XF8000774[8:8] = 0x00000001U */
2879 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2880 /* .. IO_Type = 1 */
2881 /* .. ==> 0XF8000774[11:9] = 0x00000001U */
2882 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
2883 /* .. PULLUP = 0 */
2884 /* .. ==> 0XF8000774[12:12] = 0x00000000U */
2885 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2886 /* .. DisableRcvr = 0 */
2887 /* .. ==> 0XF8000774[13:13] = 0x00000000U */
2888 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2889 /* .. */
2890 EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
2891 /* .. TRI_ENABLE = 0 */
2892 /* .. ==> 0XF8000778[0:0] = 0x00000000U */
2893 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2894 /* .. L0_SEL = 0 */
2895 /* .. ==> 0XF8000778[1:1] = 0x00000000U */
2896 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2897 /* .. L1_SEL = 1 */
2898 /* .. ==> 0XF8000778[2:2] = 0x00000001U */
2899 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2900 /* .. L2_SEL = 0 */
2901 /* .. ==> 0XF8000778[4:3] = 0x00000000U */
2902 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2903 /* .. L3_SEL = 0 */
2904 /* .. ==> 0XF8000778[7:5] = 0x00000000U */
2905 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2906 /* .. Speed = 1 */
2907 /* .. ==> 0XF8000778[8:8] = 0x00000001U */
2908 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2909 /* .. IO_Type = 1 */
2910 /* .. ==> 0XF8000778[11:9] = 0x00000001U */
2911 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
2912 /* .. PULLUP = 0 */
2913 /* .. ==> 0XF8000778[12:12] = 0x00000000U */
2914 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2915 /* .. DisableRcvr = 0 */
2916 /* .. ==> 0XF8000778[13:13] = 0x00000000U */
2917 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2918 /* .. */
2919 EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
2920 /* .. TRI_ENABLE = 1 */
2921 /* .. ==> 0XF800077C[0:0] = 0x00000001U */
2922 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
2923 /* .. L0_SEL = 0 */
2924 /* .. ==> 0XF800077C[1:1] = 0x00000000U */
2925 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2926 /* .. L1_SEL = 1 */
2927 /* .. ==> 0XF800077C[2:2] = 0x00000001U */
2928 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2929 /* .. L2_SEL = 0 */
2930 /* .. ==> 0XF800077C[4:3] = 0x00000000U */
2931 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2932 /* .. L3_SEL = 0 */
2933 /* .. ==> 0XF800077C[7:5] = 0x00000000U */
2934 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2935 /* .. Speed = 1 */
2936 /* .. ==> 0XF800077C[8:8] = 0x00000001U */
2937 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2938 /* .. IO_Type = 1 */
2939 /* .. ==> 0XF800077C[11:9] = 0x00000001U */
2940 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
2941 /* .. PULLUP = 0 */
2942 /* .. ==> 0XF800077C[12:12] = 0x00000000U */
2943 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2944 /* .. DisableRcvr = 0 */
2945 /* .. ==> 0XF800077C[13:13] = 0x00000000U */
2946 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2947 /* .. */
2948 EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
2949 /* .. TRI_ENABLE = 0 */
2950 /* .. ==> 0XF8000780[0:0] = 0x00000000U */
2951 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2952 /* .. L0_SEL = 0 */
2953 /* .. ==> 0XF8000780[1:1] = 0x00000000U */
2954 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2955 /* .. L1_SEL = 1 */
2956 /* .. ==> 0XF8000780[2:2] = 0x00000001U */
2957 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2958 /* .. L2_SEL = 0 */
2959 /* .. ==> 0XF8000780[4:3] = 0x00000000U */
2960 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2961 /* .. L3_SEL = 0 */
2962 /* .. ==> 0XF8000780[7:5] = 0x00000000U */
2963 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2964 /* .. Speed = 1 */
2965 /* .. ==> 0XF8000780[8:8] = 0x00000001U */
2966 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2967 /* .. IO_Type = 1 */
2968 /* .. ==> 0XF8000780[11:9] = 0x00000001U */
2969 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
2970 /* .. PULLUP = 0 */
2971 /* .. ==> 0XF8000780[12:12] = 0x00000000U */
2972 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
2973 /* .. DisableRcvr = 0 */
2974 /* .. ==> 0XF8000780[13:13] = 0x00000000U */
2975 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
2976 /* .. */
2977 EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
2978 /* .. TRI_ENABLE = 0 */
2979 /* .. ==> 0XF8000784[0:0] = 0x00000000U */
2980 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
2981 /* .. L0_SEL = 0 */
2982 /* .. ==> 0XF8000784[1:1] = 0x00000000U */
2983 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
2984 /* .. L1_SEL = 1 */
2985 /* .. ==> 0XF8000784[2:2] = 0x00000001U */
2986 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
2987 /* .. L2_SEL = 0 */
2988 /* .. ==> 0XF8000784[4:3] = 0x00000000U */
2989 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
2990 /* .. L3_SEL = 0 */
2991 /* .. ==> 0XF8000784[7:5] = 0x00000000U */
2992 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
2993 /* .. Speed = 1 */
2994 /* .. ==> 0XF8000784[8:8] = 0x00000001U */
2995 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
2996 /* .. IO_Type = 1 */
2997 /* .. ==> 0XF8000784[11:9] = 0x00000001U */
2998 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
2999 /* .. PULLUP = 0 */
3000 /* .. ==> 0XF8000784[12:12] = 0x00000000U */
3001 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3002 /* .. DisableRcvr = 0 */
3003 /* .. ==> 0XF8000784[13:13] = 0x00000000U */
3004 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3005 /* .. */
3006 EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
3007 /* .. TRI_ENABLE = 0 */
3008 /* .. ==> 0XF8000788[0:0] = 0x00000000U */
3009 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3010 /* .. L0_SEL = 0 */
3011 /* .. ==> 0XF8000788[1:1] = 0x00000000U */
3012 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3013 /* .. L1_SEL = 1 */
3014 /* .. ==> 0XF8000788[2:2] = 0x00000001U */
3015 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3016 /* .. L2_SEL = 0 */
3017 /* .. ==> 0XF8000788[4:3] = 0x00000000U */
3018 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3019 /* .. L3_SEL = 0 */
3020 /* .. ==> 0XF8000788[7:5] = 0x00000000U */
3021 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3022 /* .. Speed = 1 */
3023 /* .. ==> 0XF8000788[8:8] = 0x00000001U */
3024 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3025 /* .. IO_Type = 1 */
3026 /* .. ==> 0XF8000788[11:9] = 0x00000001U */
3027 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3028 /* .. PULLUP = 0 */
3029 /* .. ==> 0XF8000788[12:12] = 0x00000000U */
3030 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3031 /* .. DisableRcvr = 0 */
3032 /* .. ==> 0XF8000788[13:13] = 0x00000000U */
3033 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3034 /* .. */
3035 EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
3036 /* .. TRI_ENABLE = 0 */
3037 /* .. ==> 0XF800078C[0:0] = 0x00000000U */
3038 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3039 /* .. L0_SEL = 0 */
3040 /* .. ==> 0XF800078C[1:1] = 0x00000000U */
3041 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3042 /* .. L1_SEL = 1 */
3043 /* .. ==> 0XF800078C[2:2] = 0x00000001U */
3044 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3045 /* .. L2_SEL = 0 */
3046 /* .. ==> 0XF800078C[4:3] = 0x00000000U */
3047 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3048 /* .. L3_SEL = 0 */
3049 /* .. ==> 0XF800078C[7:5] = 0x00000000U */
3050 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3051 /* .. Speed = 1 */
3052 /* .. ==> 0XF800078C[8:8] = 0x00000001U */
3053 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3054 /* .. IO_Type = 1 */
3055 /* .. ==> 0XF800078C[11:9] = 0x00000001U */
3056 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3057 /* .. PULLUP = 0 */
3058 /* .. ==> 0XF800078C[12:12] = 0x00000000U */
3059 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3060 /* .. DisableRcvr = 0 */
3061 /* .. ==> 0XF800078C[13:13] = 0x00000000U */
3062 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3063 /* .. */
3064 EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
3065 /* .. TRI_ENABLE = 1 */
3066 /* .. ==> 0XF8000790[0:0] = 0x00000001U */
3067 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
3068 /* .. L0_SEL = 0 */
3069 /* .. ==> 0XF8000790[1:1] = 0x00000000U */
3070 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3071 /* .. L1_SEL = 1 */
3072 /* .. ==> 0XF8000790[2:2] = 0x00000001U */
3073 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3074 /* .. L2_SEL = 0 */
3075 /* .. ==> 0XF8000790[4:3] = 0x00000000U */
3076 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3077 /* .. L3_SEL = 0 */
3078 /* .. ==> 0XF8000790[7:5] = 0x00000000U */
3079 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3080 /* .. Speed = 1 */
3081 /* .. ==> 0XF8000790[8:8] = 0x00000001U */
3082 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3083 /* .. IO_Type = 1 */
3084 /* .. ==> 0XF8000790[11:9] = 0x00000001U */
3085 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3086 /* .. PULLUP = 0 */
3087 /* .. ==> 0XF8000790[12:12] = 0x00000000U */
3088 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3089 /* .. DisableRcvr = 0 */
3090 /* .. ==> 0XF8000790[13:13] = 0x00000000U */
3091 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3092 /* .. */
3093 EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
3094 /* .. TRI_ENABLE = 0 */
3095 /* .. ==> 0XF8000794[0:0] = 0x00000000U */
3096 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3097 /* .. L0_SEL = 0 */
3098 /* .. ==> 0XF8000794[1:1] = 0x00000000U */
3099 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3100 /* .. L1_SEL = 1 */
3101 /* .. ==> 0XF8000794[2:2] = 0x00000001U */
3102 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3103 /* .. L2_SEL = 0 */
3104 /* .. ==> 0XF8000794[4:3] = 0x00000000U */
3105 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3106 /* .. L3_SEL = 0 */
3107 /* .. ==> 0XF8000794[7:5] = 0x00000000U */
3108 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3109 /* .. Speed = 1 */
3110 /* .. ==> 0XF8000794[8:8] = 0x00000001U */
3111 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3112 /* .. IO_Type = 1 */
3113 /* .. ==> 0XF8000794[11:9] = 0x00000001U */
3114 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3115 /* .. PULLUP = 0 */
3116 /* .. ==> 0XF8000794[12:12] = 0x00000000U */
3117 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3118 /* .. DisableRcvr = 0 */
3119 /* .. ==> 0XF8000794[13:13] = 0x00000000U */
3120 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3121 /* .. */
3122 EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
3123 /* .. TRI_ENABLE = 0 */
3124 /* .. ==> 0XF8000798[0:0] = 0x00000000U */
3125 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3126 /* .. L0_SEL = 0 */
3127 /* .. ==> 0XF8000798[1:1] = 0x00000000U */
3128 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3129 /* .. L1_SEL = 1 */
3130 /* .. ==> 0XF8000798[2:2] = 0x00000001U */
3131 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3132 /* .. L2_SEL = 0 */
3133 /* .. ==> 0XF8000798[4:3] = 0x00000000U */
3134 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3135 /* .. L3_SEL = 0 */
3136 /* .. ==> 0XF8000798[7:5] = 0x00000000U */
3137 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3138 /* .. Speed = 1 */
3139 /* .. ==> 0XF8000798[8:8] = 0x00000001U */
3140 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3141 /* .. IO_Type = 1 */
3142 /* .. ==> 0XF8000798[11:9] = 0x00000001U */
3143 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3144 /* .. PULLUP = 0 */
3145 /* .. ==> 0XF8000798[12:12] = 0x00000000U */
3146 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3147 /* .. DisableRcvr = 0 */
3148 /* .. ==> 0XF8000798[13:13] = 0x00000000U */
3149 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3150 /* .. */
3151 EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
3152 /* .. TRI_ENABLE = 0 */
3153 /* .. ==> 0XF800079C[0:0] = 0x00000000U */
3154 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3155 /* .. L0_SEL = 0 */
3156 /* .. ==> 0XF800079C[1:1] = 0x00000000U */
3157 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3158 /* .. L1_SEL = 1 */
3159 /* .. ==> 0XF800079C[2:2] = 0x00000001U */
3160 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3161 /* .. L2_SEL = 0 */
3162 /* .. ==> 0XF800079C[4:3] = 0x00000000U */
3163 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3164 /* .. L3_SEL = 0 */
3165 /* .. ==> 0XF800079C[7:5] = 0x00000000U */
3166 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3167 /* .. Speed = 1 */
3168 /* .. ==> 0XF800079C[8:8] = 0x00000001U */
3169 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3170 /* .. IO_Type = 1 */
3171 /* .. ==> 0XF800079C[11:9] = 0x00000001U */
3172 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3173 /* .. PULLUP = 0 */
3174 /* .. ==> 0XF800079C[12:12] = 0x00000000U */
3175 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3176 /* .. DisableRcvr = 0 */
3177 /* .. ==> 0XF800079C[13:13] = 0x00000000U */
3178 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3179 /* .. */
3180 EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
3181 /* .. TRI_ENABLE = 0 */
3182 /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
3183 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3184 /* .. L0_SEL = 0 */
3185 /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
3186 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3187 /* .. L1_SEL = 0 */
3188 /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
3189 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3190 /* .. L2_SEL = 0 */
3191 /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
3192 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3193 /* .. L3_SEL = 4 */
3194 /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
3195 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3196 /* .. Speed = 1 */
3197 /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
3198 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3199 /* .. IO_Type = 1 */
3200 /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
3201 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3202 /* .. PULLUP = 0 */
3203 /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
3204 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3205 /* .. DisableRcvr = 0 */
3206 /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
3207 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3208 /* .. */
3209 EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
3210 /* .. TRI_ENABLE = 0 */
3211 /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
3212 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3213 /* .. L0_SEL = 0 */
3214 /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
3215 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3216 /* .. L1_SEL = 0 */
3217 /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
3218 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3219 /* .. L2_SEL = 0 */
3220 /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
3221 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3222 /* .. L3_SEL = 4 */
3223 /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
3224 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3225 /* .. Speed = 1 */
3226 /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
3227 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3228 /* .. IO_Type = 1 */
3229 /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
3230 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3231 /* .. PULLUP = 0 */
3232 /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
3233 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3234 /* .. DisableRcvr = 0 */
3235 /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
3236 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3237 /* .. */
3238 EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
3239 /* .. TRI_ENABLE = 0 */
3240 /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
3241 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3242 /* .. L0_SEL = 0 */
3243 /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
3244 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3245 /* .. L1_SEL = 0 */
3246 /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
3247 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3248 /* .. L2_SEL = 0 */
3249 /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
3250 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3251 /* .. L3_SEL = 4 */
3252 /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
3253 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3254 /* .. Speed = 1 */
3255 /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
3256 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3257 /* .. IO_Type = 1 */
3258 /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
3259 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3260 /* .. PULLUP = 0 */
3261 /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
3262 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3263 /* .. DisableRcvr = 0 */
3264 /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
3265 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3266 /* .. */
3267 EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
3268 /* .. TRI_ENABLE = 0 */
3269 /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
3270 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3271 /* .. L0_SEL = 0 */
3272 /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
3273 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3274 /* .. L1_SEL = 0 */
3275 /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
3276 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3277 /* .. L2_SEL = 0 */
3278 /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
3279 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3280 /* .. L3_SEL = 4 */
3281 /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
3282 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3283 /* .. Speed = 1 */
3284 /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
3285 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3286 /* .. IO_Type = 1 */
3287 /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
3288 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3289 /* .. PULLUP = 0 */
3290 /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
3291 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3292 /* .. DisableRcvr = 0 */
3293 /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
3294 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3295 /* .. */
3296 EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
3297 /* .. TRI_ENABLE = 0 */
3298 /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
3299 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3300 /* .. L0_SEL = 0 */
3301 /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
3302 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3303 /* .. L1_SEL = 0 */
3304 /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
3305 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3306 /* .. L2_SEL = 0 */
3307 /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
3308 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3309 /* .. L3_SEL = 4 */
3310 /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
3311 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3312 /* .. Speed = 1 */
3313 /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
3314 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3315 /* .. IO_Type = 1 */
3316 /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
3317 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3318 /* .. PULLUP = 0 */
3319 /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
3320 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3321 /* .. DisableRcvr = 0 */
3322 /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
3323 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3324 /* .. */
3325 EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
3326 /* .. TRI_ENABLE = 0 */
3327 /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
3328 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3329 /* .. L0_SEL = 0 */
3330 /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
3331 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3332 /* .. L1_SEL = 0 */
3333 /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
3334 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3335 /* .. L2_SEL = 0 */
3336 /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
3337 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3338 /* .. L3_SEL = 4 */
3339 /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
3340 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3341 /* .. Speed = 1 */
3342 /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
3343 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3344 /* .. IO_Type = 1 */
3345 /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
3346 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3347 /* .. PULLUP = 0 */
3348 /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
3349 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3350 /* .. DisableRcvr = 0 */
3351 /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
3352 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3353 /* .. */
3354 EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
3355 /* .. TRI_ENABLE = 0 */
3356 /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
3357 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3358 /* .. L0_SEL = 0 */
3359 /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
3360 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3361 /* .. L1_SEL = 0 */
3362 /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
3363 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3364 /* .. L2_SEL = 0 */
3365 /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
3366 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3367 /* .. L3_SEL = 0 */
3368 /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
3369 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3370 /* .. Speed = 0 */
3371 /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
3372 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3373 /* .. IO_Type = 1 */
3374 /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
3375 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3376 /* .. PULLUP = 1 */
3377 /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
3378 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
3379 /* .. DisableRcvr = 0 */
3380 /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
3381 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3382 /* .. */
3383 EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
3384 /* .. TRI_ENABLE = 1 */
3385 /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
3386 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
3387 /* .. Speed = 0 */
3388 /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
3389 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3390 /* .. IO_Type = 1 */
3391 /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
3392 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3393 /* .. PULLUP = 0 */
3394 /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
3395 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3396 /* .. DisableRcvr = 0 */
3397 /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
3398 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3399 /* .. */
3400 EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
3401 /* .. TRI_ENABLE = 0 */
3402 /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
3403 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3404 /* .. L0_SEL = 0 */
3405 /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
3406 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3407 /* .. L1_SEL = 0 */
3408 /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
3409 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3410 /* .. L2_SEL = 0 */
3411 /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
3412 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3413 /* .. L3_SEL = 7 */
3414 /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
3415 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
3416 /* .. Speed = 0 */
3417 /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
3418 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3419 /* .. IO_Type = 1 */
3420 /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
3421 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3422 /* .. PULLUP = 0 */
3423 /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
3424 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3425 /* .. DisableRcvr = 0 */
3426 /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
3427 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3428 /* .. */
3429 EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
3430 /* .. TRI_ENABLE = 1 */
3431 /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
3432 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
3433 /* .. L0_SEL = 0 */
3434 /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
3435 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3436 /* .. L1_SEL = 0 */
3437 /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
3438 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3439 /* .. L2_SEL = 0 */
3440 /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
3441 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3442 /* .. L3_SEL = 7 */
3443 /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
3444 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
3445 /* .. Speed = 0 */
3446 /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
3447 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3448 /* .. IO_Type = 1 */
3449 /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
3450 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3451 /* .. PULLUP = 0 */
3452 /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
3453 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3454 /* .. DisableRcvr = 0 */
3455 /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
3456 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3457 /* .. */
3458 EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
3459 /* .. TRI_ENABLE = 0 */
3460 /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
3461 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3462 /* .. L0_SEL = 0 */
3463 /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
3464 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3465 /* .. L1_SEL = 0 */
3466 /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
3467 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3468 /* .. L2_SEL = 0 */
3469 /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
3470 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3471 /* .. L3_SEL = 0 */
3472 /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
3473 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3474 /* .. Speed = 0 */
3475 /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
3476 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3477 /* .. IO_Type = 1 */
3478 /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
3479 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3480 /* .. PULLUP = 0 */
3481 /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
3482 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3483 /* .. DisableRcvr = 0 */
3484 /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
3485 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3486 /* .. */
3487 EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
3488 /* .. TRI_ENABLE = 0 */
3489 /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
3490 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3491 /* .. L0_SEL = 0 */
3492 /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
3493 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3494 /* .. L1_SEL = 0 */
3495 /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
3496 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3497 /* .. L2_SEL = 0 */
3498 /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
3499 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3500 /* .. L3_SEL = 0 */
3501 /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
3502 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
3503 /* .. Speed = 0 */
3504 /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
3505 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3506 /* .. IO_Type = 1 */
3507 /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
3508 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3509 /* .. PULLUP = 0 */
3510 /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
3511 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3512 /* .. DisableRcvr = 0 */
3513 /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
3514 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3515 /* .. */
3516 EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
3517 /* .. TRI_ENABLE = 0 */
3518 /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
3519 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3520 /* .. L0_SEL = 0 */
3521 /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
3522 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3523 /* .. L1_SEL = 0 */
3524 /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
3525 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3526 /* .. L2_SEL = 0 */
3527 /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
3528 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3529 /* .. L3_SEL = 4 */
3530 /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
3531 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3532 /* .. Speed = 0 */
3533 /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
3534 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3535 /* .. IO_Type = 1 */
3536 /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
3537 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3538 /* .. PULLUP = 0 */
3539 /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
3540 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3541 /* .. DisableRcvr = 0 */
3542 /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
3543 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3544 /* .. */
3545 EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
3546 /* .. TRI_ENABLE = 0 */
3547 /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
3548 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3549 /* .. L0_SEL = 0 */
3550 /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
3551 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
3552 /* .. L1_SEL = 0 */
3553 /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
3554 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
3555 /* .. L2_SEL = 0 */
3556 /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
3557 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
3558 /* .. L3_SEL = 4 */
3559 /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
3560 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
3561 /* .. Speed = 0 */
3562 /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
3563 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3564 /* .. IO_Type = 1 */
3565 /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
3566 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
3567 /* .. PULLUP = 0 */
3568 /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
3569 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
3570 /* .. DisableRcvr = 0 */
3571 /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
3572 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
3573 /* .. */
3574 EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
3575 /* .. SDIO0_WP_SEL = 55 */
3576 /* .. ==> 0XF8000830[5:0] = 0x00000037U */
3577 /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
3578 /* .. SDIO0_CD_SEL = 47 */
3579 /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
3580 /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
3581 /* .. */
3582 EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
3583 /* .. FINISH: MIO PROGRAMMING */
3584 /* .. START: LOCK IT BACK */
3585 /* .. LOCK_KEY = 0X767B */
3586 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
3587 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
3588 /* .. */
3589 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
3590 /* .. FINISH: LOCK IT BACK */
3591 /* FINISH: top */
3592 /* */
3593 EMIT_EXIT(),
3594
3595 /* */
3596 };
3597
3598 unsigned long ps7_peripherals_init_data_3_0[] = {
3599 /* START: top */
3600 /* .. START: SLCR SETTINGS */
3601 /* .. UNLOCK_KEY = 0XDF0D */
3602 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
3603 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
3604 /* .. */
3605 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
3606 /* .. FINISH: SLCR SETTINGS */
3607 /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
3608 /* .. IBUF_DISABLE_MODE = 0x1 */
3609 /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
3610 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
3611 /* .. TERM_DISABLE_MODE = 0x1 */
3612 /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
3613 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3614 /* .. */
3615 EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
3616 /* .. IBUF_DISABLE_MODE = 0x1 */
3617 /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
3618 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
3619 /* .. TERM_DISABLE_MODE = 0x1 */
3620 /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
3621 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3622 /* .. */
3623 EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
3624 /* .. IBUF_DISABLE_MODE = 0x1 */
3625 /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
3626 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
3627 /* .. TERM_DISABLE_MODE = 0x1 */
3628 /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
3629 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3630 /* .. */
3631 EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
3632 /* .. IBUF_DISABLE_MODE = 0x1 */
3633 /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
3634 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
3635 /* .. TERM_DISABLE_MODE = 0x1 */
3636 /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
3637 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
3638 /* .. */
3639 EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
3640 /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
3641 /* .. START: LOCK IT BACK */
3642 /* .. LOCK_KEY = 0X767B */
3643 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
3644 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
3645 /* .. */
3646 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
3647 /* .. FINISH: LOCK IT BACK */
3648 /* .. START: SRAM/NOR SET OPMODE */
3649 /* .. FINISH: SRAM/NOR SET OPMODE */
3650 /* .. START: UART REGISTERS */
3651 /* .. BDIV = 0x6 */
3652 /* .. ==> 0XE0001034[7:0] = 0x00000006U */
3653 /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
3654 /* .. */
3655 EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
3656 /* .. CD = 0x7c */
3657 /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
3658 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
3659 /* .. */
3660 EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
3661 /* .. STPBRK = 0x0 */
3662 /* .. ==> 0XE0001000[8:8] = 0x00000000U */
3663 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
3664 /* .. STTBRK = 0x0 */
3665 /* .. ==> 0XE0001000[7:7] = 0x00000000U */
3666 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
3667 /* .. RSTTO = 0x0 */
3668 /* .. ==> 0XE0001000[6:6] = 0x00000000U */
3669 /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
3670 /* .. TXDIS = 0x0 */
3671 /* .. ==> 0XE0001000[5:5] = 0x00000000U */
3672 /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
3673 /* .. TXEN = 0x1 */
3674 /* .. ==> 0XE0001000[4:4] = 0x00000001U */
3675 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
3676 /* .. RXDIS = 0x0 */
3677 /* .. ==> 0XE0001000[3:3] = 0x00000000U */
3678 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
3679 /* .. RXEN = 0x1 */
3680 /* .. ==> 0XE0001000[2:2] = 0x00000001U */
3681 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
3682 /* .. TXRES = 0x1 */
3683 /* .. ==> 0XE0001000[1:1] = 0x00000001U */
3684 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
3685 /* .. RXRES = 0x1 */
3686 /* .. ==> 0XE0001000[0:0] = 0x00000001U */
3687 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
3688 /* .. */
3689 EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
3690 /* .. CHMODE = 0x0 */
3691 /* .. ==> 0XE0001004[9:8] = 0x00000000U */
3692 /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
3693 /* .. NBSTOP = 0x0 */
3694 /* .. ==> 0XE0001004[7:6] = 0x00000000U */
3695 /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
3696 /* .. PAR = 0x4 */
3697 /* .. ==> 0XE0001004[5:3] = 0x00000004U */
3698 /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
3699 /* .. CHRL = 0x0 */
3700 /* .. ==> 0XE0001004[2:1] = 0x00000000U */
3701 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
3702 /* .. CLKS = 0x0 */
3703 /* .. ==> 0XE0001004[0:0] = 0x00000000U */
3704 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
3705 /* .. */
3706 EMIT_MASKWRITE(0XE0001004, 0x000003FFU, 0x00000020U),
3707 /* .. FINISH: UART REGISTERS */
3708 /* .. START: QSPI REGISTERS */
3709 /* .. Holdb_dr = 1 */
3710 /* .. ==> 0XE000D000[19:19] = 0x00000001U */
3711 /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
3712 /* .. */
3713 EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
3714 /* .. FINISH: QSPI REGISTERS */
3715 /* .. START: PL POWER ON RESET REGISTERS */
3716 /* .. PCFG_POR_CNT_4K = 0 */
3717 /* .. ==> 0XF8007000[29:29] = 0x00000000U */
3718 /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
3719 /* .. */
3720 EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
3721 /* .. FINISH: PL POWER ON RESET REGISTERS */
3722 /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
3723 /* .. .. START: NAND SET CYCLE */
3724 /* .. .. FINISH: NAND SET CYCLE */
3725 /* .. .. START: OPMODE */
3726 /* .. .. FINISH: OPMODE */
3727 /* .. .. START: DIRECT COMMAND */
3728 /* .. .. FINISH: DIRECT COMMAND */
3729 /* .. .. START: SRAM/NOR CS0 SET CYCLE */
3730 /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
3731 /* .. .. START: DIRECT COMMAND */
3732 /* .. .. FINISH: DIRECT COMMAND */
3733 /* .. .. START: NOR CS0 BASE ADDRESS */
3734 /* .. .. FINISH: NOR CS0 BASE ADDRESS */
3735 /* .. .. START: SRAM/NOR CS1 SET CYCLE */
3736 /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
3737 /* .. .. START: DIRECT COMMAND */
3738 /* .. .. FINISH: DIRECT COMMAND */
3739 /* .. .. START: NOR CS1 BASE ADDRESS */
3740 /* .. .. FINISH: NOR CS1 BASE ADDRESS */
3741 /* .. .. START: USB RESET */
3742 /* .. .. .. START: USB0 RESET */
3743 /* .. .. .. .. START: DIR MODE BANK 0 */
3744 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
3745 /* .. .. .. .. START: DIR MODE BANK 1 */
3746 /* .. .. .. .. DIRECTION_1 = 0x4000 */
3747 /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
3748 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
3749 /* .. .. .. .. */
3750 EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
3751 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
3752 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3753 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3754 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3755 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3756 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3757 /* .. .. .. .. MASK_1_LSW = 0xbfff */
3758 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
3759 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
3760 /* .. .. .. .. DATA_1_LSW = 0x4000 */
3761 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
3762 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
3763 /* .. .. .. .. */
3764 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
3765 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3766 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3767 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3768 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
3769 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
3770 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
3771 /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
3772 /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
3773 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
3774 /* .. .. .. .. */
3775 EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
3776 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
3777 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3778 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3779 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3780 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3781 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
3782 /* .. .. .. .. MASK_1_LSW = 0xbfff */
3783 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
3784 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
3785 /* .. .. .. .. DATA_1_LSW = 0x0 */
3786 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
3787 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
3788 /* .. .. .. .. */
3789 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
3790 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3791 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3792 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3793 /* .. .. .. .. START: ADD 1 MS DELAY */
3794 /* .. .. .. .. */
3795 EMIT_MASKDELAY(0XF8F00200, 1),
3796 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
3797 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3798 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3799 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3800 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3801 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3802 /* .. .. .. .. MASK_1_LSW = 0xbfff */
3803 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
3804 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
3805 /* .. .. .. .. DATA_1_LSW = 0x4000 */
3806 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
3807 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
3808 /* .. .. .. .. */
3809 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
3810 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3811 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3812 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3813 /* .. .. .. FINISH: USB0 RESET */
3814 /* .. .. .. START: USB1 RESET */
3815 /* .. .. .. .. START: DIR MODE BANK 0 */
3816 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
3817 /* .. .. .. .. START: DIR MODE BANK 1 */
3818 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
3819 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3820 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3821 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3822 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3823 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3824 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3825 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3826 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3827 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
3828 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
3829 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
3830 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
3831 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3832 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3833 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3834 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3835 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
3836 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3837 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3838 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3839 /* .. .. .. .. START: ADD 1 MS DELAY */
3840 /* .. .. .. .. */
3841 EMIT_MASKDELAY(0XF8F00200, 1),
3842 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
3843 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3844 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3845 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3846 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3847 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3848 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3849 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3850 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3851 /* .. .. .. FINISH: USB1 RESET */
3852 /* .. .. FINISH: USB RESET */
3853 /* .. .. START: ENET RESET */
3854 /* .. .. .. START: ENET0 RESET */
3855 /* .. .. .. .. START: DIR MODE BANK 0 */
3856 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
3857 /* .. .. .. .. START: DIR MODE BANK 1 */
3858 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
3859 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3860 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3861 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3862 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3863 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3864 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3865 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3866 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3867 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
3868 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
3869 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
3870 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
3871 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3872 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3873 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3874 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3875 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
3876 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3877 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3878 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3879 /* .. .. .. .. START: ADD 1 MS DELAY */
3880 /* .. .. .. .. */
3881 EMIT_MASKDELAY(0XF8F00200, 1),
3882 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
3883 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3884 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3885 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3886 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3887 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3888 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3889 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3890 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3891 /* .. .. .. FINISH: ENET0 RESET */
3892 /* .. .. .. START: ENET1 RESET */
3893 /* .. .. .. .. START: DIR MODE BANK 0 */
3894 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
3895 /* .. .. .. .. START: DIR MODE BANK 1 */
3896 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
3897 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3898 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3899 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3900 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3901 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3902 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3903 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3904 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3905 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
3906 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
3907 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
3908 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
3909 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3910 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3911 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3912 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3913 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
3914 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3915 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3916 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3917 /* .. .. .. .. START: ADD 1 MS DELAY */
3918 /* .. .. .. .. */
3919 EMIT_MASKDELAY(0XF8F00200, 1),
3920 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
3921 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3922 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3923 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3924 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3925 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3926 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3927 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3928 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3929 /* .. .. .. FINISH: ENET1 RESET */
3930 /* .. .. FINISH: ENET RESET */
3931 /* .. .. START: I2C RESET */
3932 /* .. .. .. START: I2C0 RESET */
3933 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
3934 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
3935 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
3936 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
3937 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3938 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3939 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3940 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3941 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3942 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3943 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3944 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3945 /* .. .. .. .. START: OUTPUT ENABLE */
3946 /* .. .. .. .. FINISH: OUTPUT ENABLE */
3947 /* .. .. .. .. START: OUTPUT ENABLE */
3948 /* .. .. .. .. FINISH: OUTPUT ENABLE */
3949 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3950 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3951 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3952 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3953 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
3954 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3955 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3956 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3957 /* .. .. .. .. START: ADD 1 MS DELAY */
3958 /* .. .. .. .. */
3959 EMIT_MASKDELAY(0XF8F00200, 1),
3960 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
3961 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3962 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3963 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3964 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3965 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3966 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3967 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3968 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3969 /* .. .. .. FINISH: I2C0 RESET */
3970 /* .. .. .. START: I2C1 RESET */
3971 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
3972 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
3973 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
3974 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
3975 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3976 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3977 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
3978 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
3979 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
3980 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
3981 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
3982 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
3983 /* .. .. .. .. START: OUTPUT ENABLE */
3984 /* .. .. .. .. FINISH: OUTPUT ENABLE */
3985 /* .. .. .. .. START: OUTPUT ENABLE */
3986 /* .. .. .. .. FINISH: OUTPUT ENABLE */
3987 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
3988 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
3989 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
3990 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
3991 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
3992 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
3993 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
3994 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
3995 /* .. .. .. .. START: ADD 1 MS DELAY */
3996 /* .. .. .. .. */
3997 EMIT_MASKDELAY(0XF8F00200, 1),
3998 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
3999 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
4000 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
4001 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
4002 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
4003 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
4004 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
4005 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
4006 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
4007 /* .. .. .. FINISH: I2C1 RESET */
4008 /* .. .. FINISH: I2C RESET */
4009 /* .. .. START: NOR CHIP SELECT */
4010 /* .. .. .. START: DIR MODE BANK 0 */
4011 /* .. .. .. FINISH: DIR MODE BANK 0 */
4012 /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
4013 /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
4014 /* .. .. .. START: OUTPUT ENABLE BANK 0 */
4015 /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
4016 /* .. .. FINISH: NOR CHIP SELECT */
4017 /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
4018 /* FINISH: top */
4019 /* */
4020 EMIT_EXIT(),
4021
4022 /* */
4023 };
4024
4025 unsigned long ps7_post_config_3_0[] = {
4026 /* START: top */
4027 /* .. START: SLCR SETTINGS */
4028 /* .. UNLOCK_KEY = 0XDF0D */
4029 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
4030 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
4031 /* .. */
4032 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
4033 /* .. FINISH: SLCR SETTINGS */
4034 /* .. START: ENABLING LEVEL SHIFTER */
4035 /* .. USER_LVL_INP_EN_0 = 1 */
4036 /* .. ==> 0XF8000900[3:3] = 0x00000001U */
4037 /* .. ==> MASK : 0x00000008U VAL : 0x00000008U */
4038 /* .. USER_LVL_OUT_EN_0 = 1 */
4039 /* .. ==> 0XF8000900[2:2] = 0x00000001U */
4040 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
4041 /* .. USER_LVL_INP_EN_1 = 1 */
4042 /* .. ==> 0XF8000900[1:1] = 0x00000001U */
4043 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
4044 /* .. USER_LVL_OUT_EN_1 = 1 */
4045 /* .. ==> 0XF8000900[0:0] = 0x00000001U */
4046 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4047 /* .. */
4048 EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
4049 /* .. FINISH: ENABLING LEVEL SHIFTER */
4050 /* .. START: FPGA RESETS TO 0 */
4051 /* .. reserved_3 = 0 */
4052 /* .. ==> 0XF8000240[31:25] = 0x00000000U */
4053 /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
4054 /* .. reserved_FPGA_ACP_RST = 0 */
4055 /* .. ==> 0XF8000240[24:24] = 0x00000000U */
4056 /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
4057 /* .. reserved_FPGA_AXDS3_RST = 0 */
4058 /* .. ==> 0XF8000240[23:23] = 0x00000000U */
4059 /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
4060 /* .. reserved_FPGA_AXDS2_RST = 0 */
4061 /* .. ==> 0XF8000240[22:22] = 0x00000000U */
4062 /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
4063 /* .. reserved_FPGA_AXDS1_RST = 0 */
4064 /* .. ==> 0XF8000240[21:21] = 0x00000000U */
4065 /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
4066 /* .. reserved_FPGA_AXDS0_RST = 0 */
4067 /* .. ==> 0XF8000240[20:20] = 0x00000000U */
4068 /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
4069 /* .. reserved_2 = 0 */
4070 /* .. ==> 0XF8000240[19:18] = 0x00000000U */
4071 /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
4072 /* .. reserved_FSSW1_FPGA_RST = 0 */
4073 /* .. ==> 0XF8000240[17:17] = 0x00000000U */
4074 /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
4075 /* .. reserved_FSSW0_FPGA_RST = 0 */
4076 /* .. ==> 0XF8000240[16:16] = 0x00000000U */
4077 /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
4078 /* .. reserved_1 = 0 */
4079 /* .. ==> 0XF8000240[15:14] = 0x00000000U */
4080 /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
4081 /* .. reserved_FPGA_FMSW1_RST = 0 */
4082 /* .. ==> 0XF8000240[13:13] = 0x00000000U */
4083 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
4084 /* .. reserved_FPGA_FMSW0_RST = 0 */
4085 /* .. ==> 0XF8000240[12:12] = 0x00000000U */
4086 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
4087 /* .. reserved_FPGA_DMA3_RST = 0 */
4088 /* .. ==> 0XF8000240[11:11] = 0x00000000U */
4089 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
4090 /* .. reserved_FPGA_DMA2_RST = 0 */
4091 /* .. ==> 0XF8000240[10:10] = 0x00000000U */
4092 /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
4093 /* .. reserved_FPGA_DMA1_RST = 0 */
4094 /* .. ==> 0XF8000240[9:9] = 0x00000000U */
4095 /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
4096 /* .. reserved_FPGA_DMA0_RST = 0 */
4097 /* .. ==> 0XF8000240[8:8] = 0x00000000U */
4098 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
4099 /* .. reserved = 0 */
4100 /* .. ==> 0XF8000240[7:4] = 0x00000000U */
4101 /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
4102 /* .. FPGA3_OUT_RST = 0 */
4103 /* .. ==> 0XF8000240[3:3] = 0x00000000U */
4104 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
4105 /* .. FPGA2_OUT_RST = 0 */
4106 /* .. ==> 0XF8000240[2:2] = 0x00000000U */
4107 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
4108 /* .. FPGA1_OUT_RST = 0 */
4109 /* .. ==> 0XF8000240[1:1] = 0x00000000U */
4110 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
4111 /* .. FPGA0_OUT_RST = 0 */
4112 /* .. ==> 0XF8000240[0:0] = 0x00000000U */
4113 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4114 /* .. */
4115 EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
4116 /* .. FINISH: FPGA RESETS TO 0 */
4117 /* .. START: AFI REGISTERS */
4118 /* .. .. START: AFI0 REGISTERS */
4119 /* .. .. FINISH: AFI0 REGISTERS */
4120 /* .. .. START: AFI1 REGISTERS */
4121 /* .. .. FINISH: AFI1 REGISTERS */
4122 /* .. .. START: AFI2 REGISTERS */
4123 /* .. .. FINISH: AFI2 REGISTERS */
4124 /* .. .. START: AFI3 REGISTERS */
4125 /* .. .. FINISH: AFI3 REGISTERS */
4126 /* .. .. START: AFI2 SECURE REGISTER */
4127 /* .. .. FINISH: AFI2 SECURE REGISTER */
4128 /* .. FINISH: AFI REGISTERS */
4129 /* .. START: LOCK IT BACK */
4130 /* .. LOCK_KEY = 0X767B */
4131 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
4132 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
4133 /* .. */
4134 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
4135 /* .. FINISH: LOCK IT BACK */
4136 /* FINISH: top */
4137 /* */
4138 EMIT_EXIT(),
4139
4140 /* */
4141 };
4142
4143
4144 unsigned long ps7_pll_init_data_2_0[] = {
4145 /* START: top */
4146 /* .. START: SLCR SETTINGS */
4147 /* .. UNLOCK_KEY = 0XDF0D */
4148 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
4149 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
4150 /* .. */
4151 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
4152 /* .. FINISH: SLCR SETTINGS */
4153 /* .. START: PLL SLCR REGISTERS */
4154 /* .. .. START: ARM PLL INIT */
4155 /* .. .. PLL_RES = 0xc */
4156 /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
4157 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
4158 /* .. .. PLL_CP = 0x2 */
4159 /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
4160 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
4161 /* .. .. LOCK_CNT = 0x177 */
4162 /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
4163 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
4164 /* .. .. */
4165 EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
4166 /* .. .. .. START: UPDATE FB_DIV */
4167 /* .. .. .. PLL_FDIV = 0x1a */
4168 /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
4169 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
4170 /* .. .. .. */
4171 EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
4172 /* .. .. .. FINISH: UPDATE FB_DIV */
4173 /* .. .. .. START: BY PASS PLL */
4174 /* .. .. .. PLL_BYPASS_FORCE = 1 */
4175 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
4176 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
4177 /* .. .. .. */
4178 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
4179 /* .. .. .. FINISH: BY PASS PLL */
4180 /* .. .. .. START: ASSERT RESET */
4181 /* .. .. .. PLL_RESET = 1 */
4182 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
4183 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4184 /* .. .. .. */
4185 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
4186 /* .. .. .. FINISH: ASSERT RESET */
4187 /* .. .. .. START: DEASSERT RESET */
4188 /* .. .. .. PLL_RESET = 0 */
4189 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
4190 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4191 /* .. .. .. */
4192 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
4193 /* .. .. .. FINISH: DEASSERT RESET */
4194 /* .. .. .. START: CHECK PLL STATUS */
4195 /* .. .. .. ARM_PLL_LOCK = 1 */
4196 /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
4197 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4198 /* .. .. .. */
4199 EMIT_MASKPOLL(0XF800010C, 0x00000001U),
4200 /* .. .. .. FINISH: CHECK PLL STATUS */
4201 /* .. .. .. START: REMOVE PLL BY PASS */
4202 /* .. .. .. PLL_BYPASS_FORCE = 0 */
4203 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
4204 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
4205 /* .. .. .. */
4206 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
4207 /* .. .. .. FINISH: REMOVE PLL BY PASS */
4208 /* .. .. .. SRCSEL = 0x0 */
4209 /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
4210 /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4211 /* .. .. .. DIVISOR = 0x2 */
4212 /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
4213 /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
4214 /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
4215 /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
4216 /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
4217 /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
4218 /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
4219 /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
4220 /* .. .. .. CPU_2XCLKACT = 0x1 */
4221 /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
4222 /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
4223 /* .. .. .. CPU_1XCLKACT = 0x1 */
4224 /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
4225 /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
4226 /* .. .. .. CPU_PERI_CLKACT = 0x1 */
4227 /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
4228 /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
4229 /* .. .. .. */
4230 EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
4231 /* .. .. FINISH: ARM PLL INIT */
4232 /* .. .. START: DDR PLL INIT */
4233 /* .. .. PLL_RES = 0xc */
4234 /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
4235 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
4236 /* .. .. PLL_CP = 0x2 */
4237 /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
4238 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
4239 /* .. .. LOCK_CNT = 0x1db */
4240 /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
4241 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
4242 /* .. .. */
4243 EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
4244 /* .. .. .. START: UPDATE FB_DIV */
4245 /* .. .. .. PLL_FDIV = 0x15 */
4246 /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
4247 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
4248 /* .. .. .. */
4249 EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
4250 /* .. .. .. FINISH: UPDATE FB_DIV */
4251 /* .. .. .. START: BY PASS PLL */
4252 /* .. .. .. PLL_BYPASS_FORCE = 1 */
4253 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
4254 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
4255 /* .. .. .. */
4256 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
4257 /* .. .. .. FINISH: BY PASS PLL */
4258 /* .. .. .. START: ASSERT RESET */
4259 /* .. .. .. PLL_RESET = 1 */
4260 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
4261 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4262 /* .. .. .. */
4263 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
4264 /* .. .. .. FINISH: ASSERT RESET */
4265 /* .. .. .. START: DEASSERT RESET */
4266 /* .. .. .. PLL_RESET = 0 */
4267 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
4268 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4269 /* .. .. .. */
4270 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
4271 /* .. .. .. FINISH: DEASSERT RESET */
4272 /* .. .. .. START: CHECK PLL STATUS */
4273 /* .. .. .. DDR_PLL_LOCK = 1 */
4274 /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
4275 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
4276 /* .. .. .. */
4277 EMIT_MASKPOLL(0XF800010C, 0x00000002U),
4278 /* .. .. .. FINISH: CHECK PLL STATUS */
4279 /* .. .. .. START: REMOVE PLL BY PASS */
4280 /* .. .. .. PLL_BYPASS_FORCE = 0 */
4281 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
4282 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
4283 /* .. .. .. */
4284 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
4285 /* .. .. .. FINISH: REMOVE PLL BY PASS */
4286 /* .. .. .. DDR_3XCLKACT = 0x1 */
4287 /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
4288 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4289 /* .. .. .. DDR_2XCLKACT = 0x1 */
4290 /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
4291 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
4292 /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
4293 /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
4294 /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
4295 /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
4296 /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
4297 /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
4298 /* .. .. .. */
4299 EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
4300 /* .. .. FINISH: DDR PLL INIT */
4301 /* .. .. START: IO PLL INIT */
4302 /* .. .. PLL_RES = 0xc */
4303 /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
4304 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
4305 /* .. .. PLL_CP = 0x2 */
4306 /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
4307 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
4308 /* .. .. LOCK_CNT = 0x1f4 */
4309 /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
4310 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
4311 /* .. .. */
4312 EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
4313 /* .. .. .. START: UPDATE FB_DIV */
4314 /* .. .. .. PLL_FDIV = 0x14 */
4315 /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
4316 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
4317 /* .. .. .. */
4318 EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
4319 /* .. .. .. FINISH: UPDATE FB_DIV */
4320 /* .. .. .. START: BY PASS PLL */
4321 /* .. .. .. PLL_BYPASS_FORCE = 1 */
4322 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
4323 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
4324 /* .. .. .. */
4325 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
4326 /* .. .. .. FINISH: BY PASS PLL */
4327 /* .. .. .. START: ASSERT RESET */
4328 /* .. .. .. PLL_RESET = 1 */
4329 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
4330 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4331 /* .. .. .. */
4332 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
4333 /* .. .. .. FINISH: ASSERT RESET */
4334 /* .. .. .. START: DEASSERT RESET */
4335 /* .. .. .. PLL_RESET = 0 */
4336 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
4337 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4338 /* .. .. .. */
4339 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
4340 /* .. .. .. FINISH: DEASSERT RESET */
4341 /* .. .. .. START: CHECK PLL STATUS */
4342 /* .. .. .. IO_PLL_LOCK = 1 */
4343 /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
4344 /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
4345 /* .. .. .. */
4346 EMIT_MASKPOLL(0XF800010C, 0x00000004U),
4347 /* .. .. .. FINISH: CHECK PLL STATUS */
4348 /* .. .. .. START: REMOVE PLL BY PASS */
4349 /* .. .. .. PLL_BYPASS_FORCE = 0 */
4350 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
4351 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
4352 /* .. .. .. */
4353 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
4354 /* .. .. .. FINISH: REMOVE PLL BY PASS */
4355 /* .. .. FINISH: IO PLL INIT */
4356 /* .. FINISH: PLL SLCR REGISTERS */
4357 /* .. START: LOCK IT BACK */
4358 /* .. LOCK_KEY = 0X767B */
4359 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
4360 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
4361 /* .. */
4362 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
4363 /* .. FINISH: LOCK IT BACK */
4364 /* FINISH: top */
4365 /* */
4366 EMIT_EXIT(),
4367
4368 /* */
4369 };
4370
4371 unsigned long ps7_clock_init_data_2_0[] = {
4372 /* START: top */
4373 /* .. START: SLCR SETTINGS */
4374 /* .. UNLOCK_KEY = 0XDF0D */
4375 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
4376 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
4377 /* .. */
4378 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
4379 /* .. FINISH: SLCR SETTINGS */
4380 /* .. START: CLOCK CONTROL SLCR REGISTERS */
4381 /* .. CLKACT = 0x1 */
4382 /* .. ==> 0XF8000128[0:0] = 0x00000001U */
4383 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4384 /* .. DIVISOR0 = 0x34 */
4385 /* .. ==> 0XF8000128[13:8] = 0x00000034U */
4386 /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
4387 /* .. DIVISOR1 = 0x2 */
4388 /* .. ==> 0XF8000128[25:20] = 0x00000002U */
4389 /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
4390 /* .. */
4391 EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
4392 /* .. CLKACT = 0x1 */
4393 /* .. ==> 0XF8000138[0:0] = 0x00000001U */
4394 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4395 /* .. SRCSEL = 0x0 */
4396 /* .. ==> 0XF8000138[4:4] = 0x00000000U */
4397 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
4398 /* .. */
4399 EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
4400 /* .. CLKACT = 0x1 */
4401 /* .. ==> 0XF8000140[0:0] = 0x00000001U */
4402 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4403 /* .. SRCSEL = 0x0 */
4404 /* .. ==> 0XF8000140[6:4] = 0x00000000U */
4405 /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
4406 /* .. DIVISOR = 0x8 */
4407 /* .. ==> 0XF8000140[13:8] = 0x00000008U */
4408 /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
4409 /* .. DIVISOR1 = 0x1 */
4410 /* .. ==> 0XF8000140[25:20] = 0x00000001U */
4411 /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
4412 /* .. */
4413 EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
4414 /* .. CLKACT = 0x1 */
4415 /* .. ==> 0XF800014C[0:0] = 0x00000001U */
4416 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4417 /* .. SRCSEL = 0x0 */
4418 /* .. ==> 0XF800014C[5:4] = 0x00000000U */
4419 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4420 /* .. DIVISOR = 0x5 */
4421 /* .. ==> 0XF800014C[13:8] = 0x00000005U */
4422 /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
4423 /* .. */
4424 EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
4425 /* .. CLKACT0 = 0x1 */
4426 /* .. ==> 0XF8000150[0:0] = 0x00000001U */
4427 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4428 /* .. CLKACT1 = 0x0 */
4429 /* .. ==> 0XF8000150[1:1] = 0x00000000U */
4430 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
4431 /* .. SRCSEL = 0x0 */
4432 /* .. ==> 0XF8000150[5:4] = 0x00000000U */
4433 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4434 /* .. DIVISOR = 0x14 */
4435 /* .. ==> 0XF8000150[13:8] = 0x00000014U */
4436 /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
4437 /* .. */
4438 EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
4439 /* .. CLKACT0 = 0x0 */
4440 /* .. ==> 0XF8000154[0:0] = 0x00000000U */
4441 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4442 /* .. CLKACT1 = 0x1 */
4443 /* .. ==> 0XF8000154[1:1] = 0x00000001U */
4444 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
4445 /* .. SRCSEL = 0x0 */
4446 /* .. ==> 0XF8000154[5:4] = 0x00000000U */
4447 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4448 /* .. DIVISOR = 0xa */
4449 /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
4450 /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
4451 /* .. */
4452 EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
4453 /* .. .. START: TRACE CLOCK */
4454 /* .. .. FINISH: TRACE CLOCK */
4455 /* .. .. CLKACT = 0x1 */
4456 /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
4457 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4458 /* .. .. SRCSEL = 0x0 */
4459 /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
4460 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4461 /* .. .. DIVISOR = 0x5 */
4462 /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
4463 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
4464 /* .. .. */
4465 EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
4466 /* .. .. SRCSEL = 0x0 */
4467 /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
4468 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4469 /* .. .. DIVISOR0 = 0xa */
4470 /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
4471 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
4472 /* .. .. DIVISOR1 = 0x1 */
4473 /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
4474 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
4475 /* .. .. */
4476 EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
4477 /* .. .. SRCSEL = 0x0 */
4478 /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
4479 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4480 /* .. .. DIVISOR0 = 0x7 */
4481 /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
4482 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
4483 /* .. .. DIVISOR1 = 0x1 */
4484 /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
4485 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
4486 /* .. .. */
4487 EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
4488 /* .. .. SRCSEL = 0x0 */
4489 /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
4490 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4491 /* .. .. DIVISOR0 = 0x5 */
4492 /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
4493 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
4494 /* .. .. DIVISOR1 = 0x1 */
4495 /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
4496 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
4497 /* .. .. */
4498 EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
4499 /* .. .. SRCSEL = 0x0 */
4500 /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
4501 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
4502 /* .. .. DIVISOR0 = 0x14 */
4503 /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
4504 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
4505 /* .. .. DIVISOR1 = 0x1 */
4506 /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
4507 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
4508 /* .. .. */
4509 EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
4510 /* .. .. CLK_621_TRUE = 0x1 */
4511 /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
4512 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4513 /* .. .. */
4514 EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
4515 /* .. .. DMA_CPU_2XCLKACT = 0x1 */
4516 /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
4517 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
4518 /* .. .. USB0_CPU_1XCLKACT = 0x1 */
4519 /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
4520 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
4521 /* .. .. USB1_CPU_1XCLKACT = 0x1 */
4522 /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
4523 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
4524 /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
4525 /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
4526 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
4527 /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
4528 /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
4529 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
4530 /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
4531 /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
4532 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
4533 /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
4534 /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
4535 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
4536 /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
4537 /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
4538 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
4539 /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
4540 /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
4541 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
4542 /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
4543 /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
4544 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
4545 /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
4546 /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
4547 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
4548 /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
4549 /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
4550 /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
4551 /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
4552 /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
4553 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
4554 /* .. .. UART0_CPU_1XCLKACT = 0x0 */
4555 /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
4556 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
4557 /* .. .. UART1_CPU_1XCLKACT = 0x1 */
4558 /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
4559 /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
4560 /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
4561 /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
4562 /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
4563 /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
4564 /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
4565 /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
4566 /* .. .. SMC_CPU_1XCLKACT = 0x1 */
4567 /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
4568 /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
4569 /* .. .. */
4570 EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
4571 /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
4572 /* .. START: THIS SHOULD BE BLANK */
4573 /* .. FINISH: THIS SHOULD BE BLANK */
4574 /* .. START: LOCK IT BACK */
4575 /* .. LOCK_KEY = 0X767B */
4576 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
4577 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
4578 /* .. */
4579 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
4580 /* .. FINISH: LOCK IT BACK */
4581 /* FINISH: top */
4582 /* */
4583 EMIT_EXIT(),
4584
4585 /* */
4586 };
4587
4588 unsigned long ps7_ddr_init_data_2_0[] = {
4589 /* START: top */
4590 /* .. START: DDR INITIALIZATION */
4591 /* .. .. START: LOCK DDR */
4592 /* .. .. reg_ddrc_soft_rstb = 0 */
4593 /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
4594 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4595 /* .. .. reg_ddrc_powerdown_en = 0x0 */
4596 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
4597 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
4598 /* .. .. reg_ddrc_data_bus_width = 0x0 */
4599 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
4600 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
4601 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
4602 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
4603 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
4604 /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
4605 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
4606 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
4607 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
4608 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
4609 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
4610 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
4611 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
4612 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
4613 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
4614 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
4615 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
4616 /* .. .. */
4617 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
4618 /* .. .. FINISH: LOCK DDR */
4619 /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
4620 /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
4621 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
4622 /* .. .. reg_ddrc_active_ranks = 0x1 */
4623 /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
4624 /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
4625 /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
4626 /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
4627 /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
4628 /* .. .. reg_ddrc_wr_odt_block = 0x1 */
4629 /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
4630 /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
4631 /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
4632 /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
4633 /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
4634 /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
4635 /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
4636 /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
4637 /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
4638 /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
4639 /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
4640 /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
4641 /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
4642 /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
4643 /* .. .. */
4644 EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
4645 /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
4646 /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
4647 /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
4648 /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
4649 /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
4650 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
4651 /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
4652 /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
4653 /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
4654 /* .. .. */
4655 EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
4656 /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
4657 /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
4658 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
4659 /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
4660 /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
4661 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
4662 /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
4663 /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
4664 /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
4665 /* .. .. */
4666 EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
4667 /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
4668 /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
4669 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
4670 /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
4671 /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
4672 /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
4673 /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
4674 /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
4675 /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
4676 /* .. .. */
4677 EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
4678 /* .. .. reg_ddrc_t_rc = 0x1a */
4679 /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
4680 /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
4681 /* .. .. reg_ddrc_t_rfc_min = 0x54 */
4682 /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
4683 /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
4684 /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
4685 /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
4686 /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
4687 /* .. .. */
4688 EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
4689 /* .. .. reg_ddrc_wr2pre = 0x12 */
4690 /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
4691 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
4692 /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
4693 /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
4694 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
4695 /* .. .. reg_ddrc_t_faw = 0x15 */
4696 /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
4697 /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
4698 /* .. .. reg_ddrc_t_ras_max = 0x23 */
4699 /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
4700 /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
4701 /* .. .. reg_ddrc_t_ras_min = 0x13 */
4702 /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
4703 /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
4704 /* .. .. reg_ddrc_t_cke = 0x4 */
4705 /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
4706 /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
4707 /* .. .. */
4708 EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
4709 /* .. .. reg_ddrc_write_latency = 0x5 */
4710 /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
4711 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
4712 /* .. .. reg_ddrc_rd2wr = 0x7 */
4713 /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
4714 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
4715 /* .. .. reg_ddrc_wr2rd = 0xe */
4716 /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
4717 /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
4718 /* .. .. reg_ddrc_t_xp = 0x4 */
4719 /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
4720 /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
4721 /* .. .. reg_ddrc_pad_pd = 0x0 */
4722 /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
4723 /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
4724 /* .. .. reg_ddrc_rd2pre = 0x4 */
4725 /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
4726 /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
4727 /* .. .. reg_ddrc_t_rcd = 0x7 */
4728 /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
4729 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
4730 /* .. .. */
4731 EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
4732 /* .. .. reg_ddrc_t_ccd = 0x4 */
4733 /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
4734 /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
4735 /* .. .. reg_ddrc_t_rrd = 0x6 */
4736 /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
4737 /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
4738 /* .. .. reg_ddrc_refresh_margin = 0x2 */
4739 /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
4740 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
4741 /* .. .. reg_ddrc_t_rp = 0x7 */
4742 /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
4743 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
4744 /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
4745 /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
4746 /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
4747 /* .. .. reg_ddrc_sdram = 0x1 */
4748 /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
4749 /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
4750 /* .. .. reg_ddrc_mobile = 0x0 */
4751 /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
4752 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
4753 /* .. .. reg_ddrc_clock_stop_en = 0x0 */
4754 /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
4755 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
4756 /* .. .. reg_ddrc_read_latency = 0x7 */
4757 /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
4758 /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
4759 /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
4760 /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
4761 /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
4762 /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
4763 /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
4764 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
4765 /* .. .. reg_ddrc_loopback = 0x0 */
4766 /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
4767 /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
4768 /* .. .. */
4769 EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
4770 /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
4771 /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
4772 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4773 /* .. .. reg_ddrc_prefer_write = 0x0 */
4774 /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
4775 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
4776 /* .. .. reg_ddrc_max_rank_rd = 0xf */
4777 /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
4778 /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
4779 /* .. .. reg_ddrc_mr_wr = 0x0 */
4780 /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
4781 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
4782 /* .. .. reg_ddrc_mr_addr = 0x0 */
4783 /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
4784 /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
4785 /* .. .. reg_ddrc_mr_data = 0x0 */
4786 /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
4787 /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
4788 /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
4789 /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
4790 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
4791 /* .. .. reg_ddrc_mr_type = 0x0 */
4792 /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
4793 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
4794 /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
4795 /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
4796 /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
4797 /* .. .. */
4798 EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
4799 /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
4800 /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
4801 /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
4802 /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
4803 /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
4804 /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
4805 /* .. .. reg_ddrc_t_mrd = 0x4 */
4806 /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
4807 /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
4808 /* .. .. */
4809 EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
4810 /* .. .. reg_ddrc_emr2 = 0x8 */
4811 /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
4812 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
4813 /* .. .. reg_ddrc_emr3 = 0x0 */
4814 /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
4815 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
4816 /* .. .. */
4817 EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
4818 /* .. .. reg_ddrc_mr = 0x930 */
4819 /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
4820 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
4821 /* .. .. reg_ddrc_emr = 0x4 */
4822 /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
4823 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
4824 /* .. .. */
4825 EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
4826 /* .. .. reg_ddrc_burst_rdwr = 0x4 */
4827 /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
4828 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
4829 /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
4830 /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
4831 /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
4832 /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
4833 /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
4834 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
4835 /* .. .. reg_ddrc_burstchop = 0x0 */
4836 /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
4837 /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
4838 /* .. .. */
4839 EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
4840 /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
4841 /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
4842 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
4843 /* .. .. reg_ddrc_dis_dq = 0x0 */
4844 /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
4845 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
4846 /* .. .. reg_phy_debug_mode = 0x0 */
4847 /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
4848 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
4849 /* .. .. reg_phy_wr_level_start = 0x0 */
4850 /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
4851 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
4852 /* .. .. reg_phy_rd_level_start = 0x0 */
4853 /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
4854 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
4855 /* .. .. reg_phy_dq0_wait_t = 0x0 */
4856 /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
4857 /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
4858 /* .. .. */
4859 EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
4860 /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
4861 /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
4862 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
4863 /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
4864 /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
4865 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
4866 /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
4867 /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
4868 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
4869 /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
4870 /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
4871 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
4872 /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
4873 /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
4874 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
4875 /* .. .. */
4876 EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
4877 /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
4878 /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
4879 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
4880 /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
4881 /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
4882 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
4883 /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
4884 /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
4885 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
4886 /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
4887 /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
4888 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
4889 /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
4890 /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
4891 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
4892 /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
4893 /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
4894 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
4895 /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
4896 /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
4897 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
4898 /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
4899 /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
4900 /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
4901 /* .. .. */
4902 EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
4903 /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
4904 /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
4905 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
4906 /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
4907 /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
4908 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
4909 /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
4910 /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
4911 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
4912 /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
4913 /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
4914 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
4915 /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
4916 /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
4917 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
4918 /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
4919 /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
4920 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
4921 /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
4922 /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
4923 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
4924 /* .. .. */
4925 EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
4926 /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
4927 /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
4928 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
4929 /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
4930 /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
4931 /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
4932 /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
4933 /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
4934 /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
4935 /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
4936 /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
4937 /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
4938 /* .. .. reg_phy_rd_local_odt = 0x0 */
4939 /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
4940 /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
4941 /* .. .. reg_phy_wr_local_odt = 0x3 */
4942 /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
4943 /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
4944 /* .. .. reg_phy_idle_local_odt = 0x3 */
4945 /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
4946 /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
4947 /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
4948 /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
4949 /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
4950 /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
4951 /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
4952 /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
4953 /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
4954 /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
4955 /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
4956 /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
4957 /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
4958 /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
4959 /* .. .. */
4960 EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
4961 /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
4962 /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
4963 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
4964 /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
4965 /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
4966 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
4967 /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
4968 /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
4969 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
4970 /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
4971 /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
4972 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
4973 /* .. .. reg_phy_use_fixed_re = 0x1 */
4974 /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
4975 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
4976 /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
4977 /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
4978 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
4979 /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
4980 /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
4981 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
4982 /* .. .. reg_phy_clk_stall_level = 0x0 */
4983 /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
4984 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
4985 /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
4986 /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
4987 /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
4988 /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
4989 /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
4990 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
4991 /* .. .. */
4992 EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
4993 /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
4994 /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
4995 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
4996 /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
4997 /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
4998 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
4999 /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
5000 /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
5001 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5002 /* .. .. */
5003 EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
5004 /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
5005 /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
5006 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
5007 /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
5008 /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
5009 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
5010 /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
5011 /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
5012 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
5013 /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
5014 /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
5015 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
5016 /* .. .. */
5017 EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
5018 /* .. .. reg_ddrc_pageclose = 0x0 */
5019 /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
5020 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5021 /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
5022 /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
5023 /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
5024 /* .. .. reg_ddrc_auto_pre_en = 0x0 */
5025 /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
5026 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
5027 /* .. .. reg_ddrc_refresh_update_level = 0x0 */
5028 /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
5029 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
5030 /* .. .. reg_ddrc_dis_wc = 0x0 */
5031 /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
5032 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
5033 /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
5034 /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
5035 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5036 /* .. .. reg_ddrc_selfref_en = 0x0 */
5037 /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
5038 /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
5039 /* .. .. */
5040 EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
5041 /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
5042 /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
5043 /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
5044 /* .. .. reg_arb_go2critical_en = 0x1 */
5045 /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
5046 /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
5047 /* .. .. */
5048 EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
5049 /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
5050 /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
5051 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
5052 /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
5053 /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
5054 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
5055 /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
5056 /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
5057 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
5058 /* .. .. */
5059 EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
5060 /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
5061 /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
5062 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
5063 /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
5064 /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
5065 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
5066 /* .. .. */
5067 EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
5068 /* .. .. reg_ddrc_dfi_t_ctrl_delay = 0x1 */
5069 /* .. .. ==> 0XF8006078[3:0] = 0x00000001U */
5070 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000001U */
5071 /* .. .. reg_ddrc_dfi_t_dram_clk_disable = 0x1 */
5072 /* .. .. ==> 0XF8006078[7:4] = 0x00000001U */
5073 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000010U */
5074 /* .. .. reg_ddrc_dfi_t_dram_clk_enable = 0x1 */
5075 /* .. .. ==> 0XF8006078[11:8] = 0x00000001U */
5076 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000100U */
5077 /* .. .. reg_ddrc_t_cksre = 0x6 */
5078 /* .. .. ==> 0XF8006078[15:12] = 0x00000006U */
5079 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
5080 /* .. .. reg_ddrc_t_cksrx = 0x6 */
5081 /* .. .. ==> 0XF8006078[19:16] = 0x00000006U */
5082 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
5083 /* .. .. reg_ddrc_t_ckesr = 0x4 */
5084 /* .. .. ==> 0XF8006078[25:20] = 0x00000004U */
5085 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U */
5086 /* .. .. */
5087 EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
5088 /* .. .. reg_ddrc_t_ckpde = 0x2 */
5089 /* .. .. ==> 0XF800607C[3:0] = 0x00000002U */
5090 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000002U */
5091 /* .. .. reg_ddrc_t_ckpdx = 0x2 */
5092 /* .. .. ==> 0XF800607C[7:4] = 0x00000002U */
5093 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U */
5094 /* .. .. reg_ddrc_t_ckdpde = 0x2 */
5095 /* .. .. ==> 0XF800607C[11:8] = 0x00000002U */
5096 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
5097 /* .. .. reg_ddrc_t_ckdpdx = 0x2 */
5098 /* .. .. ==> 0XF800607C[15:12] = 0x00000002U */
5099 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00002000U */
5100 /* .. .. reg_ddrc_t_ckcsx = 0x3 */
5101 /* .. .. ==> 0XF800607C[19:16] = 0x00000003U */
5102 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00030000U */
5103 /* .. .. */
5104 EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
5105 /* .. .. refresh_timer0_start_value_x32 = 0x0 */
5106 /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
5107 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
5108 /* .. .. refresh_timer1_start_value_x32 = 0x8 */
5109 /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
5110 /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
5111 /* .. .. */
5112 EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
5113 /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
5114 /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
5115 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5116 /* .. .. reg_ddrc_ddr3 = 0x1 */
5117 /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
5118 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
5119 /* .. .. reg_ddrc_t_mod = 0x200 */
5120 /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
5121 /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
5122 /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
5123 /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
5124 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
5125 /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
5126 /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
5127 /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
5128 /* .. .. */
5129 EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
5130 /* .. .. t_zq_short_interval_x1024 = 0xc845 */
5131 /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
5132 /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
5133 /* .. .. dram_rstn_x1024 = 0x67 */
5134 /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
5135 /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
5136 /* .. .. */
5137 EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
5138 /* .. .. deeppowerdown_en = 0x0 */
5139 /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
5140 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5141 /* .. .. deeppowerdown_to_x1024 = 0xff */
5142 /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
5143 /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
5144 /* .. .. */
5145 EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
5146 /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
5147 /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
5148 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
5149 /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
5150 /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
5151 /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
5152 /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
5153 /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
5154 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
5155 /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
5156 /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
5157 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
5158 /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
5159 /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
5160 /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
5161 /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
5162 /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
5163 /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
5164 /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
5165 /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
5166 /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
5167 /* .. .. */
5168 EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
5169 /* .. .. reg_ddrc_2t_delay = 0x0 */
5170 /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
5171 /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
5172 /* .. .. reg_ddrc_skip_ocd = 0x1 */
5173 /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
5174 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
5175 /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
5176 /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
5177 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5178 /* .. .. */
5179 EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
5180 /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
5181 /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
5182 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
5183 /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
5184 /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
5185 /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
5186 /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
5187 /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
5188 /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
5189 /* .. .. */
5190 EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
5191 /* .. .. START: RESET ECC ERROR */
5192 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
5193 /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
5194 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5195 /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
5196 /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
5197 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
5198 /* .. .. */
5199 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
5200 /* .. .. FINISH: RESET ECC ERROR */
5201 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
5202 /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
5203 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5204 /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
5205 /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
5206 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5207 /* .. .. */
5208 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
5209 /* .. .. CORR_ECC_LOG_VALID = 0x0 */
5210 /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
5211 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5212 /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
5213 /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
5214 /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
5215 /* .. .. */
5216 EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
5217 /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
5218 /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
5219 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5220 /* .. .. */
5221 EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
5222 /* .. .. STAT_NUM_CORR_ERR = 0x0 */
5223 /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
5224 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
5225 /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
5226 /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
5227 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
5228 /* .. .. */
5229 EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
5230 /* .. .. reg_ddrc_ecc_mode = 0x0 */
5231 /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
5232 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
5233 /* .. .. reg_ddrc_dis_scrub = 0x1 */
5234 /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
5235 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
5236 /* .. .. */
5237 EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
5238 /* .. .. reg_phy_dif_on = 0x0 */
5239 /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
5240 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
5241 /* .. .. reg_phy_dif_off = 0x0 */
5242 /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
5243 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
5244 /* .. .. */
5245 EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
5246 /* .. .. reg_phy_data_slice_in_use = 0x1 */
5247 /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
5248 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5249 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
5250 /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
5251 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5252 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
5253 /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
5254 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5255 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
5256 /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
5257 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5258 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
5259 /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
5260 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5261 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
5262 /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
5263 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
5264 /* .. .. reg_phy_bist_shift_dq = 0x0 */
5265 /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
5266 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
5267 /* .. .. reg_phy_bist_err_clr = 0x0 */
5268 /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
5269 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
5270 /* .. .. reg_phy_dq_offset = 0x40 */
5271 /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
5272 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
5273 /* .. .. */
5274 EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
5275 /* .. .. reg_phy_data_slice_in_use = 0x1 */
5276 /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
5277 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5278 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
5279 /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
5280 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5281 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
5282 /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
5283 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5284 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
5285 /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
5286 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5287 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
5288 /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
5289 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5290 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
5291 /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
5292 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
5293 /* .. .. reg_phy_bist_shift_dq = 0x0 */
5294 /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
5295 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
5296 /* .. .. reg_phy_bist_err_clr = 0x0 */
5297 /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
5298 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
5299 /* .. .. reg_phy_dq_offset = 0x40 */
5300 /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
5301 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
5302 /* .. .. */
5303 EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
5304 /* .. .. reg_phy_data_slice_in_use = 0x1 */
5305 /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
5306 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5307 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
5308 /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
5309 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5310 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
5311 /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
5312 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5313 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
5314 /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
5315 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5316 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
5317 /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
5318 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5319 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
5320 /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
5321 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
5322 /* .. .. reg_phy_bist_shift_dq = 0x0 */
5323 /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
5324 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
5325 /* .. .. reg_phy_bist_err_clr = 0x0 */
5326 /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
5327 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
5328 /* .. .. reg_phy_dq_offset = 0x40 */
5329 /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
5330 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
5331 /* .. .. reg_phy_data_slice_in_use = 0x1 */
5332 /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
5333 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5334 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
5335 /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
5336 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5337 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
5338 /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
5339 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5340 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
5341 /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
5342 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5343 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
5344 /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
5345 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5346 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
5347 /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
5348 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
5349 /* .. .. reg_phy_bist_shift_dq = 0x0 */
5350 /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
5351 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
5352 /* .. .. reg_phy_bist_err_clr = 0x0 */
5353 /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
5354 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
5355 /* .. .. reg_phy_dq_offset = 0x40 */
5356 /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
5357 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
5358 /* .. .. */
5359 EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
5360 /* .. .. reg_phy_data_slice_in_use = 0x1 */
5361 /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
5362 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5363 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
5364 /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
5365 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5366 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
5367 /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
5368 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5369 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
5370 /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
5371 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5372 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
5373 /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
5374 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5375 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
5376 /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
5377 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
5378 /* .. .. reg_phy_bist_shift_dq = 0x0 */
5379 /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
5380 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
5381 /* .. .. reg_phy_bist_err_clr = 0x0 */
5382 /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
5383 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
5384 /* .. .. reg_phy_dq_offset = 0x40 */
5385 /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
5386 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
5387 /* .. .. */
5388 EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
5389 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
5390 /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
5391 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
5392 /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
5393 /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
5394 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
5395 /* .. .. */
5396 EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
5397 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
5398 /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
5399 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
5400 /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
5401 /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
5402 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
5403 /* .. .. */
5404 EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
5405 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
5406 /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
5407 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
5408 /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
5409 /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
5410 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
5411 /* .. .. */
5412 EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
5413 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
5414 /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
5415 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
5416 /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
5417 /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
5418 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
5419 /* .. .. */
5420 EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
5421 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
5422 /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
5423 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
5424 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
5425 /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
5426 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5427 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
5428 /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
5429 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5430 /* .. .. */
5431 EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
5432 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
5433 /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
5434 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
5435 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
5436 /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
5437 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5438 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
5439 /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
5440 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5441 /* .. .. */
5442 EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
5443 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
5444 /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
5445 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
5446 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
5447 /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
5448 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5449 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
5450 /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
5451 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5452 /* .. .. */
5453 EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
5454 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
5455 /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
5456 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
5457 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
5458 /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
5459 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5460 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
5461 /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
5462 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5463 /* .. .. */
5464 EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
5465 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
5466 /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
5467 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
5468 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
5469 /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
5470 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5471 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
5472 /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
5473 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5474 /* .. .. */
5475 EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
5476 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
5477 /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
5478 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
5479 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
5480 /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
5481 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5482 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
5483 /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
5484 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5485 /* .. .. */
5486 EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
5487 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
5488 /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
5489 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
5490 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
5491 /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
5492 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5493 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
5494 /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
5495 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5496 /* .. .. */
5497 EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
5498 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
5499 /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
5500 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
5501 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
5502 /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
5503 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5504 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
5505 /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
5506 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5507 /* .. .. */
5508 EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
5509 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
5510 /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
5511 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
5512 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
5513 /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
5514 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5515 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
5516 /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
5517 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
5518 /* .. .. */
5519 EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
5520 /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
5521 /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
5522 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
5523 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
5524 /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
5525 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5526 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
5527 /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
5528 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
5529 /* .. .. */
5530 EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
5531 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
5532 /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
5533 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
5534 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
5535 /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
5536 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5537 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
5538 /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
5539 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
5540 /* .. .. */
5541 EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
5542 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
5543 /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
5544 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
5545 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
5546 /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
5547 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5548 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
5549 /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
5550 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
5551 /* .. .. */
5552 EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
5553 /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
5554 /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
5555 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
5556 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
5557 /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
5558 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5559 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
5560 /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
5561 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5562 /* .. .. */
5563 EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
5564 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
5565 /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
5566 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
5567 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
5568 /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
5569 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5570 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
5571 /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
5572 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5573 /* .. .. */
5574 EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
5575 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
5576 /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
5577 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
5578 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
5579 /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
5580 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5581 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
5582 /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
5583 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5584 /* .. .. */
5585 EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
5586 /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
5587 /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
5588 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
5589 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
5590 /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
5591 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
5592 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
5593 /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
5594 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
5595 /* .. .. */
5596 EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
5597 /* .. .. reg_phy_loopback = 0x0 */
5598 /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
5599 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5600 /* .. .. reg_phy_bl2 = 0x0 */
5601 /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
5602 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5603 /* .. .. reg_phy_at_spd_atpg = 0x0 */
5604 /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
5605 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5606 /* .. .. reg_phy_bist_enable = 0x0 */
5607 /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
5608 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5609 /* .. .. reg_phy_bist_force_err = 0x0 */
5610 /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
5611 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5612 /* .. .. reg_phy_bist_mode = 0x0 */
5613 /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
5614 /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
5615 /* .. .. reg_phy_invert_clkout = 0x1 */
5616 /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
5617 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
5618 /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
5619 /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
5620 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
5621 /* .. .. reg_phy_sel_logic = 0x0 */
5622 /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
5623 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
5624 /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
5625 /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
5626 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
5627 /* .. .. reg_phy_ctrl_slave_force = 0x0 */
5628 /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
5629 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
5630 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
5631 /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
5632 /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
5633 /* .. .. reg_phy_use_rank0_delays = 0x1 */
5634 /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
5635 /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
5636 /* .. .. reg_phy_lpddr = 0x0 */
5637 /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
5638 /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
5639 /* .. .. reg_phy_cmd_latency = 0x0 */
5640 /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
5641 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
5642 /* .. .. reg_phy_int_lpbk = 0x0 */
5643 /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
5644 /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
5645 /* .. .. */
5646 EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
5647 /* .. .. reg_phy_wr_rl_delay = 0x2 */
5648 /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
5649 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
5650 /* .. .. reg_phy_rd_rl_delay = 0x4 */
5651 /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
5652 /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
5653 /* .. .. reg_phy_dll_lock_diff = 0xf */
5654 /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
5655 /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
5656 /* .. .. reg_phy_use_wr_level = 0x1 */
5657 /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
5658 /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
5659 /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
5660 /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
5661 /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
5662 /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
5663 /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
5664 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
5665 /* .. .. reg_phy_dis_calib_rst = 0x0 */
5666 /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
5667 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5668 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
5669 /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
5670 /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
5671 /* .. .. */
5672 EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
5673 /* .. .. reg_arb_page_addr_mask = 0x0 */
5674 /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
5675 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
5676 /* .. .. */
5677 EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
5678 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
5679 /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
5680 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5681 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
5682 /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
5683 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5684 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
5685 /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
5686 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5687 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
5688 /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
5689 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5690 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
5691 /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
5692 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
5693 /* .. .. */
5694 EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
5695 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
5696 /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
5697 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5698 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
5699 /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
5700 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5701 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
5702 /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
5703 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5704 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
5705 /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
5706 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5707 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
5708 /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
5709 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
5710 /* .. .. */
5711 EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
5712 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
5713 /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
5714 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5715 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
5716 /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
5717 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5718 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
5719 /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
5720 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5721 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
5722 /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
5723 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5724 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
5725 /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
5726 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
5727 /* .. .. */
5728 EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
5729 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
5730 /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
5731 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5732 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
5733 /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
5734 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5735 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
5736 /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
5737 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5738 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
5739 /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
5740 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5741 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
5742 /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
5743 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
5744 /* .. .. */
5745 EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
5746 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
5747 /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
5748 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5749 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
5750 /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
5751 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5752 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
5753 /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
5754 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5755 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
5756 /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
5757 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5758 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
5759 /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
5760 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
5761 /* .. .. */
5762 EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
5763 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
5764 /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
5765 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5766 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
5767 /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
5768 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5769 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
5770 /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
5771 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5772 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
5773 /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
5774 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5775 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
5776 /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
5777 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
5778 /* .. .. */
5779 EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
5780 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
5781 /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
5782 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5783 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
5784 /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
5785 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5786 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
5787 /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
5788 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5789 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
5790 /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
5791 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5792 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
5793 /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
5794 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
5795 /* .. .. */
5796 EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
5797 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
5798 /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
5799 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
5800 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
5801 /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
5802 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5803 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
5804 /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
5805 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
5806 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
5807 /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
5808 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
5809 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
5810 /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
5811 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
5812 /* .. .. */
5813 EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
5814 /* .. .. reg_ddrc_lpddr2 = 0x0 */
5815 /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
5816 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5817 /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
5818 /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
5819 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5820 /* .. .. reg_ddrc_derate_enable = 0x0 */
5821 /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
5822 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
5823 /* .. .. reg_ddrc_mr4_margin = 0x0 */
5824 /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
5825 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
5826 /* .. .. */
5827 EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
5828 /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
5829 /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
5830 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
5831 /* .. .. */
5832 EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
5833 /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
5834 /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
5835 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
5836 /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
5837 /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
5838 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
5839 /* .. .. reg_ddrc_t_mrw = 0x5 */
5840 /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
5841 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
5842 /* .. .. */
5843 EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
5844 /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
5845 /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
5846 /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
5847 /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
5848 /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
5849 /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
5850 /* .. .. */
5851 EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
5852 /* .. .. START: POLL ON DCI STATUS */
5853 /* .. .. DONE = 1 */
5854 /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
5855 /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
5856 /* .. .. */
5857 EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
5858 /* .. .. FINISH: POLL ON DCI STATUS */
5859 /* .. .. START: UNLOCK DDR */
5860 /* .. .. reg_ddrc_soft_rstb = 0x1 */
5861 /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
5862 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5863 /* .. .. reg_ddrc_powerdown_en = 0x0 */
5864 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
5865 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5866 /* .. .. reg_ddrc_data_bus_width = 0x0 */
5867 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
5868 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
5869 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
5870 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
5871 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
5872 /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
5873 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
5874 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
5875 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
5876 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
5877 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
5878 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
5879 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
5880 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
5881 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
5882 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
5883 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
5884 /* .. .. */
5885 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
5886 /* .. .. FINISH: UNLOCK DDR */
5887 /* .. .. START: CHECK DDR STATUS */
5888 /* .. .. ddrc_reg_operating_mode = 1 */
5889 /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
5890 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
5891 /* .. .. */
5892 EMIT_MASKPOLL(0XF8006054, 0x00000007U),
5893 /* .. .. FINISH: CHECK DDR STATUS */
5894 /* .. FINISH: DDR INITIALIZATION */
5895 /* FINISH: top */
5896 /* */
5897 EMIT_EXIT(),
5898
5899 /* */
5900 };
5901
5902 unsigned long ps7_mio_init_data_2_0[] = {
5903 /* START: top */
5904 /* .. START: SLCR SETTINGS */
5905 /* .. UNLOCK_KEY = 0XDF0D */
5906 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
5907 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
5908 /* .. */
5909 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
5910 /* .. FINISH: SLCR SETTINGS */
5911 /* .. START: OCM REMAPPING */
5912 /* .. VREF_EN = 0x1 */
5913 /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
5914 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
5915 /* .. VREF_PULLUP_EN = 0x0 */
5916 /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
5917 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
5918 /* .. CLK_PULLUP_EN = 0x0 */
5919 /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
5920 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
5921 /* .. SRSTN_PULLUP_EN = 0x0 */
5922 /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
5923 /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
5924 /* .. */
5925 EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
5926 /* .. FINISH: OCM REMAPPING */
5927 /* .. START: DDRIOB SETTINGS */
5928 /* .. INP_POWER = 0x0 */
5929 /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
5930 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5931 /* .. INP_TYPE = 0x0 */
5932 /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
5933 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
5934 /* .. DCI_UPDATE = 0x0 */
5935 /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
5936 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5937 /* .. TERM_EN = 0x0 */
5938 /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
5939 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5940 /* .. DCR_TYPE = 0x0 */
5941 /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
5942 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
5943 /* .. IBUF_DISABLE_MODE = 0x0 */
5944 /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
5945 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
5946 /* .. TERM_DISABLE_MODE = 0x0 */
5947 /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
5948 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
5949 /* .. OUTPUT_EN = 0x3 */
5950 /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
5951 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
5952 /* .. PULLUP_EN = 0x0 */
5953 /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
5954 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5955 /* .. */
5956 EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
5957 /* .. INP_POWER = 0x0 */
5958 /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
5959 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5960 /* .. INP_TYPE = 0x0 */
5961 /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
5962 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
5963 /* .. DCI_UPDATE = 0x0 */
5964 /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
5965 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5966 /* .. TERM_EN = 0x0 */
5967 /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
5968 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
5969 /* .. DCR_TYPE = 0x0 */
5970 /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
5971 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
5972 /* .. IBUF_DISABLE_MODE = 0x0 */
5973 /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
5974 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
5975 /* .. TERM_DISABLE_MODE = 0x0 */
5976 /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
5977 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
5978 /* .. OUTPUT_EN = 0x3 */
5979 /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
5980 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
5981 /* .. PULLUP_EN = 0x0 */
5982 /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
5983 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
5984 /* .. */
5985 EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
5986 /* .. INP_POWER = 0x0 */
5987 /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
5988 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
5989 /* .. INP_TYPE = 0x1 */
5990 /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
5991 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
5992 /* .. DCI_UPDATE = 0x0 */
5993 /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
5994 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
5995 /* .. TERM_EN = 0x1 */
5996 /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
5997 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
5998 /* .. DCR_TYPE = 0x3 */
5999 /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
6000 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
6001 /* .. IBUF_DISABLE_MODE = 0 */
6002 /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
6003 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
6004 /* .. TERM_DISABLE_MODE = 0 */
6005 /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
6006 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6007 /* .. OUTPUT_EN = 0x3 */
6008 /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
6009 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
6010 /* .. PULLUP_EN = 0x0 */
6011 /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
6012 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
6013 /* .. */
6014 EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
6015 /* .. INP_POWER = 0x0 */
6016 /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
6017 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6018 /* .. INP_TYPE = 0x1 */
6019 /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
6020 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
6021 /* .. DCI_UPDATE = 0x0 */
6022 /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
6023 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
6024 /* .. TERM_EN = 0x1 */
6025 /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
6026 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
6027 /* .. DCR_TYPE = 0x3 */
6028 /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
6029 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
6030 /* .. IBUF_DISABLE_MODE = 0 */
6031 /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
6032 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
6033 /* .. TERM_DISABLE_MODE = 0 */
6034 /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
6035 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6036 /* .. OUTPUT_EN = 0x3 */
6037 /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
6038 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
6039 /* .. PULLUP_EN = 0x0 */
6040 /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
6041 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
6042 /* .. */
6043 EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
6044 /* .. INP_POWER = 0x0 */
6045 /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
6046 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6047 /* .. INP_TYPE = 0x2 */
6048 /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
6049 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
6050 /* .. DCI_UPDATE = 0x0 */
6051 /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
6052 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
6053 /* .. TERM_EN = 0x1 */
6054 /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
6055 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
6056 /* .. DCR_TYPE = 0x3 */
6057 /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
6058 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
6059 /* .. IBUF_DISABLE_MODE = 0 */
6060 /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
6061 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
6062 /* .. TERM_DISABLE_MODE = 0 */
6063 /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
6064 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6065 /* .. OUTPUT_EN = 0x3 */
6066 /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
6067 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
6068 /* .. PULLUP_EN = 0x0 */
6069 /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
6070 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
6071 /* .. */
6072 EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
6073 /* .. INP_POWER = 0x0 */
6074 /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
6075 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6076 /* .. INP_TYPE = 0x2 */
6077 /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
6078 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
6079 /* .. DCI_UPDATE = 0x0 */
6080 /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
6081 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
6082 /* .. TERM_EN = 0x1 */
6083 /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
6084 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
6085 /* .. DCR_TYPE = 0x3 */
6086 /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
6087 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
6088 /* .. IBUF_DISABLE_MODE = 0 */
6089 /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
6090 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
6091 /* .. TERM_DISABLE_MODE = 0 */
6092 /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
6093 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6094 /* .. OUTPUT_EN = 0x3 */
6095 /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
6096 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
6097 /* .. PULLUP_EN = 0x0 */
6098 /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
6099 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
6100 /* .. */
6101 EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
6102 /* .. INP_POWER = 0x0 */
6103 /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
6104 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6105 /* .. INP_TYPE = 0x0 */
6106 /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
6107 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
6108 /* .. DCI_UPDATE = 0x0 */
6109 /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
6110 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
6111 /* .. TERM_EN = 0x0 */
6112 /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
6113 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
6114 /* .. DCR_TYPE = 0x0 */
6115 /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
6116 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
6117 /* .. IBUF_DISABLE_MODE = 0x0 */
6118 /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
6119 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
6120 /* .. TERM_DISABLE_MODE = 0x0 */
6121 /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
6122 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6123 /* .. OUTPUT_EN = 0x3 */
6124 /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
6125 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
6126 /* .. PULLUP_EN = 0x0 */
6127 /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
6128 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
6129 /* .. */
6130 EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
6131 /* .. DRIVE_P = 0x1c */
6132 /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
6133 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
6134 /* .. DRIVE_N = 0xc */
6135 /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
6136 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
6137 /* .. SLEW_P = 0x3 */
6138 /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
6139 /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
6140 /* .. SLEW_N = 0x3 */
6141 /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
6142 /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
6143 /* .. GTL = 0x0 */
6144 /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
6145 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
6146 /* .. RTERM = 0x0 */
6147 /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
6148 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
6149 /* .. */
6150 EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
6151 /* .. DRIVE_P = 0x1c */
6152 /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
6153 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
6154 /* .. DRIVE_N = 0xc */
6155 /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
6156 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
6157 /* .. SLEW_P = 0x6 */
6158 /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
6159 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
6160 /* .. SLEW_N = 0x1f */
6161 /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
6162 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
6163 /* .. GTL = 0x0 */
6164 /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
6165 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
6166 /* .. RTERM = 0x0 */
6167 /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
6168 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
6169 /* .. */
6170 EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
6171 /* .. DRIVE_P = 0x1c */
6172 /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
6173 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
6174 /* .. DRIVE_N = 0xc */
6175 /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
6176 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
6177 /* .. SLEW_P = 0x6 */
6178 /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
6179 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
6180 /* .. SLEW_N = 0x1f */
6181 /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
6182 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
6183 /* .. GTL = 0x0 */
6184 /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
6185 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
6186 /* .. RTERM = 0x0 */
6187 /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
6188 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
6189 /* .. */
6190 EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
6191 /* .. DRIVE_P = 0x1c */
6192 /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
6193 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
6194 /* .. DRIVE_N = 0xc */
6195 /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
6196 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
6197 /* .. SLEW_P = 0x6 */
6198 /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
6199 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
6200 /* .. SLEW_N = 0x1f */
6201 /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
6202 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
6203 /* .. GTL = 0x0 */
6204 /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
6205 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
6206 /* .. RTERM = 0x0 */
6207 /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
6208 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
6209 /* .. */
6210 EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
6211 /* .. VREF_INT_EN = 0x0 */
6212 /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
6213 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6214 /* .. VREF_SEL = 0x0 */
6215 /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
6216 /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
6217 /* .. VREF_EXT_EN = 0x3 */
6218 /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
6219 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
6220 /* .. VREF_PULLUP_EN = 0x0 */
6221 /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
6222 /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
6223 /* .. REFIO_EN = 0x1 */
6224 /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
6225 /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
6226 /* .. REFIO_TEST = 0x0 */
6227 /* .. ==> 0XF8000B6C[11:10] = 0x00000000U */
6228 /* .. ==> MASK : 0x00000C00U VAL : 0x00000000U */
6229 /* .. REFIO_PULLUP_EN = 0x0 */
6230 /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
6231 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6232 /* .. DRST_B_PULLUP_EN = 0x0 */
6233 /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
6234 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6235 /* .. CKE_PULLUP_EN = 0x0 */
6236 /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
6237 /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
6238 /* .. */
6239 EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
6240 /* .. .. START: ASSERT RESET */
6241 /* .. .. RESET = 1 */
6242 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
6243 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
6244 /* .. .. VRN_OUT = 0x1 */
6245 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
6246 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
6247 /* .. .. */
6248 EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
6249 /* .. .. FINISH: ASSERT RESET */
6250 /* .. .. START: DEASSERT RESET */
6251 /* .. .. RESET = 0 */
6252 /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
6253 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6254 /* .. .. VRN_OUT = 0x1 */
6255 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
6256 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
6257 /* .. .. */
6258 EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
6259 /* .. .. FINISH: DEASSERT RESET */
6260 /* .. .. RESET = 0x1 */
6261 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
6262 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
6263 /* .. .. ENABLE = 0x1 */
6264 /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
6265 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6266 /* .. .. VRP_TRI = 0x0 */
6267 /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
6268 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6269 /* .. .. VRN_TRI = 0x0 */
6270 /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
6271 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
6272 /* .. .. VRP_OUT = 0x0 */
6273 /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
6274 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
6275 /* .. .. VRN_OUT = 0x1 */
6276 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
6277 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
6278 /* .. .. NREF_OPT1 = 0x0 */
6279 /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
6280 /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
6281 /* .. .. NREF_OPT2 = 0x0 */
6282 /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
6283 /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
6284 /* .. .. NREF_OPT4 = 0x1 */
6285 /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
6286 /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
6287 /* .. .. PREF_OPT1 = 0x0 */
6288 /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
6289 /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
6290 /* .. .. PREF_OPT2 = 0x0 */
6291 /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
6292 /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
6293 /* .. .. UPDATE_CONTROL = 0x0 */
6294 /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
6295 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
6296 /* .. .. INIT_COMPLETE = 0x0 */
6297 /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
6298 /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
6299 /* .. .. TST_CLK = 0x0 */
6300 /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
6301 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
6302 /* .. .. TST_HLN = 0x0 */
6303 /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
6304 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
6305 /* .. .. TST_HLP = 0x0 */
6306 /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
6307 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
6308 /* .. .. TST_RST = 0x0 */
6309 /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
6310 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
6311 /* .. .. INT_DCI_EN = 0x0 */
6312 /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
6313 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
6314 /* .. .. */
6315 EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
6316 /* .. FINISH: DDRIOB SETTINGS */
6317 /* .. START: MIO PROGRAMMING */
6318 /* .. TRI_ENABLE = 0 */
6319 /* .. ==> 0XF8000700[0:0] = 0x00000000U */
6320 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6321 /* .. L0_SEL = 0 */
6322 /* .. ==> 0XF8000700[1:1] = 0x00000000U */
6323 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6324 /* .. L1_SEL = 0 */
6325 /* .. ==> 0XF8000700[2:2] = 0x00000000U */
6326 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6327 /* .. L2_SEL = 0 */
6328 /* .. ==> 0XF8000700[4:3] = 0x00000000U */
6329 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6330 /* .. L3_SEL = 0 */
6331 /* .. ==> 0XF8000700[7:5] = 0x00000000U */
6332 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6333 /* .. Speed = 0 */
6334 /* .. ==> 0XF8000700[8:8] = 0x00000000U */
6335 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6336 /* .. IO_Type = 3 */
6337 /* .. ==> 0XF8000700[11:9] = 0x00000003U */
6338 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6339 /* .. PULLUP = 1 */
6340 /* .. ==> 0XF8000700[12:12] = 0x00000001U */
6341 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6342 /* .. DisableRcvr = 0 */
6343 /* .. ==> 0XF8000700[13:13] = 0x00000000U */
6344 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6345 /* .. */
6346 EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
6347 /* .. TRI_ENABLE = 0 */
6348 /* .. ==> 0XF8000704[0:0] = 0x00000000U */
6349 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6350 /* .. L0_SEL = 1 */
6351 /* .. ==> 0XF8000704[1:1] = 0x00000001U */
6352 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6353 /* .. L1_SEL = 0 */
6354 /* .. ==> 0XF8000704[2:2] = 0x00000000U */
6355 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6356 /* .. L2_SEL = 0 */
6357 /* .. ==> 0XF8000704[4:3] = 0x00000000U */
6358 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6359 /* .. L3_SEL = 0 */
6360 /* .. ==> 0XF8000704[7:5] = 0x00000000U */
6361 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6362 /* .. Speed = 1 */
6363 /* .. ==> 0XF8000704[8:8] = 0x00000001U */
6364 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6365 /* .. IO_Type = 3 */
6366 /* .. ==> 0XF8000704[11:9] = 0x00000003U */
6367 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6368 /* .. PULLUP = 0 */
6369 /* .. ==> 0XF8000704[12:12] = 0x00000000U */
6370 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6371 /* .. DisableRcvr = 0 */
6372 /* .. ==> 0XF8000704[13:13] = 0x00000000U */
6373 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6374 /* .. */
6375 EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
6376 /* .. TRI_ENABLE = 0 */
6377 /* .. ==> 0XF8000708[0:0] = 0x00000000U */
6378 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6379 /* .. L0_SEL = 1 */
6380 /* .. ==> 0XF8000708[1:1] = 0x00000001U */
6381 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6382 /* .. L1_SEL = 0 */
6383 /* .. ==> 0XF8000708[2:2] = 0x00000000U */
6384 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6385 /* .. L2_SEL = 0 */
6386 /* .. ==> 0XF8000708[4:3] = 0x00000000U */
6387 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6388 /* .. L3_SEL = 0 */
6389 /* .. ==> 0XF8000708[7:5] = 0x00000000U */
6390 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6391 /* .. Speed = 1 */
6392 /* .. ==> 0XF8000708[8:8] = 0x00000001U */
6393 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6394 /* .. IO_Type = 3 */
6395 /* .. ==> 0XF8000708[11:9] = 0x00000003U */
6396 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6397 /* .. PULLUP = 0 */
6398 /* .. ==> 0XF8000708[12:12] = 0x00000000U */
6399 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6400 /* .. DisableRcvr = 0 */
6401 /* .. ==> 0XF8000708[13:13] = 0x00000000U */
6402 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6403 /* .. */
6404 EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
6405 /* .. TRI_ENABLE = 0 */
6406 /* .. ==> 0XF800070C[0:0] = 0x00000000U */
6407 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6408 /* .. L0_SEL = 1 */
6409 /* .. ==> 0XF800070C[1:1] = 0x00000001U */
6410 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6411 /* .. L1_SEL = 0 */
6412 /* .. ==> 0XF800070C[2:2] = 0x00000000U */
6413 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6414 /* .. L2_SEL = 0 */
6415 /* .. ==> 0XF800070C[4:3] = 0x00000000U */
6416 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6417 /* .. L3_SEL = 0 */
6418 /* .. ==> 0XF800070C[7:5] = 0x00000000U */
6419 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6420 /* .. Speed = 1 */
6421 /* .. ==> 0XF800070C[8:8] = 0x00000001U */
6422 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6423 /* .. IO_Type = 3 */
6424 /* .. ==> 0XF800070C[11:9] = 0x00000003U */
6425 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6426 /* .. PULLUP = 0 */
6427 /* .. ==> 0XF800070C[12:12] = 0x00000000U */
6428 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6429 /* .. DisableRcvr = 0 */
6430 /* .. ==> 0XF800070C[13:13] = 0x00000000U */
6431 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6432 /* .. */
6433 EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
6434 /* .. TRI_ENABLE = 0 */
6435 /* .. ==> 0XF8000710[0:0] = 0x00000000U */
6436 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6437 /* .. L0_SEL = 1 */
6438 /* .. ==> 0XF8000710[1:1] = 0x00000001U */
6439 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6440 /* .. L1_SEL = 0 */
6441 /* .. ==> 0XF8000710[2:2] = 0x00000000U */
6442 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6443 /* .. L2_SEL = 0 */
6444 /* .. ==> 0XF8000710[4:3] = 0x00000000U */
6445 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6446 /* .. L3_SEL = 0 */
6447 /* .. ==> 0XF8000710[7:5] = 0x00000000U */
6448 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6449 /* .. Speed = 1 */
6450 /* .. ==> 0XF8000710[8:8] = 0x00000001U */
6451 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6452 /* .. IO_Type = 3 */
6453 /* .. ==> 0XF8000710[11:9] = 0x00000003U */
6454 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6455 /* .. PULLUP = 0 */
6456 /* .. ==> 0XF8000710[12:12] = 0x00000000U */
6457 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6458 /* .. DisableRcvr = 0 */
6459 /* .. ==> 0XF8000710[13:13] = 0x00000000U */
6460 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6461 /* .. */
6462 EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
6463 /* .. TRI_ENABLE = 0 */
6464 /* .. ==> 0XF8000714[0:0] = 0x00000000U */
6465 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6466 /* .. L0_SEL = 1 */
6467 /* .. ==> 0XF8000714[1:1] = 0x00000001U */
6468 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6469 /* .. L1_SEL = 0 */
6470 /* .. ==> 0XF8000714[2:2] = 0x00000000U */
6471 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6472 /* .. L2_SEL = 0 */
6473 /* .. ==> 0XF8000714[4:3] = 0x00000000U */
6474 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6475 /* .. L3_SEL = 0 */
6476 /* .. ==> 0XF8000714[7:5] = 0x00000000U */
6477 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6478 /* .. Speed = 1 */
6479 /* .. ==> 0XF8000714[8:8] = 0x00000001U */
6480 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6481 /* .. IO_Type = 3 */
6482 /* .. ==> 0XF8000714[11:9] = 0x00000003U */
6483 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6484 /* .. PULLUP = 0 */
6485 /* .. ==> 0XF8000714[12:12] = 0x00000000U */
6486 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6487 /* .. DisableRcvr = 0 */
6488 /* .. ==> 0XF8000714[13:13] = 0x00000000U */
6489 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6490 /* .. */
6491 EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
6492 /* .. TRI_ENABLE = 0 */
6493 /* .. ==> 0XF8000718[0:0] = 0x00000000U */
6494 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6495 /* .. L0_SEL = 1 */
6496 /* .. ==> 0XF8000718[1:1] = 0x00000001U */
6497 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6498 /* .. L1_SEL = 0 */
6499 /* .. ==> 0XF8000718[2:2] = 0x00000000U */
6500 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6501 /* .. L2_SEL = 0 */
6502 /* .. ==> 0XF8000718[4:3] = 0x00000000U */
6503 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6504 /* .. L3_SEL = 0 */
6505 /* .. ==> 0XF8000718[7:5] = 0x00000000U */
6506 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6507 /* .. Speed = 1 */
6508 /* .. ==> 0XF8000718[8:8] = 0x00000001U */
6509 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6510 /* .. IO_Type = 3 */
6511 /* .. ==> 0XF8000718[11:9] = 0x00000003U */
6512 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6513 /* .. PULLUP = 0 */
6514 /* .. ==> 0XF8000718[12:12] = 0x00000000U */
6515 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6516 /* .. DisableRcvr = 0 */
6517 /* .. ==> 0XF8000718[13:13] = 0x00000000U */
6518 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6519 /* .. */
6520 EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
6521 /* .. TRI_ENABLE = 0 */
6522 /* .. ==> 0XF800071C[0:0] = 0x00000000U */
6523 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6524 /* .. L0_SEL = 0 */
6525 /* .. ==> 0XF800071C[1:1] = 0x00000000U */
6526 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6527 /* .. L1_SEL = 0 */
6528 /* .. ==> 0XF800071C[2:2] = 0x00000000U */
6529 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6530 /* .. L2_SEL = 0 */
6531 /* .. ==> 0XF800071C[4:3] = 0x00000000U */
6532 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6533 /* .. L3_SEL = 0 */
6534 /* .. ==> 0XF800071C[7:5] = 0x00000000U */
6535 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6536 /* .. Speed = 0 */
6537 /* .. ==> 0XF800071C[8:8] = 0x00000000U */
6538 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6539 /* .. IO_Type = 3 */
6540 /* .. ==> 0XF800071C[11:9] = 0x00000003U */
6541 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6542 /* .. PULLUP = 0 */
6543 /* .. ==> 0XF800071C[12:12] = 0x00000000U */
6544 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6545 /* .. DisableRcvr = 0 */
6546 /* .. ==> 0XF800071C[13:13] = 0x00000000U */
6547 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6548 /* .. */
6549 EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
6550 /* .. TRI_ENABLE = 0 */
6551 /* .. ==> 0XF8000720[0:0] = 0x00000000U */
6552 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6553 /* .. L0_SEL = 1 */
6554 /* .. ==> 0XF8000720[1:1] = 0x00000001U */
6555 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6556 /* .. L1_SEL = 0 */
6557 /* .. ==> 0XF8000720[2:2] = 0x00000000U */
6558 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6559 /* .. L2_SEL = 0 */
6560 /* .. ==> 0XF8000720[4:3] = 0x00000000U */
6561 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6562 /* .. L3_SEL = 0 */
6563 /* .. ==> 0XF8000720[7:5] = 0x00000000U */
6564 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6565 /* .. Speed = 1 */
6566 /* .. ==> 0XF8000720[8:8] = 0x00000001U */
6567 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6568 /* .. IO_Type = 3 */
6569 /* .. ==> 0XF8000720[11:9] = 0x00000003U */
6570 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6571 /* .. PULLUP = 0 */
6572 /* .. ==> 0XF8000720[12:12] = 0x00000000U */
6573 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6574 /* .. DisableRcvr = 0 */
6575 /* .. ==> 0XF8000720[13:13] = 0x00000000U */
6576 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6577 /* .. */
6578 EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
6579 /* .. TRI_ENABLE = 0 */
6580 /* .. ==> 0XF8000724[0:0] = 0x00000000U */
6581 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6582 /* .. L0_SEL = 0 */
6583 /* .. ==> 0XF8000724[1:1] = 0x00000000U */
6584 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6585 /* .. L1_SEL = 0 */
6586 /* .. ==> 0XF8000724[2:2] = 0x00000000U */
6587 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6588 /* .. L2_SEL = 0 */
6589 /* .. ==> 0XF8000724[4:3] = 0x00000000U */
6590 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6591 /* .. L3_SEL = 0 */
6592 /* .. ==> 0XF8000724[7:5] = 0x00000000U */
6593 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6594 /* .. Speed = 0 */
6595 /* .. ==> 0XF8000724[8:8] = 0x00000000U */
6596 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6597 /* .. IO_Type = 3 */
6598 /* .. ==> 0XF8000724[11:9] = 0x00000003U */
6599 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6600 /* .. PULLUP = 1 */
6601 /* .. ==> 0XF8000724[12:12] = 0x00000001U */
6602 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6603 /* .. DisableRcvr = 0 */
6604 /* .. ==> 0XF8000724[13:13] = 0x00000000U */
6605 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6606 /* .. */
6607 EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
6608 /* .. TRI_ENABLE = 0 */
6609 /* .. ==> 0XF8000728[0:0] = 0x00000000U */
6610 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6611 /* .. L0_SEL = 0 */
6612 /* .. ==> 0XF8000728[1:1] = 0x00000000U */
6613 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6614 /* .. L1_SEL = 0 */
6615 /* .. ==> 0XF8000728[2:2] = 0x00000000U */
6616 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6617 /* .. L2_SEL = 0 */
6618 /* .. ==> 0XF8000728[4:3] = 0x00000000U */
6619 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6620 /* .. L3_SEL = 0 */
6621 /* .. ==> 0XF8000728[7:5] = 0x00000000U */
6622 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6623 /* .. Speed = 0 */
6624 /* .. ==> 0XF8000728[8:8] = 0x00000000U */
6625 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6626 /* .. IO_Type = 3 */
6627 /* .. ==> 0XF8000728[11:9] = 0x00000003U */
6628 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6629 /* .. PULLUP = 1 */
6630 /* .. ==> 0XF8000728[12:12] = 0x00000001U */
6631 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6632 /* .. DisableRcvr = 0 */
6633 /* .. ==> 0XF8000728[13:13] = 0x00000000U */
6634 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6635 /* .. */
6636 EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
6637 /* .. TRI_ENABLE = 0 */
6638 /* .. ==> 0XF800072C[0:0] = 0x00000000U */
6639 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6640 /* .. L0_SEL = 0 */
6641 /* .. ==> 0XF800072C[1:1] = 0x00000000U */
6642 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6643 /* .. L1_SEL = 0 */
6644 /* .. ==> 0XF800072C[2:2] = 0x00000000U */
6645 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6646 /* .. L2_SEL = 0 */
6647 /* .. ==> 0XF800072C[4:3] = 0x00000000U */
6648 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6649 /* .. L3_SEL = 0 */
6650 /* .. ==> 0XF800072C[7:5] = 0x00000000U */
6651 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6652 /* .. Speed = 0 */
6653 /* .. ==> 0XF800072C[8:8] = 0x00000000U */
6654 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6655 /* .. IO_Type = 3 */
6656 /* .. ==> 0XF800072C[11:9] = 0x00000003U */
6657 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6658 /* .. PULLUP = 1 */
6659 /* .. ==> 0XF800072C[12:12] = 0x00000001U */
6660 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6661 /* .. DisableRcvr = 0 */
6662 /* .. ==> 0XF800072C[13:13] = 0x00000000U */
6663 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6664 /* .. */
6665 EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
6666 /* .. TRI_ENABLE = 0 */
6667 /* .. ==> 0XF8000730[0:0] = 0x00000000U */
6668 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6669 /* .. L0_SEL = 0 */
6670 /* .. ==> 0XF8000730[1:1] = 0x00000000U */
6671 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6672 /* .. L1_SEL = 0 */
6673 /* .. ==> 0XF8000730[2:2] = 0x00000000U */
6674 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6675 /* .. L2_SEL = 0 */
6676 /* .. ==> 0XF8000730[4:3] = 0x00000000U */
6677 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6678 /* .. L3_SEL = 0 */
6679 /* .. ==> 0XF8000730[7:5] = 0x00000000U */
6680 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6681 /* .. Speed = 0 */
6682 /* .. ==> 0XF8000730[8:8] = 0x00000000U */
6683 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6684 /* .. IO_Type = 3 */
6685 /* .. ==> 0XF8000730[11:9] = 0x00000003U */
6686 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6687 /* .. PULLUP = 1 */
6688 /* .. ==> 0XF8000730[12:12] = 0x00000001U */
6689 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6690 /* .. DisableRcvr = 0 */
6691 /* .. ==> 0XF8000730[13:13] = 0x00000000U */
6692 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6693 /* .. */
6694 EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
6695 /* .. TRI_ENABLE = 0 */
6696 /* .. ==> 0XF8000734[0:0] = 0x00000000U */
6697 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6698 /* .. L0_SEL = 0 */
6699 /* .. ==> 0XF8000734[1:1] = 0x00000000U */
6700 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6701 /* .. L1_SEL = 0 */
6702 /* .. ==> 0XF8000734[2:2] = 0x00000000U */
6703 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6704 /* .. L2_SEL = 0 */
6705 /* .. ==> 0XF8000734[4:3] = 0x00000000U */
6706 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6707 /* .. L3_SEL = 0 */
6708 /* .. ==> 0XF8000734[7:5] = 0x00000000U */
6709 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6710 /* .. Speed = 0 */
6711 /* .. ==> 0XF8000734[8:8] = 0x00000000U */
6712 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6713 /* .. IO_Type = 3 */
6714 /* .. ==> 0XF8000734[11:9] = 0x00000003U */
6715 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6716 /* .. PULLUP = 1 */
6717 /* .. ==> 0XF8000734[12:12] = 0x00000001U */
6718 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6719 /* .. DisableRcvr = 0 */
6720 /* .. ==> 0XF8000734[13:13] = 0x00000000U */
6721 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6722 /* .. */
6723 EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
6724 /* .. TRI_ENABLE = 0 */
6725 /* .. ==> 0XF8000738[0:0] = 0x00000000U */
6726 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6727 /* .. L0_SEL = 0 */
6728 /* .. ==> 0XF8000738[1:1] = 0x00000000U */
6729 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6730 /* .. L1_SEL = 0 */
6731 /* .. ==> 0XF8000738[2:2] = 0x00000000U */
6732 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6733 /* .. L2_SEL = 0 */
6734 /* .. ==> 0XF8000738[4:3] = 0x00000000U */
6735 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6736 /* .. L3_SEL = 0 */
6737 /* .. ==> 0XF8000738[7:5] = 0x00000000U */
6738 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6739 /* .. Speed = 0 */
6740 /* .. ==> 0XF8000738[8:8] = 0x00000000U */
6741 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6742 /* .. IO_Type = 3 */
6743 /* .. ==> 0XF8000738[11:9] = 0x00000003U */
6744 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6745 /* .. PULLUP = 1 */
6746 /* .. ==> 0XF8000738[12:12] = 0x00000001U */
6747 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6748 /* .. DisableRcvr = 0 */
6749 /* .. ==> 0XF8000738[13:13] = 0x00000000U */
6750 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6751 /* .. */
6752 EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
6753 /* .. TRI_ENABLE = 0 */
6754 /* .. ==> 0XF800073C[0:0] = 0x00000000U */
6755 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6756 /* .. L0_SEL = 0 */
6757 /* .. ==> 0XF800073C[1:1] = 0x00000000U */
6758 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
6759 /* .. L1_SEL = 0 */
6760 /* .. ==> 0XF800073C[2:2] = 0x00000000U */
6761 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6762 /* .. L2_SEL = 0 */
6763 /* .. ==> 0XF800073C[4:3] = 0x00000000U */
6764 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6765 /* .. L3_SEL = 0 */
6766 /* .. ==> 0XF800073C[7:5] = 0x00000000U */
6767 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6768 /* .. Speed = 0 */
6769 /* .. ==> 0XF800073C[8:8] = 0x00000000U */
6770 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
6771 /* .. IO_Type = 3 */
6772 /* .. ==> 0XF800073C[11:9] = 0x00000003U */
6773 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
6774 /* .. PULLUP = 1 */
6775 /* .. ==> 0XF800073C[12:12] = 0x00000001U */
6776 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
6777 /* .. DisableRcvr = 0 */
6778 /* .. ==> 0XF800073C[13:13] = 0x00000000U */
6779 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6780 /* .. */
6781 EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
6782 /* .. TRI_ENABLE = 0 */
6783 /* .. ==> 0XF8000740[0:0] = 0x00000000U */
6784 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6785 /* .. L0_SEL = 1 */
6786 /* .. ==> 0XF8000740[1:1] = 0x00000001U */
6787 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6788 /* .. L1_SEL = 0 */
6789 /* .. ==> 0XF8000740[2:2] = 0x00000000U */
6790 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6791 /* .. L2_SEL = 0 */
6792 /* .. ==> 0XF8000740[4:3] = 0x00000000U */
6793 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6794 /* .. L3_SEL = 0 */
6795 /* .. ==> 0XF8000740[7:5] = 0x00000000U */
6796 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6797 /* .. Speed = 1 */
6798 /* .. ==> 0XF8000740[8:8] = 0x00000001U */
6799 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6800 /* .. IO_Type = 4 */
6801 /* .. ==> 0XF8000740[11:9] = 0x00000004U */
6802 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6803 /* .. PULLUP = 0 */
6804 /* .. ==> 0XF8000740[12:12] = 0x00000000U */
6805 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6806 /* .. DisableRcvr = 1 */
6807 /* .. ==> 0XF8000740[13:13] = 0x00000001U */
6808 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6809 /* .. */
6810 EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
6811 /* .. TRI_ENABLE = 0 */
6812 /* .. ==> 0XF8000744[0:0] = 0x00000000U */
6813 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6814 /* .. L0_SEL = 1 */
6815 /* .. ==> 0XF8000744[1:1] = 0x00000001U */
6816 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6817 /* .. L1_SEL = 0 */
6818 /* .. ==> 0XF8000744[2:2] = 0x00000000U */
6819 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6820 /* .. L2_SEL = 0 */
6821 /* .. ==> 0XF8000744[4:3] = 0x00000000U */
6822 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6823 /* .. L3_SEL = 0 */
6824 /* .. ==> 0XF8000744[7:5] = 0x00000000U */
6825 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6826 /* .. Speed = 1 */
6827 /* .. ==> 0XF8000744[8:8] = 0x00000001U */
6828 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6829 /* .. IO_Type = 4 */
6830 /* .. ==> 0XF8000744[11:9] = 0x00000004U */
6831 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6832 /* .. PULLUP = 0 */
6833 /* .. ==> 0XF8000744[12:12] = 0x00000000U */
6834 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6835 /* .. DisableRcvr = 1 */
6836 /* .. ==> 0XF8000744[13:13] = 0x00000001U */
6837 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6838 /* .. */
6839 EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
6840 /* .. TRI_ENABLE = 0 */
6841 /* .. ==> 0XF8000748[0:0] = 0x00000000U */
6842 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6843 /* .. L0_SEL = 1 */
6844 /* .. ==> 0XF8000748[1:1] = 0x00000001U */
6845 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6846 /* .. L1_SEL = 0 */
6847 /* .. ==> 0XF8000748[2:2] = 0x00000000U */
6848 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6849 /* .. L2_SEL = 0 */
6850 /* .. ==> 0XF8000748[4:3] = 0x00000000U */
6851 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6852 /* .. L3_SEL = 0 */
6853 /* .. ==> 0XF8000748[7:5] = 0x00000000U */
6854 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6855 /* .. Speed = 1 */
6856 /* .. ==> 0XF8000748[8:8] = 0x00000001U */
6857 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6858 /* .. IO_Type = 4 */
6859 /* .. ==> 0XF8000748[11:9] = 0x00000004U */
6860 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6861 /* .. PULLUP = 0 */
6862 /* .. ==> 0XF8000748[12:12] = 0x00000000U */
6863 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6864 /* .. DisableRcvr = 1 */
6865 /* .. ==> 0XF8000748[13:13] = 0x00000001U */
6866 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6867 /* .. */
6868 EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
6869 /* .. TRI_ENABLE = 0 */
6870 /* .. ==> 0XF800074C[0:0] = 0x00000000U */
6871 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6872 /* .. L0_SEL = 1 */
6873 /* .. ==> 0XF800074C[1:1] = 0x00000001U */
6874 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6875 /* .. L1_SEL = 0 */
6876 /* .. ==> 0XF800074C[2:2] = 0x00000000U */
6877 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6878 /* .. L2_SEL = 0 */
6879 /* .. ==> 0XF800074C[4:3] = 0x00000000U */
6880 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6881 /* .. L3_SEL = 0 */
6882 /* .. ==> 0XF800074C[7:5] = 0x00000000U */
6883 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6884 /* .. Speed = 1 */
6885 /* .. ==> 0XF800074C[8:8] = 0x00000001U */
6886 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6887 /* .. IO_Type = 4 */
6888 /* .. ==> 0XF800074C[11:9] = 0x00000004U */
6889 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6890 /* .. PULLUP = 0 */
6891 /* .. ==> 0XF800074C[12:12] = 0x00000000U */
6892 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6893 /* .. DisableRcvr = 1 */
6894 /* .. ==> 0XF800074C[13:13] = 0x00000001U */
6895 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6896 /* .. */
6897 EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
6898 /* .. TRI_ENABLE = 0 */
6899 /* .. ==> 0XF8000750[0:0] = 0x00000000U */
6900 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6901 /* .. L0_SEL = 1 */
6902 /* .. ==> 0XF8000750[1:1] = 0x00000001U */
6903 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6904 /* .. L1_SEL = 0 */
6905 /* .. ==> 0XF8000750[2:2] = 0x00000000U */
6906 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6907 /* .. L2_SEL = 0 */
6908 /* .. ==> 0XF8000750[4:3] = 0x00000000U */
6909 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6910 /* .. L3_SEL = 0 */
6911 /* .. ==> 0XF8000750[7:5] = 0x00000000U */
6912 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6913 /* .. Speed = 1 */
6914 /* .. ==> 0XF8000750[8:8] = 0x00000001U */
6915 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6916 /* .. IO_Type = 4 */
6917 /* .. ==> 0XF8000750[11:9] = 0x00000004U */
6918 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6919 /* .. PULLUP = 0 */
6920 /* .. ==> 0XF8000750[12:12] = 0x00000000U */
6921 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6922 /* .. DisableRcvr = 1 */
6923 /* .. ==> 0XF8000750[13:13] = 0x00000001U */
6924 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6925 /* .. */
6926 EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
6927 /* .. TRI_ENABLE = 0 */
6928 /* .. ==> 0XF8000754[0:0] = 0x00000000U */
6929 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
6930 /* .. L0_SEL = 1 */
6931 /* .. ==> 0XF8000754[1:1] = 0x00000001U */
6932 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6933 /* .. L1_SEL = 0 */
6934 /* .. ==> 0XF8000754[2:2] = 0x00000000U */
6935 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6936 /* .. L2_SEL = 0 */
6937 /* .. ==> 0XF8000754[4:3] = 0x00000000U */
6938 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6939 /* .. L3_SEL = 0 */
6940 /* .. ==> 0XF8000754[7:5] = 0x00000000U */
6941 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6942 /* .. Speed = 1 */
6943 /* .. ==> 0XF8000754[8:8] = 0x00000001U */
6944 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6945 /* .. IO_Type = 4 */
6946 /* .. ==> 0XF8000754[11:9] = 0x00000004U */
6947 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6948 /* .. PULLUP = 0 */
6949 /* .. ==> 0XF8000754[12:12] = 0x00000000U */
6950 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6951 /* .. DisableRcvr = 1 */
6952 /* .. ==> 0XF8000754[13:13] = 0x00000001U */
6953 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
6954 /* .. */
6955 EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
6956 /* .. TRI_ENABLE = 1 */
6957 /* .. ==> 0XF8000758[0:0] = 0x00000001U */
6958 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
6959 /* .. L0_SEL = 1 */
6960 /* .. ==> 0XF8000758[1:1] = 0x00000001U */
6961 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6962 /* .. L1_SEL = 0 */
6963 /* .. ==> 0XF8000758[2:2] = 0x00000000U */
6964 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6965 /* .. L2_SEL = 0 */
6966 /* .. ==> 0XF8000758[4:3] = 0x00000000U */
6967 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6968 /* .. L3_SEL = 0 */
6969 /* .. ==> 0XF8000758[7:5] = 0x00000000U */
6970 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
6971 /* .. Speed = 1 */
6972 /* .. ==> 0XF8000758[8:8] = 0x00000001U */
6973 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
6974 /* .. IO_Type = 4 */
6975 /* .. ==> 0XF8000758[11:9] = 0x00000004U */
6976 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
6977 /* .. PULLUP = 0 */
6978 /* .. ==> 0XF8000758[12:12] = 0x00000000U */
6979 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
6980 /* .. DisableRcvr = 0 */
6981 /* .. ==> 0XF8000758[13:13] = 0x00000000U */
6982 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
6983 /* .. */
6984 EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
6985 /* .. TRI_ENABLE = 1 */
6986 /* .. ==> 0XF800075C[0:0] = 0x00000001U */
6987 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
6988 /* .. L0_SEL = 1 */
6989 /* .. ==> 0XF800075C[1:1] = 0x00000001U */
6990 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
6991 /* .. L1_SEL = 0 */
6992 /* .. ==> 0XF800075C[2:2] = 0x00000000U */
6993 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
6994 /* .. L2_SEL = 0 */
6995 /* .. ==> 0XF800075C[4:3] = 0x00000000U */
6996 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
6997 /* .. L3_SEL = 0 */
6998 /* .. ==> 0XF800075C[7:5] = 0x00000000U */
6999 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7000 /* .. Speed = 1 */
7001 /* .. ==> 0XF800075C[8:8] = 0x00000001U */
7002 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7003 /* .. IO_Type = 4 */
7004 /* .. ==> 0XF800075C[11:9] = 0x00000004U */
7005 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
7006 /* .. PULLUP = 0 */
7007 /* .. ==> 0XF800075C[12:12] = 0x00000000U */
7008 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7009 /* .. DisableRcvr = 0 */
7010 /* .. ==> 0XF800075C[13:13] = 0x00000000U */
7011 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7012 /* .. */
7013 EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
7014 /* .. TRI_ENABLE = 1 */
7015 /* .. ==> 0XF8000760[0:0] = 0x00000001U */
7016 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7017 /* .. L0_SEL = 1 */
7018 /* .. ==> 0XF8000760[1:1] = 0x00000001U */
7019 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
7020 /* .. L1_SEL = 0 */
7021 /* .. ==> 0XF8000760[2:2] = 0x00000000U */
7022 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7023 /* .. L2_SEL = 0 */
7024 /* .. ==> 0XF8000760[4:3] = 0x00000000U */
7025 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7026 /* .. L3_SEL = 0 */
7027 /* .. ==> 0XF8000760[7:5] = 0x00000000U */
7028 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7029 /* .. Speed = 1 */
7030 /* .. ==> 0XF8000760[8:8] = 0x00000001U */
7031 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7032 /* .. IO_Type = 4 */
7033 /* .. ==> 0XF8000760[11:9] = 0x00000004U */
7034 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
7035 /* .. PULLUP = 0 */
7036 /* .. ==> 0XF8000760[12:12] = 0x00000000U */
7037 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7038 /* .. DisableRcvr = 0 */
7039 /* .. ==> 0XF8000760[13:13] = 0x00000000U */
7040 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7041 /* .. */
7042 EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
7043 /* .. TRI_ENABLE = 1 */
7044 /* .. ==> 0XF8000764[0:0] = 0x00000001U */
7045 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7046 /* .. L0_SEL = 1 */
7047 /* .. ==> 0XF8000764[1:1] = 0x00000001U */
7048 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
7049 /* .. L1_SEL = 0 */
7050 /* .. ==> 0XF8000764[2:2] = 0x00000000U */
7051 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7052 /* .. L2_SEL = 0 */
7053 /* .. ==> 0XF8000764[4:3] = 0x00000000U */
7054 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7055 /* .. L3_SEL = 0 */
7056 /* .. ==> 0XF8000764[7:5] = 0x00000000U */
7057 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7058 /* .. Speed = 1 */
7059 /* .. ==> 0XF8000764[8:8] = 0x00000001U */
7060 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7061 /* .. IO_Type = 4 */
7062 /* .. ==> 0XF8000764[11:9] = 0x00000004U */
7063 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
7064 /* .. PULLUP = 0 */
7065 /* .. ==> 0XF8000764[12:12] = 0x00000000U */
7066 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7067 /* .. DisableRcvr = 0 */
7068 /* .. ==> 0XF8000764[13:13] = 0x00000000U */
7069 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7070 /* .. */
7071 EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
7072 /* .. TRI_ENABLE = 1 */
7073 /* .. ==> 0XF8000768[0:0] = 0x00000001U */
7074 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7075 /* .. L0_SEL = 1 */
7076 /* .. ==> 0XF8000768[1:1] = 0x00000001U */
7077 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
7078 /* .. L1_SEL = 0 */
7079 /* .. ==> 0XF8000768[2:2] = 0x00000000U */
7080 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7081 /* .. L2_SEL = 0 */
7082 /* .. ==> 0XF8000768[4:3] = 0x00000000U */
7083 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7084 /* .. L3_SEL = 0 */
7085 /* .. ==> 0XF8000768[7:5] = 0x00000000U */
7086 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7087 /* .. Speed = 1 */
7088 /* .. ==> 0XF8000768[8:8] = 0x00000001U */
7089 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7090 /* .. IO_Type = 4 */
7091 /* .. ==> 0XF8000768[11:9] = 0x00000004U */
7092 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
7093 /* .. PULLUP = 0 */
7094 /* .. ==> 0XF8000768[12:12] = 0x00000000U */
7095 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7096 /* .. DisableRcvr = 0 */
7097 /* .. ==> 0XF8000768[13:13] = 0x00000000U */
7098 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7099 /* .. */
7100 EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
7101 /* .. TRI_ENABLE = 1 */
7102 /* .. ==> 0XF800076C[0:0] = 0x00000001U */
7103 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7104 /* .. L0_SEL = 1 */
7105 /* .. ==> 0XF800076C[1:1] = 0x00000001U */
7106 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
7107 /* .. L1_SEL = 0 */
7108 /* .. ==> 0XF800076C[2:2] = 0x00000000U */
7109 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7110 /* .. L2_SEL = 0 */
7111 /* .. ==> 0XF800076C[4:3] = 0x00000000U */
7112 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7113 /* .. L3_SEL = 0 */
7114 /* .. ==> 0XF800076C[7:5] = 0x00000000U */
7115 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7116 /* .. Speed = 1 */
7117 /* .. ==> 0XF800076C[8:8] = 0x00000001U */
7118 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7119 /* .. IO_Type = 4 */
7120 /* .. ==> 0XF800076C[11:9] = 0x00000004U */
7121 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
7122 /* .. PULLUP = 0 */
7123 /* .. ==> 0XF800076C[12:12] = 0x00000000U */
7124 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7125 /* .. DisableRcvr = 0 */
7126 /* .. ==> 0XF800076C[13:13] = 0x00000000U */
7127 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7128 /* .. */
7129 EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
7130 /* .. TRI_ENABLE = 0 */
7131 /* .. ==> 0XF8000770[0:0] = 0x00000000U */
7132 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7133 /* .. L0_SEL = 0 */
7134 /* .. ==> 0XF8000770[1:1] = 0x00000000U */
7135 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7136 /* .. L1_SEL = 1 */
7137 /* .. ==> 0XF8000770[2:2] = 0x00000001U */
7138 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7139 /* .. L2_SEL = 0 */
7140 /* .. ==> 0XF8000770[4:3] = 0x00000000U */
7141 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7142 /* .. L3_SEL = 0 */
7143 /* .. ==> 0XF8000770[7:5] = 0x00000000U */
7144 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7145 /* .. Speed = 1 */
7146 /* .. ==> 0XF8000770[8:8] = 0x00000001U */
7147 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7148 /* .. IO_Type = 1 */
7149 /* .. ==> 0XF8000770[11:9] = 0x00000001U */
7150 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7151 /* .. PULLUP = 0 */
7152 /* .. ==> 0XF8000770[12:12] = 0x00000000U */
7153 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7154 /* .. DisableRcvr = 0 */
7155 /* .. ==> 0XF8000770[13:13] = 0x00000000U */
7156 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7157 /* .. */
7158 EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
7159 /* .. TRI_ENABLE = 1 */
7160 /* .. ==> 0XF8000774[0:0] = 0x00000001U */
7161 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7162 /* .. L0_SEL = 0 */
7163 /* .. ==> 0XF8000774[1:1] = 0x00000000U */
7164 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7165 /* .. L1_SEL = 1 */
7166 /* .. ==> 0XF8000774[2:2] = 0x00000001U */
7167 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7168 /* .. L2_SEL = 0 */
7169 /* .. ==> 0XF8000774[4:3] = 0x00000000U */
7170 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7171 /* .. L3_SEL = 0 */
7172 /* .. ==> 0XF8000774[7:5] = 0x00000000U */
7173 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7174 /* .. Speed = 1 */
7175 /* .. ==> 0XF8000774[8:8] = 0x00000001U */
7176 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7177 /* .. IO_Type = 1 */
7178 /* .. ==> 0XF8000774[11:9] = 0x00000001U */
7179 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7180 /* .. PULLUP = 0 */
7181 /* .. ==> 0XF8000774[12:12] = 0x00000000U */
7182 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7183 /* .. DisableRcvr = 0 */
7184 /* .. ==> 0XF8000774[13:13] = 0x00000000U */
7185 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7186 /* .. */
7187 EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
7188 /* .. TRI_ENABLE = 0 */
7189 /* .. ==> 0XF8000778[0:0] = 0x00000000U */
7190 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7191 /* .. L0_SEL = 0 */
7192 /* .. ==> 0XF8000778[1:1] = 0x00000000U */
7193 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7194 /* .. L1_SEL = 1 */
7195 /* .. ==> 0XF8000778[2:2] = 0x00000001U */
7196 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7197 /* .. L2_SEL = 0 */
7198 /* .. ==> 0XF8000778[4:3] = 0x00000000U */
7199 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7200 /* .. L3_SEL = 0 */
7201 /* .. ==> 0XF8000778[7:5] = 0x00000000U */
7202 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7203 /* .. Speed = 1 */
7204 /* .. ==> 0XF8000778[8:8] = 0x00000001U */
7205 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7206 /* .. IO_Type = 1 */
7207 /* .. ==> 0XF8000778[11:9] = 0x00000001U */
7208 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7209 /* .. PULLUP = 0 */
7210 /* .. ==> 0XF8000778[12:12] = 0x00000000U */
7211 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7212 /* .. DisableRcvr = 0 */
7213 /* .. ==> 0XF8000778[13:13] = 0x00000000U */
7214 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7215 /* .. */
7216 EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
7217 /* .. TRI_ENABLE = 1 */
7218 /* .. ==> 0XF800077C[0:0] = 0x00000001U */
7219 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7220 /* .. L0_SEL = 0 */
7221 /* .. ==> 0XF800077C[1:1] = 0x00000000U */
7222 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7223 /* .. L1_SEL = 1 */
7224 /* .. ==> 0XF800077C[2:2] = 0x00000001U */
7225 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7226 /* .. L2_SEL = 0 */
7227 /* .. ==> 0XF800077C[4:3] = 0x00000000U */
7228 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7229 /* .. L3_SEL = 0 */
7230 /* .. ==> 0XF800077C[7:5] = 0x00000000U */
7231 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7232 /* .. Speed = 1 */
7233 /* .. ==> 0XF800077C[8:8] = 0x00000001U */
7234 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7235 /* .. IO_Type = 1 */
7236 /* .. ==> 0XF800077C[11:9] = 0x00000001U */
7237 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7238 /* .. PULLUP = 0 */
7239 /* .. ==> 0XF800077C[12:12] = 0x00000000U */
7240 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7241 /* .. DisableRcvr = 0 */
7242 /* .. ==> 0XF800077C[13:13] = 0x00000000U */
7243 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7244 /* .. */
7245 EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
7246 /* .. TRI_ENABLE = 0 */
7247 /* .. ==> 0XF8000780[0:0] = 0x00000000U */
7248 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7249 /* .. L0_SEL = 0 */
7250 /* .. ==> 0XF8000780[1:1] = 0x00000000U */
7251 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7252 /* .. L1_SEL = 1 */
7253 /* .. ==> 0XF8000780[2:2] = 0x00000001U */
7254 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7255 /* .. L2_SEL = 0 */
7256 /* .. ==> 0XF8000780[4:3] = 0x00000000U */
7257 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7258 /* .. L3_SEL = 0 */
7259 /* .. ==> 0XF8000780[7:5] = 0x00000000U */
7260 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7261 /* .. Speed = 1 */
7262 /* .. ==> 0XF8000780[8:8] = 0x00000001U */
7263 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7264 /* .. IO_Type = 1 */
7265 /* .. ==> 0XF8000780[11:9] = 0x00000001U */
7266 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7267 /* .. PULLUP = 0 */
7268 /* .. ==> 0XF8000780[12:12] = 0x00000000U */
7269 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7270 /* .. DisableRcvr = 0 */
7271 /* .. ==> 0XF8000780[13:13] = 0x00000000U */
7272 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7273 /* .. */
7274 EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
7275 /* .. TRI_ENABLE = 0 */
7276 /* .. ==> 0XF8000784[0:0] = 0x00000000U */
7277 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7278 /* .. L0_SEL = 0 */
7279 /* .. ==> 0XF8000784[1:1] = 0x00000000U */
7280 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7281 /* .. L1_SEL = 1 */
7282 /* .. ==> 0XF8000784[2:2] = 0x00000001U */
7283 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7284 /* .. L2_SEL = 0 */
7285 /* .. ==> 0XF8000784[4:3] = 0x00000000U */
7286 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7287 /* .. L3_SEL = 0 */
7288 /* .. ==> 0XF8000784[7:5] = 0x00000000U */
7289 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7290 /* .. Speed = 1 */
7291 /* .. ==> 0XF8000784[8:8] = 0x00000001U */
7292 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7293 /* .. IO_Type = 1 */
7294 /* .. ==> 0XF8000784[11:9] = 0x00000001U */
7295 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7296 /* .. PULLUP = 0 */
7297 /* .. ==> 0XF8000784[12:12] = 0x00000000U */
7298 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7299 /* .. DisableRcvr = 0 */
7300 /* .. ==> 0XF8000784[13:13] = 0x00000000U */
7301 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7302 /* .. */
7303 EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
7304 /* .. TRI_ENABLE = 0 */
7305 /* .. ==> 0XF8000788[0:0] = 0x00000000U */
7306 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7307 /* .. L0_SEL = 0 */
7308 /* .. ==> 0XF8000788[1:1] = 0x00000000U */
7309 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7310 /* .. L1_SEL = 1 */
7311 /* .. ==> 0XF8000788[2:2] = 0x00000001U */
7312 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7313 /* .. L2_SEL = 0 */
7314 /* .. ==> 0XF8000788[4:3] = 0x00000000U */
7315 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7316 /* .. L3_SEL = 0 */
7317 /* .. ==> 0XF8000788[7:5] = 0x00000000U */
7318 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7319 /* .. Speed = 1 */
7320 /* .. ==> 0XF8000788[8:8] = 0x00000001U */
7321 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7322 /* .. IO_Type = 1 */
7323 /* .. ==> 0XF8000788[11:9] = 0x00000001U */
7324 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7325 /* .. PULLUP = 0 */
7326 /* .. ==> 0XF8000788[12:12] = 0x00000000U */
7327 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7328 /* .. DisableRcvr = 0 */
7329 /* .. ==> 0XF8000788[13:13] = 0x00000000U */
7330 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7331 /* .. */
7332 EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
7333 /* .. TRI_ENABLE = 0 */
7334 /* .. ==> 0XF800078C[0:0] = 0x00000000U */
7335 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7336 /* .. L0_SEL = 0 */
7337 /* .. ==> 0XF800078C[1:1] = 0x00000000U */
7338 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7339 /* .. L1_SEL = 1 */
7340 /* .. ==> 0XF800078C[2:2] = 0x00000001U */
7341 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7342 /* .. L2_SEL = 0 */
7343 /* .. ==> 0XF800078C[4:3] = 0x00000000U */
7344 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7345 /* .. L3_SEL = 0 */
7346 /* .. ==> 0XF800078C[7:5] = 0x00000000U */
7347 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7348 /* .. Speed = 1 */
7349 /* .. ==> 0XF800078C[8:8] = 0x00000001U */
7350 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7351 /* .. IO_Type = 1 */
7352 /* .. ==> 0XF800078C[11:9] = 0x00000001U */
7353 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7354 /* .. PULLUP = 0 */
7355 /* .. ==> 0XF800078C[12:12] = 0x00000000U */
7356 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7357 /* .. DisableRcvr = 0 */
7358 /* .. ==> 0XF800078C[13:13] = 0x00000000U */
7359 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7360 /* .. */
7361 EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
7362 /* .. TRI_ENABLE = 1 */
7363 /* .. ==> 0XF8000790[0:0] = 0x00000001U */
7364 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7365 /* .. L0_SEL = 0 */
7366 /* .. ==> 0XF8000790[1:1] = 0x00000000U */
7367 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7368 /* .. L1_SEL = 1 */
7369 /* .. ==> 0XF8000790[2:2] = 0x00000001U */
7370 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7371 /* .. L2_SEL = 0 */
7372 /* .. ==> 0XF8000790[4:3] = 0x00000000U */
7373 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7374 /* .. L3_SEL = 0 */
7375 /* .. ==> 0XF8000790[7:5] = 0x00000000U */
7376 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7377 /* .. Speed = 1 */
7378 /* .. ==> 0XF8000790[8:8] = 0x00000001U */
7379 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7380 /* .. IO_Type = 1 */
7381 /* .. ==> 0XF8000790[11:9] = 0x00000001U */
7382 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7383 /* .. PULLUP = 0 */
7384 /* .. ==> 0XF8000790[12:12] = 0x00000000U */
7385 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7386 /* .. DisableRcvr = 0 */
7387 /* .. ==> 0XF8000790[13:13] = 0x00000000U */
7388 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7389 /* .. */
7390 EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
7391 /* .. TRI_ENABLE = 0 */
7392 /* .. ==> 0XF8000794[0:0] = 0x00000000U */
7393 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7394 /* .. L0_SEL = 0 */
7395 /* .. ==> 0XF8000794[1:1] = 0x00000000U */
7396 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7397 /* .. L1_SEL = 1 */
7398 /* .. ==> 0XF8000794[2:2] = 0x00000001U */
7399 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7400 /* .. L2_SEL = 0 */
7401 /* .. ==> 0XF8000794[4:3] = 0x00000000U */
7402 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7403 /* .. L3_SEL = 0 */
7404 /* .. ==> 0XF8000794[7:5] = 0x00000000U */
7405 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7406 /* .. Speed = 1 */
7407 /* .. ==> 0XF8000794[8:8] = 0x00000001U */
7408 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7409 /* .. IO_Type = 1 */
7410 /* .. ==> 0XF8000794[11:9] = 0x00000001U */
7411 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7412 /* .. PULLUP = 0 */
7413 /* .. ==> 0XF8000794[12:12] = 0x00000000U */
7414 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7415 /* .. DisableRcvr = 0 */
7416 /* .. ==> 0XF8000794[13:13] = 0x00000000U */
7417 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7418 /* .. */
7419 EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
7420 /* .. TRI_ENABLE = 0 */
7421 /* .. ==> 0XF8000798[0:0] = 0x00000000U */
7422 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7423 /* .. L0_SEL = 0 */
7424 /* .. ==> 0XF8000798[1:1] = 0x00000000U */
7425 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7426 /* .. L1_SEL = 1 */
7427 /* .. ==> 0XF8000798[2:2] = 0x00000001U */
7428 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7429 /* .. L2_SEL = 0 */
7430 /* .. ==> 0XF8000798[4:3] = 0x00000000U */
7431 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7432 /* .. L3_SEL = 0 */
7433 /* .. ==> 0XF8000798[7:5] = 0x00000000U */
7434 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7435 /* .. Speed = 1 */
7436 /* .. ==> 0XF8000798[8:8] = 0x00000001U */
7437 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7438 /* .. IO_Type = 1 */
7439 /* .. ==> 0XF8000798[11:9] = 0x00000001U */
7440 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7441 /* .. PULLUP = 0 */
7442 /* .. ==> 0XF8000798[12:12] = 0x00000000U */
7443 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7444 /* .. DisableRcvr = 0 */
7445 /* .. ==> 0XF8000798[13:13] = 0x00000000U */
7446 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7447 /* .. */
7448 EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
7449 /* .. TRI_ENABLE = 0 */
7450 /* .. ==> 0XF800079C[0:0] = 0x00000000U */
7451 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7452 /* .. L0_SEL = 0 */
7453 /* .. ==> 0XF800079C[1:1] = 0x00000000U */
7454 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7455 /* .. L1_SEL = 1 */
7456 /* .. ==> 0XF800079C[2:2] = 0x00000001U */
7457 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7458 /* .. L2_SEL = 0 */
7459 /* .. ==> 0XF800079C[4:3] = 0x00000000U */
7460 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7461 /* .. L3_SEL = 0 */
7462 /* .. ==> 0XF800079C[7:5] = 0x00000000U */
7463 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7464 /* .. Speed = 1 */
7465 /* .. ==> 0XF800079C[8:8] = 0x00000001U */
7466 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7467 /* .. IO_Type = 1 */
7468 /* .. ==> 0XF800079C[11:9] = 0x00000001U */
7469 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7470 /* .. PULLUP = 0 */
7471 /* .. ==> 0XF800079C[12:12] = 0x00000000U */
7472 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7473 /* .. DisableRcvr = 0 */
7474 /* .. ==> 0XF800079C[13:13] = 0x00000000U */
7475 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7476 /* .. */
7477 EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
7478 /* .. TRI_ENABLE = 0 */
7479 /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
7480 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7481 /* .. L0_SEL = 0 */
7482 /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
7483 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7484 /* .. L1_SEL = 0 */
7485 /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
7486 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7487 /* .. L2_SEL = 0 */
7488 /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
7489 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7490 /* .. L3_SEL = 4 */
7491 /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
7492 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7493 /* .. Speed = 1 */
7494 /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
7495 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7496 /* .. IO_Type = 1 */
7497 /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
7498 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7499 /* .. PULLUP = 0 */
7500 /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
7501 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7502 /* .. DisableRcvr = 0 */
7503 /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
7504 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7505 /* .. */
7506 EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
7507 /* .. TRI_ENABLE = 0 */
7508 /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
7509 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7510 /* .. L0_SEL = 0 */
7511 /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
7512 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7513 /* .. L1_SEL = 0 */
7514 /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
7515 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7516 /* .. L2_SEL = 0 */
7517 /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
7518 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7519 /* .. L3_SEL = 4 */
7520 /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
7521 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7522 /* .. Speed = 1 */
7523 /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
7524 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7525 /* .. IO_Type = 1 */
7526 /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
7527 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7528 /* .. PULLUP = 0 */
7529 /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
7530 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7531 /* .. DisableRcvr = 0 */
7532 /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
7533 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7534 /* .. */
7535 EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
7536 /* .. TRI_ENABLE = 0 */
7537 /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
7538 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7539 /* .. L0_SEL = 0 */
7540 /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
7541 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7542 /* .. L1_SEL = 0 */
7543 /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
7544 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7545 /* .. L2_SEL = 0 */
7546 /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
7547 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7548 /* .. L3_SEL = 4 */
7549 /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
7550 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7551 /* .. Speed = 1 */
7552 /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
7553 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7554 /* .. IO_Type = 1 */
7555 /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
7556 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7557 /* .. PULLUP = 0 */
7558 /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
7559 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7560 /* .. DisableRcvr = 0 */
7561 /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
7562 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7563 /* .. */
7564 EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
7565 /* .. TRI_ENABLE = 0 */
7566 /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
7567 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7568 /* .. L0_SEL = 0 */
7569 /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
7570 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7571 /* .. L1_SEL = 0 */
7572 /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
7573 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7574 /* .. L2_SEL = 0 */
7575 /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
7576 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7577 /* .. L3_SEL = 4 */
7578 /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
7579 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7580 /* .. Speed = 1 */
7581 /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
7582 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7583 /* .. IO_Type = 1 */
7584 /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
7585 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7586 /* .. PULLUP = 0 */
7587 /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
7588 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7589 /* .. DisableRcvr = 0 */
7590 /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
7591 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7592 /* .. */
7593 EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
7594 /* .. TRI_ENABLE = 0 */
7595 /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
7596 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7597 /* .. L0_SEL = 0 */
7598 /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
7599 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7600 /* .. L1_SEL = 0 */
7601 /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
7602 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7603 /* .. L2_SEL = 0 */
7604 /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
7605 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7606 /* .. L3_SEL = 4 */
7607 /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
7608 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7609 /* .. Speed = 1 */
7610 /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
7611 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7612 /* .. IO_Type = 1 */
7613 /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
7614 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7615 /* .. PULLUP = 0 */
7616 /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
7617 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7618 /* .. DisableRcvr = 0 */
7619 /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
7620 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7621 /* .. */
7622 EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
7623 /* .. TRI_ENABLE = 0 */
7624 /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
7625 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7626 /* .. L0_SEL = 0 */
7627 /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
7628 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7629 /* .. L1_SEL = 0 */
7630 /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
7631 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7632 /* .. L2_SEL = 0 */
7633 /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
7634 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7635 /* .. L3_SEL = 4 */
7636 /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
7637 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7638 /* .. Speed = 1 */
7639 /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
7640 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7641 /* .. IO_Type = 1 */
7642 /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
7643 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7644 /* .. PULLUP = 0 */
7645 /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
7646 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7647 /* .. DisableRcvr = 0 */
7648 /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
7649 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7650 /* .. */
7651 EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
7652 /* .. TRI_ENABLE = 0 */
7653 /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
7654 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7655 /* .. L0_SEL = 0 */
7656 /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
7657 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7658 /* .. L1_SEL = 0 */
7659 /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
7660 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7661 /* .. L2_SEL = 0 */
7662 /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
7663 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7664 /* .. L3_SEL = 0 */
7665 /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
7666 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7667 /* .. Speed = 0 */
7668 /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
7669 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7670 /* .. IO_Type = 1 */
7671 /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
7672 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7673 /* .. PULLUP = 1 */
7674 /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
7675 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
7676 /* .. DisableRcvr = 0 */
7677 /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
7678 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7679 /* .. */
7680 EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
7681 /* .. TRI_ENABLE = 1 */
7682 /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
7683 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7684 /* .. Speed = 0 */
7685 /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
7686 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7687 /* .. IO_Type = 1 */
7688 /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
7689 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7690 /* .. PULLUP = 0 */
7691 /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
7692 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7693 /* .. DisableRcvr = 0 */
7694 /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
7695 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7696 /* .. */
7697 EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
7698 /* .. TRI_ENABLE = 0 */
7699 /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
7700 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7701 /* .. L0_SEL = 0 */
7702 /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
7703 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7704 /* .. L1_SEL = 0 */
7705 /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
7706 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7707 /* .. L2_SEL = 0 */
7708 /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
7709 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7710 /* .. L3_SEL = 7 */
7711 /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
7712 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
7713 /* .. Speed = 0 */
7714 /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
7715 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7716 /* .. IO_Type = 1 */
7717 /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
7718 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7719 /* .. PULLUP = 0 */
7720 /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
7721 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7722 /* .. DisableRcvr = 0 */
7723 /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
7724 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7725 /* .. */
7726 EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
7727 /* .. TRI_ENABLE = 1 */
7728 /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
7729 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7730 /* .. L0_SEL = 0 */
7731 /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
7732 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7733 /* .. L1_SEL = 0 */
7734 /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
7735 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7736 /* .. L2_SEL = 0 */
7737 /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
7738 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7739 /* .. L3_SEL = 7 */
7740 /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
7741 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
7742 /* .. Speed = 0 */
7743 /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
7744 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7745 /* .. IO_Type = 1 */
7746 /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
7747 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7748 /* .. PULLUP = 0 */
7749 /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
7750 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7751 /* .. DisableRcvr = 0 */
7752 /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
7753 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7754 /* .. */
7755 EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
7756 /* .. TRI_ENABLE = 0 */
7757 /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
7758 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7759 /* .. L0_SEL = 0 */
7760 /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
7761 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7762 /* .. L1_SEL = 0 */
7763 /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
7764 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7765 /* .. L2_SEL = 0 */
7766 /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
7767 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7768 /* .. L3_SEL = 0 */
7769 /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
7770 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7771 /* .. Speed = 0 */
7772 /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
7773 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7774 /* .. IO_Type = 1 */
7775 /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
7776 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7777 /* .. PULLUP = 0 */
7778 /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
7779 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7780 /* .. DisableRcvr = 0 */
7781 /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
7782 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7783 /* .. */
7784 EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
7785 /* .. TRI_ENABLE = 0 */
7786 /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
7787 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7788 /* .. L0_SEL = 0 */
7789 /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
7790 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7791 /* .. L1_SEL = 0 */
7792 /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
7793 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7794 /* .. L2_SEL = 0 */
7795 /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
7796 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7797 /* .. L3_SEL = 0 */
7798 /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
7799 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
7800 /* .. Speed = 0 */
7801 /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
7802 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7803 /* .. IO_Type = 1 */
7804 /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
7805 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7806 /* .. PULLUP = 0 */
7807 /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
7808 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7809 /* .. DisableRcvr = 0 */
7810 /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
7811 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7812 /* .. */
7813 EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
7814 /* .. TRI_ENABLE = 0 */
7815 /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
7816 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7817 /* .. L0_SEL = 0 */
7818 /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
7819 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7820 /* .. L1_SEL = 0 */
7821 /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
7822 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7823 /* .. L2_SEL = 0 */
7824 /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
7825 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7826 /* .. L3_SEL = 4 */
7827 /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
7828 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7829 /* .. Speed = 0 */
7830 /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
7831 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7832 /* .. IO_Type = 1 */
7833 /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
7834 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7835 /* .. PULLUP = 0 */
7836 /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
7837 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7838 /* .. DisableRcvr = 0 */
7839 /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
7840 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7841 /* .. */
7842 EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
7843 /* .. TRI_ENABLE = 0 */
7844 /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
7845 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
7846 /* .. L0_SEL = 0 */
7847 /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
7848 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
7849 /* .. L1_SEL = 0 */
7850 /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
7851 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
7852 /* .. L2_SEL = 0 */
7853 /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
7854 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
7855 /* .. L3_SEL = 4 */
7856 /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
7857 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
7858 /* .. Speed = 0 */
7859 /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
7860 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7861 /* .. IO_Type = 1 */
7862 /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
7863 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
7864 /* .. PULLUP = 0 */
7865 /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
7866 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
7867 /* .. DisableRcvr = 0 */
7868 /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
7869 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
7870 /* .. */
7871 EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
7872 /* .. SDIO0_WP_SEL = 55 */
7873 /* .. ==> 0XF8000830[5:0] = 0x00000037U */
7874 /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
7875 /* .. SDIO0_CD_SEL = 47 */
7876 /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
7877 /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
7878 /* .. */
7879 EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
7880 /* .. FINISH: MIO PROGRAMMING */
7881 /* .. START: LOCK IT BACK */
7882 /* .. LOCK_KEY = 0X767B */
7883 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
7884 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
7885 /* .. */
7886 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
7887 /* .. FINISH: LOCK IT BACK */
7888 /* FINISH: top */
7889 /* */
7890 EMIT_EXIT(),
7891
7892 /* */
7893 };
7894
7895 unsigned long ps7_peripherals_init_data_2_0[] = {
7896 /* START: top */
7897 /* .. START: SLCR SETTINGS */
7898 /* .. UNLOCK_KEY = 0XDF0D */
7899 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
7900 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
7901 /* .. */
7902 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
7903 /* .. FINISH: SLCR SETTINGS */
7904 /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
7905 /* .. IBUF_DISABLE_MODE = 0x1 */
7906 /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
7907 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
7908 /* .. TERM_DISABLE_MODE = 0x1 */
7909 /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
7910 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7911 /* .. */
7912 EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
7913 /* .. IBUF_DISABLE_MODE = 0x1 */
7914 /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
7915 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
7916 /* .. TERM_DISABLE_MODE = 0x1 */
7917 /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
7918 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7919 /* .. */
7920 EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
7921 /* .. IBUF_DISABLE_MODE = 0x1 */
7922 /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
7923 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
7924 /* .. TERM_DISABLE_MODE = 0x1 */
7925 /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
7926 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7927 /* .. */
7928 EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
7929 /* .. IBUF_DISABLE_MODE = 0x1 */
7930 /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
7931 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
7932 /* .. TERM_DISABLE_MODE = 0x1 */
7933 /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
7934 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
7935 /* .. */
7936 EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
7937 /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
7938 /* .. START: LOCK IT BACK */
7939 /* .. LOCK_KEY = 0X767B */
7940 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
7941 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
7942 /* .. */
7943 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
7944 /* .. FINISH: LOCK IT BACK */
7945 /* .. START: SRAM/NOR SET OPMODE */
7946 /* .. FINISH: SRAM/NOR SET OPMODE */
7947 /* .. START: UART REGISTERS */
7948 /* .. BDIV = 0x6 */
7949 /* .. ==> 0XE0001034[7:0] = 0x00000006U */
7950 /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
7951 /* .. */
7952 EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
7953 /* .. CD = 0x7c */
7954 /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
7955 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
7956 /* .. */
7957 EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
7958 /* .. STPBRK = 0x0 */
7959 /* .. ==> 0XE0001000[8:8] = 0x00000000U */
7960 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
7961 /* .. STTBRK = 0x0 */
7962 /* .. ==> 0XE0001000[7:7] = 0x00000000U */
7963 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
7964 /* .. RSTTO = 0x0 */
7965 /* .. ==> 0XE0001000[6:6] = 0x00000000U */
7966 /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
7967 /* .. TXDIS = 0x0 */
7968 /* .. ==> 0XE0001000[5:5] = 0x00000000U */
7969 /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
7970 /* .. TXEN = 0x1 */
7971 /* .. ==> 0XE0001000[4:4] = 0x00000001U */
7972 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
7973 /* .. RXDIS = 0x0 */
7974 /* .. ==> 0XE0001000[3:3] = 0x00000000U */
7975 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
7976 /* .. RXEN = 0x1 */
7977 /* .. ==> 0XE0001000[2:2] = 0x00000001U */
7978 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
7979 /* .. TXRES = 0x1 */
7980 /* .. ==> 0XE0001000[1:1] = 0x00000001U */
7981 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
7982 /* .. RXRES = 0x1 */
7983 /* .. ==> 0XE0001000[0:0] = 0x00000001U */
7984 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
7985 /* .. */
7986 EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
7987 /* .. IRMODE = 0x0 */
7988 /* .. ==> 0XE0001004[11:11] = 0x00000000U */
7989 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
7990 /* .. UCLKEN = 0x0 */
7991 /* .. ==> 0XE0001004[10:10] = 0x00000000U */
7992 /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
7993 /* .. CHMODE = 0x0 */
7994 /* .. ==> 0XE0001004[9:8] = 0x00000000U */
7995 /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
7996 /* .. NBSTOP = 0x0 */
7997 /* .. ==> 0XE0001004[7:6] = 0x00000000U */
7998 /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
7999 /* .. PAR = 0x4 */
8000 /* .. ==> 0XE0001004[5:3] = 0x00000004U */
8001 /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
8002 /* .. CHRL = 0x0 */
8003 /* .. ==> 0XE0001004[2:1] = 0x00000000U */
8004 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
8005 /* .. CLKS = 0x0 */
8006 /* .. ==> 0XE0001004[0:0] = 0x00000000U */
8007 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8008 /* .. */
8009 EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
8010 /* .. FINISH: UART REGISTERS */
8011 /* .. START: QSPI REGISTERS */
8012 /* .. Holdb_dr = 1 */
8013 /* .. ==> 0XE000D000[19:19] = 0x00000001U */
8014 /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
8015 /* .. */
8016 EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
8017 /* .. FINISH: QSPI REGISTERS */
8018 /* .. START: PL POWER ON RESET REGISTERS */
8019 /* .. PCFG_POR_CNT_4K = 0 */
8020 /* .. ==> 0XF8007000[29:29] = 0x00000000U */
8021 /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
8022 /* .. */
8023 EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
8024 /* .. FINISH: PL POWER ON RESET REGISTERS */
8025 /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
8026 /* .. .. START: NAND SET CYCLE */
8027 /* .. .. FINISH: NAND SET CYCLE */
8028 /* .. .. START: OPMODE */
8029 /* .. .. FINISH: OPMODE */
8030 /* .. .. START: DIRECT COMMAND */
8031 /* .. .. FINISH: DIRECT COMMAND */
8032 /* .. .. START: SRAM/NOR CS0 SET CYCLE */
8033 /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
8034 /* .. .. START: DIRECT COMMAND */
8035 /* .. .. FINISH: DIRECT COMMAND */
8036 /* .. .. START: NOR CS0 BASE ADDRESS */
8037 /* .. .. FINISH: NOR CS0 BASE ADDRESS */
8038 /* .. .. START: SRAM/NOR CS1 SET CYCLE */
8039 /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
8040 /* .. .. START: DIRECT COMMAND */
8041 /* .. .. FINISH: DIRECT COMMAND */
8042 /* .. .. START: NOR CS1 BASE ADDRESS */
8043 /* .. .. FINISH: NOR CS1 BASE ADDRESS */
8044 /* .. .. START: USB RESET */
8045 /* .. .. .. START: USB0 RESET */
8046 /* .. .. .. .. START: DIR MODE BANK 0 */
8047 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
8048 /* .. .. .. .. START: DIR MODE BANK 1 */
8049 /* .. .. .. .. DIRECTION_1 = 0x4000 */
8050 /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
8051 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
8052 /* .. .. .. .. */
8053 EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
8054 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
8055 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8056 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8057 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8058 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8059 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8060 /* .. .. .. .. MASK_1_LSW = 0xbfff */
8061 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
8062 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
8063 /* .. .. .. .. DATA_1_LSW = 0x4000 */
8064 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
8065 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
8066 /* .. .. .. .. */
8067 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
8068 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8069 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8070 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8071 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
8072 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
8073 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
8074 /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
8075 /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
8076 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
8077 /* .. .. .. .. */
8078 EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
8079 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
8080 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8081 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8082 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8083 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8084 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
8085 /* .. .. .. .. MASK_1_LSW = 0xbfff */
8086 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
8087 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
8088 /* .. .. .. .. DATA_1_LSW = 0x0 */
8089 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
8090 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
8091 /* .. .. .. .. */
8092 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
8093 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8094 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8095 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8096 /* .. .. .. .. START: ADD 1 MS DELAY */
8097 /* .. .. .. .. */
8098 EMIT_MASKDELAY(0XF8F00200, 1),
8099 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8100 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8101 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8102 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8103 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8104 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8105 /* .. .. .. .. MASK_1_LSW = 0xbfff */
8106 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
8107 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
8108 /* .. .. .. .. DATA_1_LSW = 0x4000 */
8109 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
8110 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
8111 /* .. .. .. .. */
8112 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
8113 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8114 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8115 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8116 /* .. .. .. FINISH: USB0 RESET */
8117 /* .. .. .. START: USB1 RESET */
8118 /* .. .. .. .. START: DIR MODE BANK 0 */
8119 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
8120 /* .. .. .. .. START: DIR MODE BANK 1 */
8121 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
8122 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8123 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8124 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8125 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8126 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8127 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8128 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8129 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8130 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
8131 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
8132 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
8133 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
8134 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8135 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8136 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8137 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8138 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
8139 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8140 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8141 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8142 /* .. .. .. .. START: ADD 1 MS DELAY */
8143 /* .. .. .. .. */
8144 EMIT_MASKDELAY(0XF8F00200, 1),
8145 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8146 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8147 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8148 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8149 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8150 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8151 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8152 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8153 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8154 /* .. .. .. FINISH: USB1 RESET */
8155 /* .. .. FINISH: USB RESET */
8156 /* .. .. START: ENET RESET */
8157 /* .. .. .. START: ENET0 RESET */
8158 /* .. .. .. .. START: DIR MODE BANK 0 */
8159 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
8160 /* .. .. .. .. START: DIR MODE BANK 1 */
8161 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
8162 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8163 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8164 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8165 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8166 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8167 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8168 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8169 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8170 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
8171 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
8172 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
8173 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
8174 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8175 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8176 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8177 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8178 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
8179 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8180 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8181 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8182 /* .. .. .. .. START: ADD 1 MS DELAY */
8183 /* .. .. .. .. */
8184 EMIT_MASKDELAY(0XF8F00200, 1),
8185 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8186 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8187 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8188 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8189 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8190 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8191 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8192 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8193 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8194 /* .. .. .. FINISH: ENET0 RESET */
8195 /* .. .. .. START: ENET1 RESET */
8196 /* .. .. .. .. START: DIR MODE BANK 0 */
8197 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
8198 /* .. .. .. .. START: DIR MODE BANK 1 */
8199 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
8200 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8201 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8202 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8203 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8204 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8205 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8206 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8207 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8208 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
8209 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
8210 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
8211 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
8212 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8213 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8214 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8215 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8216 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
8217 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8218 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8219 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8220 /* .. .. .. .. START: ADD 1 MS DELAY */
8221 /* .. .. .. .. */
8222 EMIT_MASKDELAY(0XF8F00200, 1),
8223 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8224 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8225 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8226 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8227 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8228 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8229 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8230 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8231 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8232 /* .. .. .. FINISH: ENET1 RESET */
8233 /* .. .. FINISH: ENET RESET */
8234 /* .. .. START: I2C RESET */
8235 /* .. .. .. START: I2C0 RESET */
8236 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
8237 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
8238 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
8239 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
8240 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8241 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8242 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8243 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8244 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8245 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8246 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8247 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8248 /* .. .. .. .. START: OUTPUT ENABLE */
8249 /* .. .. .. .. FINISH: OUTPUT ENABLE */
8250 /* .. .. .. .. START: OUTPUT ENABLE */
8251 /* .. .. .. .. FINISH: OUTPUT ENABLE */
8252 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8253 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8254 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8255 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8256 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
8257 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8258 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8259 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8260 /* .. .. .. .. START: ADD 1 MS DELAY */
8261 /* .. .. .. .. */
8262 EMIT_MASKDELAY(0XF8F00200, 1),
8263 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8264 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8265 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8266 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8267 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8268 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8269 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8270 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8271 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8272 /* .. .. .. FINISH: I2C0 RESET */
8273 /* .. .. .. START: I2C1 RESET */
8274 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
8275 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
8276 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
8277 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
8278 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8279 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8280 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8281 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8282 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8283 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8284 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8285 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8286 /* .. .. .. .. START: OUTPUT ENABLE */
8287 /* .. .. .. .. FINISH: OUTPUT ENABLE */
8288 /* .. .. .. .. START: OUTPUT ENABLE */
8289 /* .. .. .. .. FINISH: OUTPUT ENABLE */
8290 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
8291 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
8292 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
8293 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
8294 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
8295 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
8296 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
8297 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
8298 /* .. .. .. .. START: ADD 1 MS DELAY */
8299 /* .. .. .. .. */
8300 EMIT_MASKDELAY(0XF8F00200, 1),
8301 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
8302 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8303 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8304 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
8305 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
8306 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
8307 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
8308 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
8309 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
8310 /* .. .. .. FINISH: I2C1 RESET */
8311 /* .. .. FINISH: I2C RESET */
8312 /* .. .. START: NOR CHIP SELECT */
8313 /* .. .. .. START: DIR MODE BANK 0 */
8314 /* .. .. .. FINISH: DIR MODE BANK 0 */
8315 /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
8316 /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
8317 /* .. .. .. START: OUTPUT ENABLE BANK 0 */
8318 /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
8319 /* .. .. FINISH: NOR CHIP SELECT */
8320 /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
8321 /* FINISH: top */
8322 /* */
8323 EMIT_EXIT(),
8324
8325 /* */
8326 };
8327
8328 unsigned long ps7_post_config_2_0[] = {
8329 /* START: top */
8330 /* .. START: SLCR SETTINGS */
8331 /* .. UNLOCK_KEY = 0XDF0D */
8332 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
8333 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
8334 /* .. */
8335 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
8336 /* .. FINISH: SLCR SETTINGS */
8337 /* .. START: ENABLING LEVEL SHIFTER */
8338 /* .. USER_INP_ICT_EN_0 = 3 */
8339 /* .. ==> 0XF8000900[1:0] = 0x00000003U */
8340 /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
8341 /* .. USER_INP_ICT_EN_1 = 3 */
8342 /* .. ==> 0XF8000900[3:2] = 0x00000003U */
8343 /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
8344 /* .. */
8345 EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
8346 /* .. FINISH: ENABLING LEVEL SHIFTER */
8347 /* .. START: FPGA RESETS TO 0 */
8348 /* .. reserved_3 = 0 */
8349 /* .. ==> 0XF8000240[31:25] = 0x00000000U */
8350 /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
8351 /* .. FPGA_ACP_RST = 0 */
8352 /* .. ==> 0XF8000240[24:24] = 0x00000000U */
8353 /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
8354 /* .. FPGA_AXDS3_RST = 0 */
8355 /* .. ==> 0XF8000240[23:23] = 0x00000000U */
8356 /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
8357 /* .. FPGA_AXDS2_RST = 0 */
8358 /* .. ==> 0XF8000240[22:22] = 0x00000000U */
8359 /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
8360 /* .. FPGA_AXDS1_RST = 0 */
8361 /* .. ==> 0XF8000240[21:21] = 0x00000000U */
8362 /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
8363 /* .. FPGA_AXDS0_RST = 0 */
8364 /* .. ==> 0XF8000240[20:20] = 0x00000000U */
8365 /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
8366 /* .. reserved_2 = 0 */
8367 /* .. ==> 0XF8000240[19:18] = 0x00000000U */
8368 /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
8369 /* .. FSSW1_FPGA_RST = 0 */
8370 /* .. ==> 0XF8000240[17:17] = 0x00000000U */
8371 /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
8372 /* .. FSSW0_FPGA_RST = 0 */
8373 /* .. ==> 0XF8000240[16:16] = 0x00000000U */
8374 /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
8375 /* .. reserved_1 = 0 */
8376 /* .. ==> 0XF8000240[15:14] = 0x00000000U */
8377 /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
8378 /* .. FPGA_FMSW1_RST = 0 */
8379 /* .. ==> 0XF8000240[13:13] = 0x00000000U */
8380 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
8381 /* .. FPGA_FMSW0_RST = 0 */
8382 /* .. ==> 0XF8000240[12:12] = 0x00000000U */
8383 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
8384 /* .. FPGA_DMA3_RST = 0 */
8385 /* .. ==> 0XF8000240[11:11] = 0x00000000U */
8386 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
8387 /* .. FPGA_DMA2_RST = 0 */
8388 /* .. ==> 0XF8000240[10:10] = 0x00000000U */
8389 /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
8390 /* .. FPGA_DMA1_RST = 0 */
8391 /* .. ==> 0XF8000240[9:9] = 0x00000000U */
8392 /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
8393 /* .. FPGA_DMA0_RST = 0 */
8394 /* .. ==> 0XF8000240[8:8] = 0x00000000U */
8395 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
8396 /* .. reserved = 0 */
8397 /* .. ==> 0XF8000240[7:4] = 0x00000000U */
8398 /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
8399 /* .. FPGA3_OUT_RST = 0 */
8400 /* .. ==> 0XF8000240[3:3] = 0x00000000U */
8401 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
8402 /* .. FPGA2_OUT_RST = 0 */
8403 /* .. ==> 0XF8000240[2:2] = 0x00000000U */
8404 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
8405 /* .. FPGA1_OUT_RST = 0 */
8406 /* .. ==> 0XF8000240[1:1] = 0x00000000U */
8407 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
8408 /* .. FPGA0_OUT_RST = 0 */
8409 /* .. ==> 0XF8000240[0:0] = 0x00000000U */
8410 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8411 /* .. */
8412 EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
8413 /* .. FINISH: FPGA RESETS TO 0 */
8414 /* .. START: AFI REGISTERS */
8415 /* .. .. START: AFI0 REGISTERS */
8416 /* .. .. FINISH: AFI0 REGISTERS */
8417 /* .. .. START: AFI1 REGISTERS */
8418 /* .. .. FINISH: AFI1 REGISTERS */
8419 /* .. .. START: AFI2 REGISTERS */
8420 /* .. .. FINISH: AFI2 REGISTERS */
8421 /* .. .. START: AFI3 REGISTERS */
8422 /* .. .. FINISH: AFI3 REGISTERS */
8423 /* .. FINISH: AFI REGISTERS */
8424 /* .. START: LOCK IT BACK */
8425 /* .. LOCK_KEY = 0X767B */
8426 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
8427 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
8428 /* .. */
8429 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
8430 /* .. FINISH: LOCK IT BACK */
8431 /* FINISH: top */
8432 /* */
8433 EMIT_EXIT(),
8434
8435 /* */
8436 };
8437
8438
8439 unsigned long ps7_pll_init_data_1_0[] = {
8440 /* START: top */
8441 /* .. START: SLCR SETTINGS */
8442 /* .. UNLOCK_KEY = 0XDF0D */
8443 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
8444 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
8445 /* .. */
8446 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
8447 /* .. FINISH: SLCR SETTINGS */
8448 /* .. START: PLL SLCR REGISTERS */
8449 /* .. .. START: ARM PLL INIT */
8450 /* .. .. PLL_RES = 0xc */
8451 /* .. .. ==> 0XF8000110[7:4] = 0x0000000CU */
8452 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
8453 /* .. .. PLL_CP = 0x2 */
8454 /* .. .. ==> 0XF8000110[11:8] = 0x00000002U */
8455 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
8456 /* .. .. LOCK_CNT = 0x177 */
8457 /* .. .. ==> 0XF8000110[21:12] = 0x00000177U */
8458 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00177000U */
8459 /* .. .. */
8460 EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
8461 /* .. .. .. START: UPDATE FB_DIV */
8462 /* .. .. .. PLL_FDIV = 0x1a */
8463 /* .. .. .. ==> 0XF8000100[18:12] = 0x0000001AU */
8464 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x0001A000U */
8465 /* .. .. .. */
8466 EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
8467 /* .. .. .. FINISH: UPDATE FB_DIV */
8468 /* .. .. .. START: BY PASS PLL */
8469 /* .. .. .. PLL_BYPASS_FORCE = 1 */
8470 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000001U */
8471 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
8472 /* .. .. .. */
8473 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
8474 /* .. .. .. FINISH: BY PASS PLL */
8475 /* .. .. .. START: ASSERT RESET */
8476 /* .. .. .. PLL_RESET = 1 */
8477 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000001U */
8478 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8479 /* .. .. .. */
8480 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
8481 /* .. .. .. FINISH: ASSERT RESET */
8482 /* .. .. .. START: DEASSERT RESET */
8483 /* .. .. .. PLL_RESET = 0 */
8484 /* .. .. .. ==> 0XF8000100[0:0] = 0x00000000U */
8485 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8486 /* .. .. .. */
8487 EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
8488 /* .. .. .. FINISH: DEASSERT RESET */
8489 /* .. .. .. START: CHECK PLL STATUS */
8490 /* .. .. .. ARM_PLL_LOCK = 1 */
8491 /* .. .. .. ==> 0XF800010C[0:0] = 0x00000001U */
8492 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8493 /* .. .. .. */
8494 EMIT_MASKPOLL(0XF800010C, 0x00000001U),
8495 /* .. .. .. FINISH: CHECK PLL STATUS */
8496 /* .. .. .. START: REMOVE PLL BY PASS */
8497 /* .. .. .. PLL_BYPASS_FORCE = 0 */
8498 /* .. .. .. ==> 0XF8000100[4:4] = 0x00000000U */
8499 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
8500 /* .. .. .. */
8501 EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
8502 /* .. .. .. FINISH: REMOVE PLL BY PASS */
8503 /* .. .. .. SRCSEL = 0x0 */
8504 /* .. .. .. ==> 0XF8000120[5:4] = 0x00000000U */
8505 /* .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8506 /* .. .. .. DIVISOR = 0x2 */
8507 /* .. .. .. ==> 0XF8000120[13:8] = 0x00000002U */
8508 /* .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U */
8509 /* .. .. .. CPU_6OR4XCLKACT = 0x1 */
8510 /* .. .. .. ==> 0XF8000120[24:24] = 0x00000001U */
8511 /* .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
8512 /* .. .. .. CPU_3OR2XCLKACT = 0x1 */
8513 /* .. .. .. ==> 0XF8000120[25:25] = 0x00000001U */
8514 /* .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U */
8515 /* .. .. .. CPU_2XCLKACT = 0x1 */
8516 /* .. .. .. ==> 0XF8000120[26:26] = 0x00000001U */
8517 /* .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
8518 /* .. .. .. CPU_1XCLKACT = 0x1 */
8519 /* .. .. .. ==> 0XF8000120[27:27] = 0x00000001U */
8520 /* .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
8521 /* .. .. .. CPU_PERI_CLKACT = 0x1 */
8522 /* .. .. .. ==> 0XF8000120[28:28] = 0x00000001U */
8523 /* .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
8524 /* .. .. .. */
8525 EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
8526 /* .. .. FINISH: ARM PLL INIT */
8527 /* .. .. START: DDR PLL INIT */
8528 /* .. .. PLL_RES = 0xc */
8529 /* .. .. ==> 0XF8000114[7:4] = 0x0000000CU */
8530 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
8531 /* .. .. PLL_CP = 0x2 */
8532 /* .. .. ==> 0XF8000114[11:8] = 0x00000002U */
8533 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
8534 /* .. .. LOCK_CNT = 0x1db */
8535 /* .. .. ==> 0XF8000114[21:12] = 0x000001DBU */
8536 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001DB000U */
8537 /* .. .. */
8538 EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
8539 /* .. .. .. START: UPDATE FB_DIV */
8540 /* .. .. .. PLL_FDIV = 0x15 */
8541 /* .. .. .. ==> 0XF8000104[18:12] = 0x00000015U */
8542 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00015000U */
8543 /* .. .. .. */
8544 EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
8545 /* .. .. .. FINISH: UPDATE FB_DIV */
8546 /* .. .. .. START: BY PASS PLL */
8547 /* .. .. .. PLL_BYPASS_FORCE = 1 */
8548 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000001U */
8549 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
8550 /* .. .. .. */
8551 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
8552 /* .. .. .. FINISH: BY PASS PLL */
8553 /* .. .. .. START: ASSERT RESET */
8554 /* .. .. .. PLL_RESET = 1 */
8555 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000001U */
8556 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8557 /* .. .. .. */
8558 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
8559 /* .. .. .. FINISH: ASSERT RESET */
8560 /* .. .. .. START: DEASSERT RESET */
8561 /* .. .. .. PLL_RESET = 0 */
8562 /* .. .. .. ==> 0XF8000104[0:0] = 0x00000000U */
8563 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8564 /* .. .. .. */
8565 EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
8566 /* .. .. .. FINISH: DEASSERT RESET */
8567 /* .. .. .. START: CHECK PLL STATUS */
8568 /* .. .. .. DDR_PLL_LOCK = 1 */
8569 /* .. .. .. ==> 0XF800010C[1:1] = 0x00000001U */
8570 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
8571 /* .. .. .. */
8572 EMIT_MASKPOLL(0XF800010C, 0x00000002U),
8573 /* .. .. .. FINISH: CHECK PLL STATUS */
8574 /* .. .. .. START: REMOVE PLL BY PASS */
8575 /* .. .. .. PLL_BYPASS_FORCE = 0 */
8576 /* .. .. .. ==> 0XF8000104[4:4] = 0x00000000U */
8577 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
8578 /* .. .. .. */
8579 EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
8580 /* .. .. .. FINISH: REMOVE PLL BY PASS */
8581 /* .. .. .. DDR_3XCLKACT = 0x1 */
8582 /* .. .. .. ==> 0XF8000124[0:0] = 0x00000001U */
8583 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8584 /* .. .. .. DDR_2XCLKACT = 0x1 */
8585 /* .. .. .. ==> 0XF8000124[1:1] = 0x00000001U */
8586 /* .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
8587 /* .. .. .. DDR_3XCLK_DIVISOR = 0x2 */
8588 /* .. .. .. ==> 0XF8000124[25:20] = 0x00000002U */
8589 /* .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
8590 /* .. .. .. DDR_2XCLK_DIVISOR = 0x3 */
8591 /* .. .. .. ==> 0XF8000124[31:26] = 0x00000003U */
8592 /* .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U */
8593 /* .. .. .. */
8594 EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
8595 /* .. .. FINISH: DDR PLL INIT */
8596 /* .. .. START: IO PLL INIT */
8597 /* .. .. PLL_RES = 0xc */
8598 /* .. .. ==> 0XF8000118[7:4] = 0x0000000CU */
8599 /* .. .. ==> MASK : 0x000000F0U VAL : 0x000000C0U */
8600 /* .. .. PLL_CP = 0x2 */
8601 /* .. .. ==> 0XF8000118[11:8] = 0x00000002U */
8602 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
8603 /* .. .. LOCK_CNT = 0x1f4 */
8604 /* .. .. ==> 0XF8000118[21:12] = 0x000001F4U */
8605 /* .. .. ==> MASK : 0x003FF000U VAL : 0x001F4000U */
8606 /* .. .. */
8607 EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
8608 /* .. .. .. START: UPDATE FB_DIV */
8609 /* .. .. .. PLL_FDIV = 0x14 */
8610 /* .. .. .. ==> 0XF8000108[18:12] = 0x00000014U */
8611 /* .. .. .. ==> MASK : 0x0007F000U VAL : 0x00014000U */
8612 /* .. .. .. */
8613 EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
8614 /* .. .. .. FINISH: UPDATE FB_DIV */
8615 /* .. .. .. START: BY PASS PLL */
8616 /* .. .. .. PLL_BYPASS_FORCE = 1 */
8617 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000001U */
8618 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U */
8619 /* .. .. .. */
8620 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
8621 /* .. .. .. FINISH: BY PASS PLL */
8622 /* .. .. .. START: ASSERT RESET */
8623 /* .. .. .. PLL_RESET = 1 */
8624 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000001U */
8625 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8626 /* .. .. .. */
8627 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
8628 /* .. .. .. FINISH: ASSERT RESET */
8629 /* .. .. .. START: DEASSERT RESET */
8630 /* .. .. .. PLL_RESET = 0 */
8631 /* .. .. .. ==> 0XF8000108[0:0] = 0x00000000U */
8632 /* .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8633 /* .. .. .. */
8634 EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
8635 /* .. .. .. FINISH: DEASSERT RESET */
8636 /* .. .. .. START: CHECK PLL STATUS */
8637 /* .. .. .. IO_PLL_LOCK = 1 */
8638 /* .. .. .. ==> 0XF800010C[2:2] = 0x00000001U */
8639 /* .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
8640 /* .. .. .. */
8641 EMIT_MASKPOLL(0XF800010C, 0x00000004U),
8642 /* .. .. .. FINISH: CHECK PLL STATUS */
8643 /* .. .. .. START: REMOVE PLL BY PASS */
8644 /* .. .. .. PLL_BYPASS_FORCE = 0 */
8645 /* .. .. .. ==> 0XF8000108[4:4] = 0x00000000U */
8646 /* .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
8647 /* .. .. .. */
8648 EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
8649 /* .. .. .. FINISH: REMOVE PLL BY PASS */
8650 /* .. .. FINISH: IO PLL INIT */
8651 /* .. FINISH: PLL SLCR REGISTERS */
8652 /* .. START: LOCK IT BACK */
8653 /* .. LOCK_KEY = 0X767B */
8654 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
8655 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
8656 /* .. */
8657 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
8658 /* .. FINISH: LOCK IT BACK */
8659 /* FINISH: top */
8660 /* */
8661 EMIT_EXIT(),
8662
8663 /* */
8664 };
8665
8666 unsigned long ps7_clock_init_data_1_0[] = {
8667 /* START: top */
8668 /* .. START: SLCR SETTINGS */
8669 /* .. UNLOCK_KEY = 0XDF0D */
8670 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
8671 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
8672 /* .. */
8673 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
8674 /* .. FINISH: SLCR SETTINGS */
8675 /* .. START: CLOCK CONTROL SLCR REGISTERS */
8676 /* .. CLKACT = 0x1 */
8677 /* .. ==> 0XF8000128[0:0] = 0x00000001U */
8678 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8679 /* .. DIVISOR0 = 0x34 */
8680 /* .. ==> 0XF8000128[13:8] = 0x00000034U */
8681 /* .. ==> MASK : 0x00003F00U VAL : 0x00003400U */
8682 /* .. DIVISOR1 = 0x2 */
8683 /* .. ==> 0XF8000128[25:20] = 0x00000002U */
8684 /* .. ==> MASK : 0x03F00000U VAL : 0x00200000U */
8685 /* .. */
8686 EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
8687 /* .. CLKACT = 0x1 */
8688 /* .. ==> 0XF8000138[0:0] = 0x00000001U */
8689 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8690 /* .. SRCSEL = 0x0 */
8691 /* .. ==> 0XF8000138[4:4] = 0x00000000U */
8692 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
8693 /* .. */
8694 EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
8695 /* .. CLKACT = 0x1 */
8696 /* .. ==> 0XF8000140[0:0] = 0x00000001U */
8697 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8698 /* .. SRCSEL = 0x0 */
8699 /* .. ==> 0XF8000140[6:4] = 0x00000000U */
8700 /* .. ==> MASK : 0x00000070U VAL : 0x00000000U */
8701 /* .. DIVISOR = 0x8 */
8702 /* .. ==> 0XF8000140[13:8] = 0x00000008U */
8703 /* .. ==> MASK : 0x00003F00U VAL : 0x00000800U */
8704 /* .. DIVISOR1 = 0x1 */
8705 /* .. ==> 0XF8000140[25:20] = 0x00000001U */
8706 /* .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
8707 /* .. */
8708 EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
8709 /* .. CLKACT = 0x1 */
8710 /* .. ==> 0XF800014C[0:0] = 0x00000001U */
8711 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8712 /* .. SRCSEL = 0x0 */
8713 /* .. ==> 0XF800014C[5:4] = 0x00000000U */
8714 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8715 /* .. DIVISOR = 0x5 */
8716 /* .. ==> 0XF800014C[13:8] = 0x00000005U */
8717 /* .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
8718 /* .. */
8719 EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
8720 /* .. CLKACT0 = 0x1 */
8721 /* .. ==> 0XF8000150[0:0] = 0x00000001U */
8722 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8723 /* .. CLKACT1 = 0x0 */
8724 /* .. ==> 0XF8000150[1:1] = 0x00000000U */
8725 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
8726 /* .. SRCSEL = 0x0 */
8727 /* .. ==> 0XF8000150[5:4] = 0x00000000U */
8728 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8729 /* .. DIVISOR = 0x14 */
8730 /* .. ==> 0XF8000150[13:8] = 0x00000014U */
8731 /* .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
8732 /* .. */
8733 EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00001401U),
8734 /* .. CLKACT0 = 0x0 */
8735 /* .. ==> 0XF8000154[0:0] = 0x00000000U */
8736 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8737 /* .. CLKACT1 = 0x1 */
8738 /* .. ==> 0XF8000154[1:1] = 0x00000001U */
8739 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
8740 /* .. SRCSEL = 0x0 */
8741 /* .. ==> 0XF8000154[5:4] = 0x00000000U */
8742 /* .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8743 /* .. DIVISOR = 0xa */
8744 /* .. ==> 0XF8000154[13:8] = 0x0000000AU */
8745 /* .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
8746 /* .. */
8747 EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A02U),
8748 /* .. .. START: TRACE CLOCK */
8749 /* .. .. FINISH: TRACE CLOCK */
8750 /* .. .. CLKACT = 0x1 */
8751 /* .. .. ==> 0XF8000168[0:0] = 0x00000001U */
8752 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8753 /* .. .. SRCSEL = 0x0 */
8754 /* .. .. ==> 0XF8000168[5:4] = 0x00000000U */
8755 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8756 /* .. .. DIVISOR = 0x5 */
8757 /* .. .. ==> 0XF8000168[13:8] = 0x00000005U */
8758 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
8759 /* .. .. */
8760 EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
8761 /* .. .. SRCSEL = 0x0 */
8762 /* .. .. ==> 0XF8000170[5:4] = 0x00000000U */
8763 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8764 /* .. .. DIVISOR0 = 0xa */
8765 /* .. .. ==> 0XF8000170[13:8] = 0x0000000AU */
8766 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000A00U */
8767 /* .. .. DIVISOR1 = 0x1 */
8768 /* .. .. ==> 0XF8000170[25:20] = 0x00000001U */
8769 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
8770 /* .. .. */
8771 EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00100A00U),
8772 /* .. .. SRCSEL = 0x0 */
8773 /* .. .. ==> 0XF8000180[5:4] = 0x00000000U */
8774 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8775 /* .. .. DIVISOR0 = 0x7 */
8776 /* .. .. ==> 0XF8000180[13:8] = 0x00000007U */
8777 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000700U */
8778 /* .. .. DIVISOR1 = 0x1 */
8779 /* .. .. ==> 0XF8000180[25:20] = 0x00000001U */
8780 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
8781 /* .. .. */
8782 EMIT_MASKWRITE(0XF8000180, 0x03F03F30U, 0x00100700U),
8783 /* .. .. SRCSEL = 0x0 */
8784 /* .. .. ==> 0XF8000190[5:4] = 0x00000000U */
8785 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8786 /* .. .. DIVISOR0 = 0x5 */
8787 /* .. .. ==> 0XF8000190[13:8] = 0x00000005U */
8788 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00000500U */
8789 /* .. .. DIVISOR1 = 0x1 */
8790 /* .. .. ==> 0XF8000190[25:20] = 0x00000001U */
8791 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
8792 /* .. .. */
8793 EMIT_MASKWRITE(0XF8000190, 0x03F03F30U, 0x00100500U),
8794 /* .. .. SRCSEL = 0x0 */
8795 /* .. .. ==> 0XF80001A0[5:4] = 0x00000000U */
8796 /* .. .. ==> MASK : 0x00000030U VAL : 0x00000000U */
8797 /* .. .. DIVISOR0 = 0x14 */
8798 /* .. .. ==> 0XF80001A0[13:8] = 0x00000014U */
8799 /* .. .. ==> MASK : 0x00003F00U VAL : 0x00001400U */
8800 /* .. .. DIVISOR1 = 0x1 */
8801 /* .. .. ==> 0XF80001A0[25:20] = 0x00000001U */
8802 /* .. .. ==> MASK : 0x03F00000U VAL : 0x00100000U */
8803 /* .. .. */
8804 EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U, 0x00101400U),
8805 /* .. .. CLK_621_TRUE = 0x1 */
8806 /* .. .. ==> 0XF80001C4[0:0] = 0x00000001U */
8807 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8808 /* .. .. */
8809 EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
8810 /* .. .. DMA_CPU_2XCLKACT = 0x1 */
8811 /* .. .. ==> 0XF800012C[0:0] = 0x00000001U */
8812 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
8813 /* .. .. USB0_CPU_1XCLKACT = 0x1 */
8814 /* .. .. ==> 0XF800012C[2:2] = 0x00000001U */
8815 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000004U */
8816 /* .. .. USB1_CPU_1XCLKACT = 0x1 */
8817 /* .. .. ==> 0XF800012C[3:3] = 0x00000001U */
8818 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
8819 /* .. .. GEM0_CPU_1XCLKACT = 0x1 */
8820 /* .. .. ==> 0XF800012C[6:6] = 0x00000001U */
8821 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000040U */
8822 /* .. .. GEM1_CPU_1XCLKACT = 0x0 */
8823 /* .. .. ==> 0XF800012C[7:7] = 0x00000000U */
8824 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
8825 /* .. .. SDI0_CPU_1XCLKACT = 0x1 */
8826 /* .. .. ==> 0XF800012C[10:10] = 0x00000001U */
8827 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000400U */
8828 /* .. .. SDI1_CPU_1XCLKACT = 0x0 */
8829 /* .. .. ==> 0XF800012C[11:11] = 0x00000000U */
8830 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
8831 /* .. .. SPI0_CPU_1XCLKACT = 0x0 */
8832 /* .. .. ==> 0XF800012C[14:14] = 0x00000000U */
8833 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
8834 /* .. .. SPI1_CPU_1XCLKACT = 0x0 */
8835 /* .. .. ==> 0XF800012C[15:15] = 0x00000000U */
8836 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
8837 /* .. .. CAN0_CPU_1XCLKACT = 0x0 */
8838 /* .. .. ==> 0XF800012C[16:16] = 0x00000000U */
8839 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
8840 /* .. .. CAN1_CPU_1XCLKACT = 0x0 */
8841 /* .. .. ==> 0XF800012C[17:17] = 0x00000000U */
8842 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
8843 /* .. .. I2C0_CPU_1XCLKACT = 0x1 */
8844 /* .. .. ==> 0XF800012C[18:18] = 0x00000001U */
8845 /* .. .. ==> MASK : 0x00040000U VAL : 0x00040000U */
8846 /* .. .. I2C1_CPU_1XCLKACT = 0x1 */
8847 /* .. .. ==> 0XF800012C[19:19] = 0x00000001U */
8848 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
8849 /* .. .. UART0_CPU_1XCLKACT = 0x0 */
8850 /* .. .. ==> 0XF800012C[20:20] = 0x00000000U */
8851 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
8852 /* .. .. UART1_CPU_1XCLKACT = 0x1 */
8853 /* .. .. ==> 0XF800012C[21:21] = 0x00000001U */
8854 /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
8855 /* .. .. GPIO_CPU_1XCLKACT = 0x1 */
8856 /* .. .. ==> 0XF800012C[22:22] = 0x00000001U */
8857 /* .. .. ==> MASK : 0x00400000U VAL : 0x00400000U */
8858 /* .. .. LQSPI_CPU_1XCLKACT = 0x1 */
8859 /* .. .. ==> 0XF800012C[23:23] = 0x00000001U */
8860 /* .. .. ==> MASK : 0x00800000U VAL : 0x00800000U */
8861 /* .. .. SMC_CPU_1XCLKACT = 0x1 */
8862 /* .. .. ==> 0XF800012C[24:24] = 0x00000001U */
8863 /* .. .. ==> MASK : 0x01000000U VAL : 0x01000000U */
8864 /* .. .. */
8865 EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01EC044DU),
8866 /* .. FINISH: CLOCK CONTROL SLCR REGISTERS */
8867 /* .. START: THIS SHOULD BE BLANK */
8868 /* .. FINISH: THIS SHOULD BE BLANK */
8869 /* .. START: LOCK IT BACK */
8870 /* .. LOCK_KEY = 0X767B */
8871 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
8872 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
8873 /* .. */
8874 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
8875 /* .. FINISH: LOCK IT BACK */
8876 /* FINISH: top */
8877 /* */
8878 EMIT_EXIT(),
8879
8880 /* */
8881 };
8882
8883 unsigned long ps7_ddr_init_data_1_0[] = {
8884 /* START: top */
8885 /* .. START: DDR INITIALIZATION */
8886 /* .. .. START: LOCK DDR */
8887 /* .. .. reg_ddrc_soft_rstb = 0 */
8888 /* .. .. ==> 0XF8006000[0:0] = 0x00000000U */
8889 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
8890 /* .. .. reg_ddrc_powerdown_en = 0x0 */
8891 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
8892 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
8893 /* .. .. reg_ddrc_data_bus_width = 0x0 */
8894 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
8895 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
8896 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
8897 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
8898 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
8899 /* .. .. reg_ddrc_rdwr_idle_gap = 0x1 */
8900 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
8901 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
8902 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
8903 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
8904 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
8905 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
8906 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
8907 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
8908 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
8909 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
8910 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
8911 /* .. .. */
8912 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
8913 /* .. .. FINISH: LOCK DDR */
8914 /* .. .. reg_ddrc_t_rfc_nom_x32 = 0x7f */
8915 /* .. .. ==> 0XF8006004[11:0] = 0x0000007FU */
8916 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x0000007FU */
8917 /* .. .. reg_ddrc_active_ranks = 0x1 */
8918 /* .. .. ==> 0XF8006004[13:12] = 0x00000001U */
8919 /* .. .. ==> MASK : 0x00003000U VAL : 0x00001000U */
8920 /* .. .. reg_ddrc_addrmap_cs_bit0 = 0x0 */
8921 /* .. .. ==> 0XF8006004[18:14] = 0x00000000U */
8922 /* .. .. ==> MASK : 0x0007C000U VAL : 0x00000000U */
8923 /* .. .. reg_ddrc_wr_odt_block = 0x1 */
8924 /* .. .. ==> 0XF8006004[20:19] = 0x00000001U */
8925 /* .. .. ==> MASK : 0x00180000U VAL : 0x00080000U */
8926 /* .. .. reg_ddrc_diff_rank_rd_2cycle_gap = 0x0 */
8927 /* .. .. ==> 0XF8006004[21:21] = 0x00000000U */
8928 /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
8929 /* .. .. reg_ddrc_addrmap_cs_bit1 = 0x0 */
8930 /* .. .. ==> 0XF8006004[26:22] = 0x00000000U */
8931 /* .. .. ==> MASK : 0x07C00000U VAL : 0x00000000U */
8932 /* .. .. reg_ddrc_addrmap_open_bank = 0x0 */
8933 /* .. .. ==> 0XF8006004[27:27] = 0x00000000U */
8934 /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
8935 /* .. .. reg_ddrc_addrmap_4bank_ram = 0x0 */
8936 /* .. .. ==> 0XF8006004[28:28] = 0x00000000U */
8937 /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
8938 /* .. .. */
8939 EMIT_MASKWRITE(0XF8006004, 0x1FFFFFFFU, 0x0008107FU),
8940 /* .. .. reg_ddrc_hpr_min_non_critical_x32 = 0xf */
8941 /* .. .. ==> 0XF8006008[10:0] = 0x0000000FU */
8942 /* .. .. ==> MASK : 0x000007FFU VAL : 0x0000000FU */
8943 /* .. .. reg_ddrc_hpr_max_starve_x32 = 0xf */
8944 /* .. .. ==> 0XF8006008[21:11] = 0x0000000FU */
8945 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00007800U */
8946 /* .. .. reg_ddrc_hpr_xact_run_length = 0xf */
8947 /* .. .. ==> 0XF8006008[25:22] = 0x0000000FU */
8948 /* .. .. ==> MASK : 0x03C00000U VAL : 0x03C00000U */
8949 /* .. .. */
8950 EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
8951 /* .. .. reg_ddrc_lpr_min_non_critical_x32 = 0x1 */
8952 /* .. .. ==> 0XF800600C[10:0] = 0x00000001U */
8953 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
8954 /* .. .. reg_ddrc_lpr_max_starve_x32 = 0x2 */
8955 /* .. .. ==> 0XF800600C[21:11] = 0x00000002U */
8956 /* .. .. ==> MASK : 0x003FF800U VAL : 0x00001000U */
8957 /* .. .. reg_ddrc_lpr_xact_run_length = 0x8 */
8958 /* .. .. ==> 0XF800600C[25:22] = 0x00000008U */
8959 /* .. .. ==> MASK : 0x03C00000U VAL : 0x02000000U */
8960 /* .. .. */
8961 EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
8962 /* .. .. reg_ddrc_w_min_non_critical_x32 = 0x1 */
8963 /* .. .. ==> 0XF8006010[10:0] = 0x00000001U */
8964 /* .. .. ==> MASK : 0x000007FFU VAL : 0x00000001U */
8965 /* .. .. reg_ddrc_w_xact_run_length = 0x8 */
8966 /* .. .. ==> 0XF8006010[14:11] = 0x00000008U */
8967 /* .. .. ==> MASK : 0x00007800U VAL : 0x00004000U */
8968 /* .. .. reg_ddrc_w_max_starve_x32 = 0x2 */
8969 /* .. .. ==> 0XF8006010[25:15] = 0x00000002U */
8970 /* .. .. ==> MASK : 0x03FF8000U VAL : 0x00010000U */
8971 /* .. .. */
8972 EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
8973 /* .. .. reg_ddrc_t_rc = 0x1a */
8974 /* .. .. ==> 0XF8006014[5:0] = 0x0000001AU */
8975 /* .. .. ==> MASK : 0x0000003FU VAL : 0x0000001AU */
8976 /* .. .. reg_ddrc_t_rfc_min = 0x54 */
8977 /* .. .. ==> 0XF8006014[13:6] = 0x00000054U */
8978 /* .. .. ==> MASK : 0x00003FC0U VAL : 0x00001500U */
8979 /* .. .. reg_ddrc_post_selfref_gap_x32 = 0x10 */
8980 /* .. .. ==> 0XF8006014[20:14] = 0x00000010U */
8981 /* .. .. ==> MASK : 0x001FC000U VAL : 0x00040000U */
8982 /* .. .. */
8983 EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004151AU),
8984 /* .. .. reg_ddrc_wr2pre = 0x12 */
8985 /* .. .. ==> 0XF8006018[4:0] = 0x00000012U */
8986 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000012U */
8987 /* .. .. reg_ddrc_powerdown_to_x32 = 0x6 */
8988 /* .. .. ==> 0XF8006018[9:5] = 0x00000006U */
8989 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000C0U */
8990 /* .. .. reg_ddrc_t_faw = 0x15 */
8991 /* .. .. ==> 0XF8006018[15:10] = 0x00000015U */
8992 /* .. .. ==> MASK : 0x0000FC00U VAL : 0x00005400U */
8993 /* .. .. reg_ddrc_t_ras_max = 0x23 */
8994 /* .. .. ==> 0XF8006018[21:16] = 0x00000023U */
8995 /* .. .. ==> MASK : 0x003F0000U VAL : 0x00230000U */
8996 /* .. .. reg_ddrc_t_ras_min = 0x13 */
8997 /* .. .. ==> 0XF8006018[26:22] = 0x00000013U */
8998 /* .. .. ==> MASK : 0x07C00000U VAL : 0x04C00000U */
8999 /* .. .. reg_ddrc_t_cke = 0x4 */
9000 /* .. .. ==> 0XF8006018[31:28] = 0x00000004U */
9001 /* .. .. ==> MASK : 0xF0000000U VAL : 0x40000000U */
9002 /* .. .. */
9003 EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E354D2U),
9004 /* .. .. reg_ddrc_write_latency = 0x5 */
9005 /* .. .. ==> 0XF800601C[4:0] = 0x00000005U */
9006 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000005U */
9007 /* .. .. reg_ddrc_rd2wr = 0x7 */
9008 /* .. .. ==> 0XF800601C[9:5] = 0x00000007U */
9009 /* .. .. ==> MASK : 0x000003E0U VAL : 0x000000E0U */
9010 /* .. .. reg_ddrc_wr2rd = 0xe */
9011 /* .. .. ==> 0XF800601C[14:10] = 0x0000000EU */
9012 /* .. .. ==> MASK : 0x00007C00U VAL : 0x00003800U */
9013 /* .. .. reg_ddrc_t_xp = 0x4 */
9014 /* .. .. ==> 0XF800601C[19:15] = 0x00000004U */
9015 /* .. .. ==> MASK : 0x000F8000U VAL : 0x00020000U */
9016 /* .. .. reg_ddrc_pad_pd = 0x0 */
9017 /* .. .. ==> 0XF800601C[22:20] = 0x00000000U */
9018 /* .. .. ==> MASK : 0x00700000U VAL : 0x00000000U */
9019 /* .. .. reg_ddrc_rd2pre = 0x4 */
9020 /* .. .. ==> 0XF800601C[27:23] = 0x00000004U */
9021 /* .. .. ==> MASK : 0x0F800000U VAL : 0x02000000U */
9022 /* .. .. reg_ddrc_t_rcd = 0x7 */
9023 /* .. .. ==> 0XF800601C[31:28] = 0x00000007U */
9024 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
9025 /* .. .. */
9026 EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
9027 /* .. .. reg_ddrc_t_ccd = 0x4 */
9028 /* .. .. ==> 0XF8006020[4:2] = 0x00000004U */
9029 /* .. .. ==> MASK : 0x0000001CU VAL : 0x00000010U */
9030 /* .. .. reg_ddrc_t_rrd = 0x6 */
9031 /* .. .. ==> 0XF8006020[7:5] = 0x00000006U */
9032 /* .. .. ==> MASK : 0x000000E0U VAL : 0x000000C0U */
9033 /* .. .. reg_ddrc_refresh_margin = 0x2 */
9034 /* .. .. ==> 0XF8006020[11:8] = 0x00000002U */
9035 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U */
9036 /* .. .. reg_ddrc_t_rp = 0x7 */
9037 /* .. .. ==> 0XF8006020[15:12] = 0x00000007U */
9038 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00007000U */
9039 /* .. .. reg_ddrc_refresh_to_x32 = 0x8 */
9040 /* .. .. ==> 0XF8006020[20:16] = 0x00000008U */
9041 /* .. .. ==> MASK : 0x001F0000U VAL : 0x00080000U */
9042 /* .. .. reg_ddrc_sdram = 0x1 */
9043 /* .. .. ==> 0XF8006020[21:21] = 0x00000001U */
9044 /* .. .. ==> MASK : 0x00200000U VAL : 0x00200000U */
9045 /* .. .. reg_ddrc_mobile = 0x0 */
9046 /* .. .. ==> 0XF8006020[22:22] = 0x00000000U */
9047 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
9048 /* .. .. reg_ddrc_clock_stop_en = 0x0 */
9049 /* .. .. ==> 0XF8006020[23:23] = 0x00000000U */
9050 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
9051 /* .. .. reg_ddrc_read_latency = 0x7 */
9052 /* .. .. ==> 0XF8006020[28:24] = 0x00000007U */
9053 /* .. .. ==> MASK : 0x1F000000U VAL : 0x07000000U */
9054 /* .. .. reg_phy_mode_ddr1_ddr2 = 0x1 */
9055 /* .. .. ==> 0XF8006020[29:29] = 0x00000001U */
9056 /* .. .. ==> MASK : 0x20000000U VAL : 0x20000000U */
9057 /* .. .. reg_ddrc_dis_pad_pd = 0x0 */
9058 /* .. .. ==> 0XF8006020[30:30] = 0x00000000U */
9059 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
9060 /* .. .. reg_ddrc_loopback = 0x0 */
9061 /* .. .. ==> 0XF8006020[31:31] = 0x00000000U */
9062 /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
9063 /* .. .. */
9064 EMIT_MASKWRITE(0XF8006020, 0xFFFFFFFCU, 0x272872D0U),
9065 /* .. .. reg_ddrc_en_2t_timing_mode = 0x0 */
9066 /* .. .. ==> 0XF8006024[0:0] = 0x00000000U */
9067 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9068 /* .. .. reg_ddrc_prefer_write = 0x0 */
9069 /* .. .. ==> 0XF8006024[1:1] = 0x00000000U */
9070 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9071 /* .. .. reg_ddrc_max_rank_rd = 0xf */
9072 /* .. .. ==> 0XF8006024[5:2] = 0x0000000FU */
9073 /* .. .. ==> MASK : 0x0000003CU VAL : 0x0000003CU */
9074 /* .. .. reg_ddrc_mr_wr = 0x0 */
9075 /* .. .. ==> 0XF8006024[6:6] = 0x00000000U */
9076 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
9077 /* .. .. reg_ddrc_mr_addr = 0x0 */
9078 /* .. .. ==> 0XF8006024[8:7] = 0x00000000U */
9079 /* .. .. ==> MASK : 0x00000180U VAL : 0x00000000U */
9080 /* .. .. reg_ddrc_mr_data = 0x0 */
9081 /* .. .. ==> 0XF8006024[24:9] = 0x00000000U */
9082 /* .. .. ==> MASK : 0x01FFFE00U VAL : 0x00000000U */
9083 /* .. .. ddrc_reg_mr_wr_busy = 0x0 */
9084 /* .. .. ==> 0XF8006024[25:25] = 0x00000000U */
9085 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
9086 /* .. .. reg_ddrc_mr_type = 0x0 */
9087 /* .. .. ==> 0XF8006024[26:26] = 0x00000000U */
9088 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
9089 /* .. .. reg_ddrc_mr_rdata_valid = 0x0 */
9090 /* .. .. ==> 0XF8006024[27:27] = 0x00000000U */
9091 /* .. .. ==> MASK : 0x08000000U VAL : 0x00000000U */
9092 /* .. .. */
9093 EMIT_MASKWRITE(0XF8006024, 0x0FFFFFFFU, 0x0000003CU),
9094 /* .. .. reg_ddrc_final_wait_x32 = 0x7 */
9095 /* .. .. ==> 0XF8006028[6:0] = 0x00000007U */
9096 /* .. .. ==> MASK : 0x0000007FU VAL : 0x00000007U */
9097 /* .. .. reg_ddrc_pre_ocd_x32 = 0x0 */
9098 /* .. .. ==> 0XF8006028[10:7] = 0x00000000U */
9099 /* .. .. ==> MASK : 0x00000780U VAL : 0x00000000U */
9100 /* .. .. reg_ddrc_t_mrd = 0x4 */
9101 /* .. .. ==> 0XF8006028[13:11] = 0x00000004U */
9102 /* .. .. ==> MASK : 0x00003800U VAL : 0x00002000U */
9103 /* .. .. */
9104 EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
9105 /* .. .. reg_ddrc_emr2 = 0x8 */
9106 /* .. .. ==> 0XF800602C[15:0] = 0x00000008U */
9107 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000008U */
9108 /* .. .. reg_ddrc_emr3 = 0x0 */
9109 /* .. .. ==> 0XF800602C[31:16] = 0x00000000U */
9110 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00000000U */
9111 /* .. .. */
9112 EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
9113 /* .. .. reg_ddrc_mr = 0x930 */
9114 /* .. .. ==> 0XF8006030[15:0] = 0x00000930U */
9115 /* .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000930U */
9116 /* .. .. reg_ddrc_emr = 0x4 */
9117 /* .. .. ==> 0XF8006030[31:16] = 0x00000004U */
9118 /* .. .. ==> MASK : 0xFFFF0000U VAL : 0x00040000U */
9119 /* .. .. */
9120 EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
9121 /* .. .. reg_ddrc_burst_rdwr = 0x4 */
9122 /* .. .. ==> 0XF8006034[3:0] = 0x00000004U */
9123 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000004U */
9124 /* .. .. reg_ddrc_pre_cke_x1024 = 0x167 */
9125 /* .. .. ==> 0XF8006034[13:4] = 0x00000167U */
9126 /* .. .. ==> MASK : 0x00003FF0U VAL : 0x00001670U */
9127 /* .. .. reg_ddrc_post_cke_x1024 = 0x1 */
9128 /* .. .. ==> 0XF8006034[25:16] = 0x00000001U */
9129 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00010000U */
9130 /* .. .. reg_ddrc_burstchop = 0x0 */
9131 /* .. .. ==> 0XF8006034[28:28] = 0x00000000U */
9132 /* .. .. ==> MASK : 0x10000000U VAL : 0x00000000U */
9133 /* .. .. */
9134 EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x00011674U),
9135 /* .. .. reg_ddrc_force_low_pri_n = 0x0 */
9136 /* .. .. ==> 0XF8006038[0:0] = 0x00000000U */
9137 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9138 /* .. .. reg_ddrc_dis_dq = 0x0 */
9139 /* .. .. ==> 0XF8006038[1:1] = 0x00000000U */
9140 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9141 /* .. .. reg_phy_debug_mode = 0x0 */
9142 /* .. .. ==> 0XF8006038[6:6] = 0x00000000U */
9143 /* .. .. ==> MASK : 0x00000040U VAL : 0x00000000U */
9144 /* .. .. reg_phy_wr_level_start = 0x0 */
9145 /* .. .. ==> 0XF8006038[7:7] = 0x00000000U */
9146 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
9147 /* .. .. reg_phy_rd_level_start = 0x0 */
9148 /* .. .. ==> 0XF8006038[8:8] = 0x00000000U */
9149 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
9150 /* .. .. reg_phy_dq0_wait_t = 0x0 */
9151 /* .. .. ==> 0XF8006038[12:9] = 0x00000000U */
9152 /* .. .. ==> MASK : 0x00001E00U VAL : 0x00000000U */
9153 /* .. .. */
9154 EMIT_MASKWRITE(0XF8006038, 0x00001FC3U, 0x00000000U),
9155 /* .. .. reg_ddrc_addrmap_bank_b0 = 0x7 */
9156 /* .. .. ==> 0XF800603C[3:0] = 0x00000007U */
9157 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000007U */
9158 /* .. .. reg_ddrc_addrmap_bank_b1 = 0x7 */
9159 /* .. .. ==> 0XF800603C[7:4] = 0x00000007U */
9160 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000070U */
9161 /* .. .. reg_ddrc_addrmap_bank_b2 = 0x7 */
9162 /* .. .. ==> 0XF800603C[11:8] = 0x00000007U */
9163 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000700U */
9164 /* .. .. reg_ddrc_addrmap_col_b5 = 0x0 */
9165 /* .. .. ==> 0XF800603C[15:12] = 0x00000000U */
9166 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
9167 /* .. .. reg_ddrc_addrmap_col_b6 = 0x0 */
9168 /* .. .. ==> 0XF800603C[19:16] = 0x00000000U */
9169 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
9170 /* .. .. */
9171 EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
9172 /* .. .. reg_ddrc_addrmap_col_b2 = 0x0 */
9173 /* .. .. ==> 0XF8006040[3:0] = 0x00000000U */
9174 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
9175 /* .. .. reg_ddrc_addrmap_col_b3 = 0x0 */
9176 /* .. .. ==> 0XF8006040[7:4] = 0x00000000U */
9177 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
9178 /* .. .. reg_ddrc_addrmap_col_b4 = 0x0 */
9179 /* .. .. ==> 0XF8006040[11:8] = 0x00000000U */
9180 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
9181 /* .. .. reg_ddrc_addrmap_col_b7 = 0x0 */
9182 /* .. .. ==> 0XF8006040[15:12] = 0x00000000U */
9183 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00000000U */
9184 /* .. .. reg_ddrc_addrmap_col_b8 = 0x0 */
9185 /* .. .. ==> 0XF8006040[19:16] = 0x00000000U */
9186 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00000000U */
9187 /* .. .. reg_ddrc_addrmap_col_b9 = 0xf */
9188 /* .. .. ==> 0XF8006040[23:20] = 0x0000000FU */
9189 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
9190 /* .. .. reg_ddrc_addrmap_col_b10 = 0xf */
9191 /* .. .. ==> 0XF8006040[27:24] = 0x0000000FU */
9192 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
9193 /* .. .. reg_ddrc_addrmap_col_b11 = 0xf */
9194 /* .. .. ==> 0XF8006040[31:28] = 0x0000000FU */
9195 /* .. .. ==> MASK : 0xF0000000U VAL : 0xF0000000U */
9196 /* .. .. */
9197 EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
9198 /* .. .. reg_ddrc_addrmap_row_b0 = 0x6 */
9199 /* .. .. ==> 0XF8006044[3:0] = 0x00000006U */
9200 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000006U */
9201 /* .. .. reg_ddrc_addrmap_row_b1 = 0x6 */
9202 /* .. .. ==> 0XF8006044[7:4] = 0x00000006U */
9203 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000060U */
9204 /* .. .. reg_ddrc_addrmap_row_b2_11 = 0x6 */
9205 /* .. .. ==> 0XF8006044[11:8] = 0x00000006U */
9206 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000600U */
9207 /* .. .. reg_ddrc_addrmap_row_b12 = 0x6 */
9208 /* .. .. ==> 0XF8006044[15:12] = 0x00000006U */
9209 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00006000U */
9210 /* .. .. reg_ddrc_addrmap_row_b13 = 0x6 */
9211 /* .. .. ==> 0XF8006044[19:16] = 0x00000006U */
9212 /* .. .. ==> MASK : 0x000F0000U VAL : 0x00060000U */
9213 /* .. .. reg_ddrc_addrmap_row_b14 = 0xf */
9214 /* .. .. ==> 0XF8006044[23:20] = 0x0000000FU */
9215 /* .. .. ==> MASK : 0x00F00000U VAL : 0x00F00000U */
9216 /* .. .. reg_ddrc_addrmap_row_b15 = 0xf */
9217 /* .. .. ==> 0XF8006044[27:24] = 0x0000000FU */
9218 /* .. .. ==> MASK : 0x0F000000U VAL : 0x0F000000U */
9219 /* .. .. */
9220 EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0FF66666U),
9221 /* .. .. reg_ddrc_rank0_rd_odt = 0x0 */
9222 /* .. .. ==> 0XF8006048[2:0] = 0x00000000U */
9223 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
9224 /* .. .. reg_ddrc_rank0_wr_odt = 0x1 */
9225 /* .. .. ==> 0XF8006048[5:3] = 0x00000001U */
9226 /* .. .. ==> MASK : 0x00000038U VAL : 0x00000008U */
9227 /* .. .. reg_ddrc_rank1_rd_odt = 0x1 */
9228 /* .. .. ==> 0XF8006048[8:6] = 0x00000001U */
9229 /* .. .. ==> MASK : 0x000001C0U VAL : 0x00000040U */
9230 /* .. .. reg_ddrc_rank1_wr_odt = 0x1 */
9231 /* .. .. ==> 0XF8006048[11:9] = 0x00000001U */
9232 /* .. .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
9233 /* .. .. reg_phy_rd_local_odt = 0x0 */
9234 /* .. .. ==> 0XF8006048[13:12] = 0x00000000U */
9235 /* .. .. ==> MASK : 0x00003000U VAL : 0x00000000U */
9236 /* .. .. reg_phy_wr_local_odt = 0x3 */
9237 /* .. .. ==> 0XF8006048[15:14] = 0x00000003U */
9238 /* .. .. ==> MASK : 0x0000C000U VAL : 0x0000C000U */
9239 /* .. .. reg_phy_idle_local_odt = 0x3 */
9240 /* .. .. ==> 0XF8006048[17:16] = 0x00000003U */
9241 /* .. .. ==> MASK : 0x00030000U VAL : 0x00030000U */
9242 /* .. .. reg_ddrc_rank2_rd_odt = 0x0 */
9243 /* .. .. ==> 0XF8006048[20:18] = 0x00000000U */
9244 /* .. .. ==> MASK : 0x001C0000U VAL : 0x00000000U */
9245 /* .. .. reg_ddrc_rank2_wr_odt = 0x0 */
9246 /* .. .. ==> 0XF8006048[23:21] = 0x00000000U */
9247 /* .. .. ==> MASK : 0x00E00000U VAL : 0x00000000U */
9248 /* .. .. reg_ddrc_rank3_rd_odt = 0x0 */
9249 /* .. .. ==> 0XF8006048[26:24] = 0x00000000U */
9250 /* .. .. ==> MASK : 0x07000000U VAL : 0x00000000U */
9251 /* .. .. reg_ddrc_rank3_wr_odt = 0x0 */
9252 /* .. .. ==> 0XF8006048[29:27] = 0x00000000U */
9253 /* .. .. ==> MASK : 0x38000000U VAL : 0x00000000U */
9254 /* .. .. */
9255 EMIT_MASKWRITE(0XF8006048, 0x3FFFFFFFU, 0x0003C248U),
9256 /* .. .. reg_phy_rd_cmd_to_data = 0x0 */
9257 /* .. .. ==> 0XF8006050[3:0] = 0x00000000U */
9258 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
9259 /* .. .. reg_phy_wr_cmd_to_data = 0x0 */
9260 /* .. .. ==> 0XF8006050[7:4] = 0x00000000U */
9261 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
9262 /* .. .. reg_phy_rdc_we_to_re_delay = 0x8 */
9263 /* .. .. ==> 0XF8006050[11:8] = 0x00000008U */
9264 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000800U */
9265 /* .. .. reg_phy_rdc_fifo_rst_disable = 0x0 */
9266 /* .. .. ==> 0XF8006050[15:15] = 0x00000000U */
9267 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
9268 /* .. .. reg_phy_use_fixed_re = 0x1 */
9269 /* .. .. ==> 0XF8006050[16:16] = 0x00000001U */
9270 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
9271 /* .. .. reg_phy_rdc_fifo_rst_err_cnt_clr = 0x0 */
9272 /* .. .. ==> 0XF8006050[17:17] = 0x00000000U */
9273 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9274 /* .. .. reg_phy_dis_phy_ctrl_rstn = 0x0 */
9275 /* .. .. ==> 0XF8006050[18:18] = 0x00000000U */
9276 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9277 /* .. .. reg_phy_clk_stall_level = 0x0 */
9278 /* .. .. ==> 0XF8006050[19:19] = 0x00000000U */
9279 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
9280 /* .. .. reg_phy_gatelvl_num_of_dq0 = 0x7 */
9281 /* .. .. ==> 0XF8006050[27:24] = 0x00000007U */
9282 /* .. .. ==> MASK : 0x0F000000U VAL : 0x07000000U */
9283 /* .. .. reg_phy_wrlvl_num_of_dq0 = 0x7 */
9284 /* .. .. ==> 0XF8006050[31:28] = 0x00000007U */
9285 /* .. .. ==> MASK : 0xF0000000U VAL : 0x70000000U */
9286 /* .. .. */
9287 EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
9288 /* .. .. reg_ddrc_dll_calib_to_min_x1024 = 0x1 */
9289 /* .. .. ==> 0XF8006058[7:0] = 0x00000001U */
9290 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000001U */
9291 /* .. .. reg_ddrc_dll_calib_to_max_x1024 = 0x1 */
9292 /* .. .. ==> 0XF8006058[15:8] = 0x00000001U */
9293 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000100U */
9294 /* .. .. reg_ddrc_dis_dll_calib = 0x0 */
9295 /* .. .. ==> 0XF8006058[16:16] = 0x00000000U */
9296 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9297 /* .. .. */
9298 EMIT_MASKWRITE(0XF8006058, 0x0001FFFFU, 0x00000101U),
9299 /* .. .. reg_ddrc_rd_odt_delay = 0x3 */
9300 /* .. .. ==> 0XF800605C[3:0] = 0x00000003U */
9301 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000003U */
9302 /* .. .. reg_ddrc_wr_odt_delay = 0x0 */
9303 /* .. .. ==> 0XF800605C[7:4] = 0x00000000U */
9304 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
9305 /* .. .. reg_ddrc_rd_odt_hold = 0x0 */
9306 /* .. .. ==> 0XF800605C[11:8] = 0x00000000U */
9307 /* .. .. ==> MASK : 0x00000F00U VAL : 0x00000000U */
9308 /* .. .. reg_ddrc_wr_odt_hold = 0x5 */
9309 /* .. .. ==> 0XF800605C[15:12] = 0x00000005U */
9310 /* .. .. ==> MASK : 0x0000F000U VAL : 0x00005000U */
9311 /* .. .. */
9312 EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
9313 /* .. .. reg_ddrc_pageclose = 0x0 */
9314 /* .. .. ==> 0XF8006060[0:0] = 0x00000000U */
9315 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9316 /* .. .. reg_ddrc_lpr_num_entries = 0x1f */
9317 /* .. .. ==> 0XF8006060[6:1] = 0x0000001FU */
9318 /* .. .. ==> MASK : 0x0000007EU VAL : 0x0000003EU */
9319 /* .. .. reg_ddrc_auto_pre_en = 0x0 */
9320 /* .. .. ==> 0XF8006060[7:7] = 0x00000000U */
9321 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000000U */
9322 /* .. .. reg_ddrc_refresh_update_level = 0x0 */
9323 /* .. .. ==> 0XF8006060[8:8] = 0x00000000U */
9324 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
9325 /* .. .. reg_ddrc_dis_wc = 0x0 */
9326 /* .. .. ==> 0XF8006060[9:9] = 0x00000000U */
9327 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
9328 /* .. .. reg_ddrc_dis_collision_page_opt = 0x0 */
9329 /* .. .. ==> 0XF8006060[10:10] = 0x00000000U */
9330 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9331 /* .. .. reg_ddrc_selfref_en = 0x0 */
9332 /* .. .. ==> 0XF8006060[12:12] = 0x00000000U */
9333 /* .. .. ==> MASK : 0x00001000U VAL : 0x00000000U */
9334 /* .. .. */
9335 EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
9336 /* .. .. reg_ddrc_go2critical_hysteresis = 0x0 */
9337 /* .. .. ==> 0XF8006064[12:5] = 0x00000000U */
9338 /* .. .. ==> MASK : 0x00001FE0U VAL : 0x00000000U */
9339 /* .. .. reg_arb_go2critical_en = 0x1 */
9340 /* .. .. ==> 0XF8006064[17:17] = 0x00000001U */
9341 /* .. .. ==> MASK : 0x00020000U VAL : 0x00020000U */
9342 /* .. .. */
9343 EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
9344 /* .. .. reg_ddrc_wrlvl_ww = 0x41 */
9345 /* .. .. ==> 0XF8006068[7:0] = 0x00000041U */
9346 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000041U */
9347 /* .. .. reg_ddrc_rdlvl_rr = 0x41 */
9348 /* .. .. ==> 0XF8006068[15:8] = 0x00000041U */
9349 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00004100U */
9350 /* .. .. reg_ddrc_dfi_t_wlmrd = 0x28 */
9351 /* .. .. ==> 0XF8006068[25:16] = 0x00000028U */
9352 /* .. .. ==> MASK : 0x03FF0000U VAL : 0x00280000U */
9353 /* .. .. */
9354 EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
9355 /* .. .. dfi_t_ctrlupd_interval_min_x1024 = 0x10 */
9356 /* .. .. ==> 0XF800606C[7:0] = 0x00000010U */
9357 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000010U */
9358 /* .. .. dfi_t_ctrlupd_interval_max_x1024 = 0x16 */
9359 /* .. .. ==> 0XF800606C[15:8] = 0x00000016U */
9360 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00001600U */
9361 /* .. .. */
9362 EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
9363 /* .. .. refresh_timer0_start_value_x32 = 0x0 */
9364 /* .. .. ==> 0XF80060A0[11:0] = 0x00000000U */
9365 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000000U */
9366 /* .. .. refresh_timer1_start_value_x32 = 0x8 */
9367 /* .. .. ==> 0XF80060A0[23:12] = 0x00000008U */
9368 /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00008000U */
9369 /* .. .. */
9370 EMIT_MASKWRITE(0XF80060A0, 0x00FFFFFFU, 0x00008000U),
9371 /* .. .. reg_ddrc_dis_auto_zq = 0x0 */
9372 /* .. .. ==> 0XF80060A4[0:0] = 0x00000000U */
9373 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9374 /* .. .. reg_ddrc_ddr3 = 0x1 */
9375 /* .. .. ==> 0XF80060A4[1:1] = 0x00000001U */
9376 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
9377 /* .. .. reg_ddrc_t_mod = 0x200 */
9378 /* .. .. ==> 0XF80060A4[11:2] = 0x00000200U */
9379 /* .. .. ==> MASK : 0x00000FFCU VAL : 0x00000800U */
9380 /* .. .. reg_ddrc_t_zq_long_nop = 0x200 */
9381 /* .. .. ==> 0XF80060A4[21:12] = 0x00000200U */
9382 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00200000U */
9383 /* .. .. reg_ddrc_t_zq_short_nop = 0x40 */
9384 /* .. .. ==> 0XF80060A4[31:22] = 0x00000040U */
9385 /* .. .. ==> MASK : 0xFFC00000U VAL : 0x10000000U */
9386 /* .. .. */
9387 EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
9388 /* .. .. t_zq_short_interval_x1024 = 0xc845 */
9389 /* .. .. ==> 0XF80060A8[19:0] = 0x0000C845U */
9390 /* .. .. ==> MASK : 0x000FFFFFU VAL : 0x0000C845U */
9391 /* .. .. dram_rstn_x1024 = 0x67 */
9392 /* .. .. ==> 0XF80060A8[27:20] = 0x00000067U */
9393 /* .. .. ==> MASK : 0x0FF00000U VAL : 0x06700000U */
9394 /* .. .. */
9395 EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0670C845U),
9396 /* .. .. deeppowerdown_en = 0x0 */
9397 /* .. .. ==> 0XF80060AC[0:0] = 0x00000000U */
9398 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9399 /* .. .. deeppowerdown_to_x1024 = 0xff */
9400 /* .. .. ==> 0XF80060AC[8:1] = 0x000000FFU */
9401 /* .. .. ==> MASK : 0x000001FEU VAL : 0x000001FEU */
9402 /* .. .. */
9403 EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
9404 /* .. .. dfi_wrlvl_max_x1024 = 0xfff */
9405 /* .. .. ==> 0XF80060B0[11:0] = 0x00000FFFU */
9406 /* .. .. ==> MASK : 0x00000FFFU VAL : 0x00000FFFU */
9407 /* .. .. dfi_rdlvl_max_x1024 = 0xfff */
9408 /* .. .. ==> 0XF80060B0[23:12] = 0x00000FFFU */
9409 /* .. .. ==> MASK : 0x00FFF000U VAL : 0x00FFF000U */
9410 /* .. .. ddrc_reg_twrlvl_max_error = 0x0 */
9411 /* .. .. ==> 0XF80060B0[24:24] = 0x00000000U */
9412 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
9413 /* .. .. ddrc_reg_trdlvl_max_error = 0x0 */
9414 /* .. .. ==> 0XF80060B0[25:25] = 0x00000000U */
9415 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
9416 /* .. .. reg_ddrc_dfi_wr_level_en = 0x1 */
9417 /* .. .. ==> 0XF80060B0[26:26] = 0x00000001U */
9418 /* .. .. ==> MASK : 0x04000000U VAL : 0x04000000U */
9419 /* .. .. reg_ddrc_dfi_rd_dqs_gate_level = 0x1 */
9420 /* .. .. ==> 0XF80060B0[27:27] = 0x00000001U */
9421 /* .. .. ==> MASK : 0x08000000U VAL : 0x08000000U */
9422 /* .. .. reg_ddrc_dfi_rd_data_eye_train = 0x1 */
9423 /* .. .. ==> 0XF80060B0[28:28] = 0x00000001U */
9424 /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
9425 /* .. .. */
9426 EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
9427 /* .. .. reg_ddrc_2t_delay = 0x0 */
9428 /* .. .. ==> 0XF80060B4[8:0] = 0x00000000U */
9429 /* .. .. ==> MASK : 0x000001FFU VAL : 0x00000000U */
9430 /* .. .. reg_ddrc_skip_ocd = 0x1 */
9431 /* .. .. ==> 0XF80060B4[9:9] = 0x00000001U */
9432 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000200U */
9433 /* .. .. reg_ddrc_dis_pre_bypass = 0x0 */
9434 /* .. .. ==> 0XF80060B4[10:10] = 0x00000000U */
9435 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9436 /* .. .. */
9437 EMIT_MASKWRITE(0XF80060B4, 0x000007FFU, 0x00000200U),
9438 /* .. .. reg_ddrc_dfi_t_rddata_en = 0x6 */
9439 /* .. .. ==> 0XF80060B8[4:0] = 0x00000006U */
9440 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000006U */
9441 /* .. .. reg_ddrc_dfi_t_ctrlup_min = 0x3 */
9442 /* .. .. ==> 0XF80060B8[14:5] = 0x00000003U */
9443 /* .. .. ==> MASK : 0x00007FE0U VAL : 0x00000060U */
9444 /* .. .. reg_ddrc_dfi_t_ctrlup_max = 0x40 */
9445 /* .. .. ==> 0XF80060B8[24:15] = 0x00000040U */
9446 /* .. .. ==> MASK : 0x01FF8000U VAL : 0x00200000U */
9447 /* .. .. */
9448 EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
9449 /* .. .. START: RESET ECC ERROR */
9450 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 1 */
9451 /* .. .. ==> 0XF80060C4[0:0] = 0x00000001U */
9452 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
9453 /* .. .. Clear_Correctable_DRAM_ECC_error = 1 */
9454 /* .. .. ==> 0XF80060C4[1:1] = 0x00000001U */
9455 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
9456 /* .. .. */
9457 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000003U),
9458 /* .. .. FINISH: RESET ECC ERROR */
9459 /* .. .. Clear_Uncorrectable_DRAM_ECC_error = 0x0 */
9460 /* .. .. ==> 0XF80060C4[0:0] = 0x00000000U */
9461 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9462 /* .. .. Clear_Correctable_DRAM_ECC_error = 0x0 */
9463 /* .. .. ==> 0XF80060C4[1:1] = 0x00000000U */
9464 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9465 /* .. .. */
9466 EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
9467 /* .. .. CORR_ECC_LOG_VALID = 0x0 */
9468 /* .. .. ==> 0XF80060C8[0:0] = 0x00000000U */
9469 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9470 /* .. .. ECC_CORRECTED_BIT_NUM = 0x0 */
9471 /* .. .. ==> 0XF80060C8[7:1] = 0x00000000U */
9472 /* .. .. ==> MASK : 0x000000FEU VAL : 0x00000000U */
9473 /* .. .. */
9474 EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
9475 /* .. .. UNCORR_ECC_LOG_VALID = 0x0 */
9476 /* .. .. ==> 0XF80060DC[0:0] = 0x00000000U */
9477 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9478 /* .. .. */
9479 EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
9480 /* .. .. STAT_NUM_CORR_ERR = 0x0 */
9481 /* .. .. ==> 0XF80060F0[15:8] = 0x00000000U */
9482 /* .. .. ==> MASK : 0x0000FF00U VAL : 0x00000000U */
9483 /* .. .. STAT_NUM_UNCORR_ERR = 0x0 */
9484 /* .. .. ==> 0XF80060F0[7:0] = 0x00000000U */
9485 /* .. .. ==> MASK : 0x000000FFU VAL : 0x00000000U */
9486 /* .. .. */
9487 EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
9488 /* .. .. reg_ddrc_ecc_mode = 0x0 */
9489 /* .. .. ==> 0XF80060F4[2:0] = 0x00000000U */
9490 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000000U */
9491 /* .. .. reg_ddrc_dis_scrub = 0x1 */
9492 /* .. .. ==> 0XF80060F4[3:3] = 0x00000001U */
9493 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000008U */
9494 /* .. .. */
9495 EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
9496 /* .. .. reg_phy_dif_on = 0x0 */
9497 /* .. .. ==> 0XF8006114[3:0] = 0x00000000U */
9498 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000000U */
9499 /* .. .. reg_phy_dif_off = 0x0 */
9500 /* .. .. ==> 0XF8006114[7:4] = 0x00000000U */
9501 /* .. .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
9502 /* .. .. */
9503 EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
9504 /* .. .. reg_phy_data_slice_in_use = 0x1 */
9505 /* .. .. ==> 0XF8006118[0:0] = 0x00000001U */
9506 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
9507 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
9508 /* .. .. ==> 0XF8006118[1:1] = 0x00000000U */
9509 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9510 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
9511 /* .. .. ==> 0XF8006118[2:2] = 0x00000000U */
9512 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
9513 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
9514 /* .. .. ==> 0XF8006118[3:3] = 0x00000000U */
9515 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
9516 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
9517 /* .. .. ==> 0XF8006118[4:4] = 0x00000000U */
9518 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
9519 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
9520 /* .. .. ==> 0XF8006118[5:5] = 0x00000000U */
9521 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
9522 /* .. .. reg_phy_bist_shift_dq = 0x0 */
9523 /* .. .. ==> 0XF8006118[14:6] = 0x00000000U */
9524 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
9525 /* .. .. reg_phy_bist_err_clr = 0x0 */
9526 /* .. .. ==> 0XF8006118[23:15] = 0x00000000U */
9527 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
9528 /* .. .. reg_phy_dq_offset = 0x40 */
9529 /* .. .. ==> 0XF8006118[30:24] = 0x00000040U */
9530 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
9531 /* .. .. */
9532 EMIT_MASKWRITE(0XF8006118, 0x7FFFFFFFU, 0x40000001U),
9533 /* .. .. reg_phy_data_slice_in_use = 0x1 */
9534 /* .. .. ==> 0XF800611C[0:0] = 0x00000001U */
9535 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
9536 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
9537 /* .. .. ==> 0XF800611C[1:1] = 0x00000000U */
9538 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9539 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
9540 /* .. .. ==> 0XF800611C[2:2] = 0x00000000U */
9541 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
9542 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
9543 /* .. .. ==> 0XF800611C[3:3] = 0x00000000U */
9544 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
9545 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
9546 /* .. .. ==> 0XF800611C[4:4] = 0x00000000U */
9547 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
9548 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
9549 /* .. .. ==> 0XF800611C[5:5] = 0x00000000U */
9550 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
9551 /* .. .. reg_phy_bist_shift_dq = 0x0 */
9552 /* .. .. ==> 0XF800611C[14:6] = 0x00000000U */
9553 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
9554 /* .. .. reg_phy_bist_err_clr = 0x0 */
9555 /* .. .. ==> 0XF800611C[23:15] = 0x00000000U */
9556 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
9557 /* .. .. reg_phy_dq_offset = 0x40 */
9558 /* .. .. ==> 0XF800611C[30:24] = 0x00000040U */
9559 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
9560 /* .. .. */
9561 EMIT_MASKWRITE(0XF800611C, 0x7FFFFFFFU, 0x40000001U),
9562 /* .. .. reg_phy_data_slice_in_use = 0x1 */
9563 /* .. .. ==> 0XF8006120[0:0] = 0x00000001U */
9564 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
9565 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
9566 /* .. .. ==> 0XF8006120[1:1] = 0x00000000U */
9567 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9568 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
9569 /* .. .. ==> 0XF8006120[2:2] = 0x00000000U */
9570 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
9571 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
9572 /* .. .. ==> 0XF8006120[3:3] = 0x00000000U */
9573 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
9574 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
9575 /* .. .. ==> 0XF8006120[4:4] = 0x00000000U */
9576 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
9577 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
9578 /* .. .. ==> 0XF8006120[5:5] = 0x00000000U */
9579 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
9580 /* .. .. reg_phy_bist_shift_dq = 0x0 */
9581 /* .. .. ==> 0XF8006120[14:6] = 0x00000000U */
9582 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
9583 /* .. .. reg_phy_bist_err_clr = 0x0 */
9584 /* .. .. ==> 0XF8006120[23:15] = 0x00000000U */
9585 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
9586 /* .. .. reg_phy_dq_offset = 0x40 */
9587 /* .. .. ==> 0XF8006120[30:24] = 0x00000040U */
9588 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
9589 /* .. .. */
9590 EMIT_MASKWRITE(0XF8006120, 0x7FFFFFFFU, 0x40000001U),
9591 /* .. .. reg_phy_data_slice_in_use = 0x1 */
9592 /* .. .. ==> 0XF8006124[0:0] = 0x00000001U */
9593 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
9594 /* .. .. reg_phy_rdlvl_inc_mode = 0x0 */
9595 /* .. .. ==> 0XF8006124[1:1] = 0x00000000U */
9596 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9597 /* .. .. reg_phy_gatelvl_inc_mode = 0x0 */
9598 /* .. .. ==> 0XF8006124[2:2] = 0x00000000U */
9599 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
9600 /* .. .. reg_phy_wrlvl_inc_mode = 0x0 */
9601 /* .. .. ==> 0XF8006124[3:3] = 0x00000000U */
9602 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
9603 /* .. .. reg_phy_board_lpbk_tx = 0x0 */
9604 /* .. .. ==> 0XF8006124[4:4] = 0x00000000U */
9605 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
9606 /* .. .. reg_phy_board_lpbk_rx = 0x0 */
9607 /* .. .. ==> 0XF8006124[5:5] = 0x00000000U */
9608 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000000U */
9609 /* .. .. reg_phy_bist_shift_dq = 0x0 */
9610 /* .. .. ==> 0XF8006124[14:6] = 0x00000000U */
9611 /* .. .. ==> MASK : 0x00007FC0U VAL : 0x00000000U */
9612 /* .. .. reg_phy_bist_err_clr = 0x0 */
9613 /* .. .. ==> 0XF8006124[23:15] = 0x00000000U */
9614 /* .. .. ==> MASK : 0x00FF8000U VAL : 0x00000000U */
9615 /* .. .. reg_phy_dq_offset = 0x40 */
9616 /* .. .. ==> 0XF8006124[30:24] = 0x00000040U */
9617 /* .. .. ==> MASK : 0x7F000000U VAL : 0x40000000U */
9618 /* .. .. */
9619 EMIT_MASKWRITE(0XF8006124, 0x7FFFFFFFU, 0x40000001U),
9620 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
9621 /* .. .. ==> 0XF800612C[9:0] = 0x00000000U */
9622 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
9623 /* .. .. reg_phy_gatelvl_init_ratio = 0x8f */
9624 /* .. .. ==> 0XF800612C[19:10] = 0x0000008FU */
9625 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00023C00U */
9626 /* .. .. */
9627 EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00023C00U),
9628 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
9629 /* .. .. ==> 0XF8006130[9:0] = 0x00000000U */
9630 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
9631 /* .. .. reg_phy_gatelvl_init_ratio = 0x8a */
9632 /* .. .. ==> 0XF8006130[19:10] = 0x0000008AU */
9633 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022800U */
9634 /* .. .. */
9635 EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00022800U),
9636 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
9637 /* .. .. ==> 0XF8006134[9:0] = 0x00000000U */
9638 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
9639 /* .. .. reg_phy_gatelvl_init_ratio = 0x8b */
9640 /* .. .. ==> 0XF8006134[19:10] = 0x0000008BU */
9641 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00022C00U */
9642 /* .. .. */
9643 EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00022C00U),
9644 /* .. .. reg_phy_wrlvl_init_ratio = 0x0 */
9645 /* .. .. ==> 0XF8006138[9:0] = 0x00000000U */
9646 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000000U */
9647 /* .. .. reg_phy_gatelvl_init_ratio = 0x92 */
9648 /* .. .. ==> 0XF8006138[19:10] = 0x00000092U */
9649 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00024800U */
9650 /* .. .. */
9651 EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00024800U),
9652 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
9653 /* .. .. ==> 0XF8006140[9:0] = 0x00000035U */
9654 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
9655 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
9656 /* .. .. ==> 0XF8006140[10:10] = 0x00000000U */
9657 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9658 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
9659 /* .. .. ==> 0XF8006140[19:11] = 0x00000000U */
9660 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9661 /* .. .. */
9662 EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
9663 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
9664 /* .. .. ==> 0XF8006144[9:0] = 0x00000035U */
9665 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
9666 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
9667 /* .. .. ==> 0XF8006144[10:10] = 0x00000000U */
9668 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9669 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
9670 /* .. .. ==> 0XF8006144[19:11] = 0x00000000U */
9671 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9672 /* .. .. */
9673 EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
9674 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
9675 /* .. .. ==> 0XF8006148[9:0] = 0x00000035U */
9676 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
9677 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
9678 /* .. .. ==> 0XF8006148[10:10] = 0x00000000U */
9679 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9680 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
9681 /* .. .. ==> 0XF8006148[19:11] = 0x00000000U */
9682 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9683 /* .. .. */
9684 EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
9685 /* .. .. reg_phy_rd_dqs_slave_ratio = 0x35 */
9686 /* .. .. ==> 0XF800614C[9:0] = 0x00000035U */
9687 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000035U */
9688 /* .. .. reg_phy_rd_dqs_slave_force = 0x0 */
9689 /* .. .. ==> 0XF800614C[10:10] = 0x00000000U */
9690 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9691 /* .. .. reg_phy_rd_dqs_slave_delay = 0x0 */
9692 /* .. .. ==> 0XF800614C[19:11] = 0x00000000U */
9693 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9694 /* .. .. */
9695 EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
9696 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x77 */
9697 /* .. .. ==> 0XF8006154[9:0] = 0x00000077U */
9698 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000077U */
9699 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
9700 /* .. .. ==> 0XF8006154[10:10] = 0x00000000U */
9701 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9702 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
9703 /* .. .. ==> 0XF8006154[19:11] = 0x00000000U */
9704 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9705 /* .. .. */
9706 EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000077U),
9707 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
9708 /* .. .. ==> 0XF8006158[9:0] = 0x0000007CU */
9709 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
9710 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
9711 /* .. .. ==> 0XF8006158[10:10] = 0x00000000U */
9712 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9713 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
9714 /* .. .. ==> 0XF8006158[19:11] = 0x00000000U */
9715 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9716 /* .. .. */
9717 EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x0000007CU),
9718 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x7c */
9719 /* .. .. ==> 0XF800615C[9:0] = 0x0000007CU */
9720 /* .. .. ==> MASK : 0x000003FFU VAL : 0x0000007CU */
9721 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
9722 /* .. .. ==> 0XF800615C[10:10] = 0x00000000U */
9723 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9724 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
9725 /* .. .. ==> 0XF800615C[19:11] = 0x00000000U */
9726 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9727 /* .. .. */
9728 EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x0000007CU),
9729 /* .. .. reg_phy_wr_dqs_slave_ratio = 0x75 */
9730 /* .. .. ==> 0XF8006160[9:0] = 0x00000075U */
9731 /* .. .. ==> MASK : 0x000003FFU VAL : 0x00000075U */
9732 /* .. .. reg_phy_wr_dqs_slave_force = 0x0 */
9733 /* .. .. ==> 0XF8006160[10:10] = 0x00000000U */
9734 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9735 /* .. .. reg_phy_wr_dqs_slave_delay = 0x0 */
9736 /* .. .. ==> 0XF8006160[19:11] = 0x00000000U */
9737 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9738 /* .. .. */
9739 EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000075U),
9740 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe4 */
9741 /* .. .. ==> 0XF8006168[10:0] = 0x000000E4U */
9742 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E4U */
9743 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
9744 /* .. .. ==> 0XF8006168[11:11] = 0x00000000U */
9745 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
9746 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
9747 /* .. .. ==> 0XF8006168[20:12] = 0x00000000U */
9748 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
9749 /* .. .. */
9750 EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000E4U),
9751 /* .. .. reg_phy_fifo_we_slave_ratio = 0xdf */
9752 /* .. .. ==> 0XF800616C[10:0] = 0x000000DFU */
9753 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000DFU */
9754 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
9755 /* .. .. ==> 0XF800616C[11:11] = 0x00000000U */
9756 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
9757 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
9758 /* .. .. ==> 0XF800616C[20:12] = 0x00000000U */
9759 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
9760 /* .. .. */
9761 EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000DFU),
9762 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe0 */
9763 /* .. .. ==> 0XF8006170[10:0] = 0x000000E0U */
9764 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E0U */
9765 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
9766 /* .. .. ==> 0XF8006170[11:11] = 0x00000000U */
9767 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
9768 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
9769 /* .. .. ==> 0XF8006170[20:12] = 0x00000000U */
9770 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
9771 /* .. .. */
9772 EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000E0U),
9773 /* .. .. reg_phy_fifo_we_slave_ratio = 0xe7 */
9774 /* .. .. ==> 0XF8006174[10:0] = 0x000000E7U */
9775 /* .. .. ==> MASK : 0x000007FFU VAL : 0x000000E7U */
9776 /* .. .. reg_phy_fifo_we_in_force = 0x0 */
9777 /* .. .. ==> 0XF8006174[11:11] = 0x00000000U */
9778 /* .. .. ==> MASK : 0x00000800U VAL : 0x00000000U */
9779 /* .. .. reg_phy_fifo_we_in_delay = 0x0 */
9780 /* .. .. ==> 0XF8006174[20:12] = 0x00000000U */
9781 /* .. .. ==> MASK : 0x001FF000U VAL : 0x00000000U */
9782 /* .. .. */
9783 EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000E7U),
9784 /* .. .. reg_phy_wr_data_slave_ratio = 0xb7 */
9785 /* .. .. ==> 0XF800617C[9:0] = 0x000000B7U */
9786 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B7U */
9787 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
9788 /* .. .. ==> 0XF800617C[10:10] = 0x00000000U */
9789 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9790 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
9791 /* .. .. ==> 0XF800617C[19:11] = 0x00000000U */
9792 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9793 /* .. .. */
9794 EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000B7U),
9795 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
9796 /* .. .. ==> 0XF8006180[9:0] = 0x000000BCU */
9797 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
9798 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
9799 /* .. .. ==> 0XF8006180[10:10] = 0x00000000U */
9800 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9801 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
9802 /* .. .. ==> 0XF8006180[19:11] = 0x00000000U */
9803 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9804 /* .. .. */
9805 EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000BCU),
9806 /* .. .. reg_phy_wr_data_slave_ratio = 0xbc */
9807 /* .. .. ==> 0XF8006184[9:0] = 0x000000BCU */
9808 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000BCU */
9809 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
9810 /* .. .. ==> 0XF8006184[10:10] = 0x00000000U */
9811 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9812 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
9813 /* .. .. ==> 0XF8006184[19:11] = 0x00000000U */
9814 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9815 /* .. .. */
9816 EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000BCU),
9817 /* .. .. reg_phy_wr_data_slave_ratio = 0xb5 */
9818 /* .. .. ==> 0XF8006188[9:0] = 0x000000B5U */
9819 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000000B5U */
9820 /* .. .. reg_phy_wr_data_slave_force = 0x0 */
9821 /* .. .. ==> 0XF8006188[10:10] = 0x00000000U */
9822 /* .. .. ==> MASK : 0x00000400U VAL : 0x00000000U */
9823 /* .. .. reg_phy_wr_data_slave_delay = 0x0 */
9824 /* .. .. ==> 0XF8006188[19:11] = 0x00000000U */
9825 /* .. .. ==> MASK : 0x000FF800U VAL : 0x00000000U */
9826 /* .. .. */
9827 EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000B5U),
9828 /* .. .. reg_phy_loopback = 0x0 */
9829 /* .. .. ==> 0XF8006190[0:0] = 0x00000000U */
9830 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
9831 /* .. .. reg_phy_bl2 = 0x0 */
9832 /* .. .. ==> 0XF8006190[1:1] = 0x00000000U */
9833 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
9834 /* .. .. reg_phy_at_spd_atpg = 0x0 */
9835 /* .. .. ==> 0XF8006190[2:2] = 0x00000000U */
9836 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
9837 /* .. .. reg_phy_bist_enable = 0x0 */
9838 /* .. .. ==> 0XF8006190[3:3] = 0x00000000U */
9839 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
9840 /* .. .. reg_phy_bist_force_err = 0x0 */
9841 /* .. .. ==> 0XF8006190[4:4] = 0x00000000U */
9842 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
9843 /* .. .. reg_phy_bist_mode = 0x0 */
9844 /* .. .. ==> 0XF8006190[6:5] = 0x00000000U */
9845 /* .. .. ==> MASK : 0x00000060U VAL : 0x00000000U */
9846 /* .. .. reg_phy_invert_clkout = 0x1 */
9847 /* .. .. ==> 0XF8006190[7:7] = 0x00000001U */
9848 /* .. .. ==> MASK : 0x00000080U VAL : 0x00000080U */
9849 /* .. .. reg_phy_all_dq_mpr_rd_resp = 0x0 */
9850 /* .. .. ==> 0XF8006190[8:8] = 0x00000000U */
9851 /* .. .. ==> MASK : 0x00000100U VAL : 0x00000000U */
9852 /* .. .. reg_phy_sel_logic = 0x0 */
9853 /* .. .. ==> 0XF8006190[9:9] = 0x00000000U */
9854 /* .. .. ==> MASK : 0x00000200U VAL : 0x00000000U */
9855 /* .. .. reg_phy_ctrl_slave_ratio = 0x100 */
9856 /* .. .. ==> 0XF8006190[19:10] = 0x00000100U */
9857 /* .. .. ==> MASK : 0x000FFC00U VAL : 0x00040000U */
9858 /* .. .. reg_phy_ctrl_slave_force = 0x0 */
9859 /* .. .. ==> 0XF8006190[20:20] = 0x00000000U */
9860 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
9861 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
9862 /* .. .. ==> 0XF8006190[27:21] = 0x00000000U */
9863 /* .. .. ==> MASK : 0x0FE00000U VAL : 0x00000000U */
9864 /* .. .. reg_phy_use_rank0_delays = 0x1 */
9865 /* .. .. ==> 0XF8006190[28:28] = 0x00000001U */
9866 /* .. .. ==> MASK : 0x10000000U VAL : 0x10000000U */
9867 /* .. .. reg_phy_lpddr = 0x0 */
9868 /* .. .. ==> 0XF8006190[29:29] = 0x00000000U */
9869 /* .. .. ==> MASK : 0x20000000U VAL : 0x00000000U */
9870 /* .. .. reg_phy_cmd_latency = 0x0 */
9871 /* .. .. ==> 0XF8006190[30:30] = 0x00000000U */
9872 /* .. .. ==> MASK : 0x40000000U VAL : 0x00000000U */
9873 /* .. .. reg_phy_int_lpbk = 0x0 */
9874 /* .. .. ==> 0XF8006190[31:31] = 0x00000000U */
9875 /* .. .. ==> MASK : 0x80000000U VAL : 0x00000000U */
9876 /* .. .. */
9877 EMIT_MASKWRITE(0XF8006190, 0xFFFFFFFFU, 0x10040080U),
9878 /* .. .. reg_phy_wr_rl_delay = 0x2 */
9879 /* .. .. ==> 0XF8006194[4:0] = 0x00000002U */
9880 /* .. .. ==> MASK : 0x0000001FU VAL : 0x00000002U */
9881 /* .. .. reg_phy_rd_rl_delay = 0x4 */
9882 /* .. .. ==> 0XF8006194[9:5] = 0x00000004U */
9883 /* .. .. ==> MASK : 0x000003E0U VAL : 0x00000080U */
9884 /* .. .. reg_phy_dll_lock_diff = 0xf */
9885 /* .. .. ==> 0XF8006194[13:10] = 0x0000000FU */
9886 /* .. .. ==> MASK : 0x00003C00U VAL : 0x00003C00U */
9887 /* .. .. reg_phy_use_wr_level = 0x1 */
9888 /* .. .. ==> 0XF8006194[14:14] = 0x00000001U */
9889 /* .. .. ==> MASK : 0x00004000U VAL : 0x00004000U */
9890 /* .. .. reg_phy_use_rd_dqs_gate_level = 0x1 */
9891 /* .. .. ==> 0XF8006194[15:15] = 0x00000001U */
9892 /* .. .. ==> MASK : 0x00008000U VAL : 0x00008000U */
9893 /* .. .. reg_phy_use_rd_data_eye_level = 0x1 */
9894 /* .. .. ==> 0XF8006194[16:16] = 0x00000001U */
9895 /* .. .. ==> MASK : 0x00010000U VAL : 0x00010000U */
9896 /* .. .. reg_phy_dis_calib_rst = 0x0 */
9897 /* .. .. ==> 0XF8006194[17:17] = 0x00000000U */
9898 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9899 /* .. .. reg_phy_ctrl_slave_delay = 0x0 */
9900 /* .. .. ==> 0XF8006194[19:18] = 0x00000000U */
9901 /* .. .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
9902 /* .. .. */
9903 EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
9904 /* .. .. reg_arb_page_addr_mask = 0x0 */
9905 /* .. .. ==> 0XF8006204[31:0] = 0x00000000U */
9906 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
9907 /* .. .. */
9908 EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
9909 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
9910 /* .. .. ==> 0XF8006208[9:0] = 0x000003FFU */
9911 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9912 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
9913 /* .. .. ==> 0XF8006208[16:16] = 0x00000000U */
9914 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9915 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
9916 /* .. .. ==> 0XF8006208[17:17] = 0x00000000U */
9917 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9918 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
9919 /* .. .. ==> 0XF8006208[18:18] = 0x00000000U */
9920 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9921 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
9922 /* .. .. ==> 0XF8006208[19:19] = 0x00000001U */
9923 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
9924 /* .. .. */
9925 EMIT_MASKWRITE(0XF8006208, 0x000F03FFU, 0x000803FFU),
9926 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
9927 /* .. .. ==> 0XF800620C[9:0] = 0x000003FFU */
9928 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9929 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
9930 /* .. .. ==> 0XF800620C[16:16] = 0x00000000U */
9931 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9932 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
9933 /* .. .. ==> 0XF800620C[17:17] = 0x00000000U */
9934 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9935 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
9936 /* .. .. ==> 0XF800620C[18:18] = 0x00000000U */
9937 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9938 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
9939 /* .. .. ==> 0XF800620C[19:19] = 0x00000001U */
9940 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
9941 /* .. .. */
9942 EMIT_MASKWRITE(0XF800620C, 0x000F03FFU, 0x000803FFU),
9943 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
9944 /* .. .. ==> 0XF8006210[9:0] = 0x000003FFU */
9945 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9946 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
9947 /* .. .. ==> 0XF8006210[16:16] = 0x00000000U */
9948 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9949 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
9950 /* .. .. ==> 0XF8006210[17:17] = 0x00000000U */
9951 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9952 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
9953 /* .. .. ==> 0XF8006210[18:18] = 0x00000000U */
9954 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9955 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
9956 /* .. .. ==> 0XF8006210[19:19] = 0x00000001U */
9957 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
9958 /* .. .. */
9959 EMIT_MASKWRITE(0XF8006210, 0x000F03FFU, 0x000803FFU),
9960 /* .. .. reg_arb_pri_wr_portn = 0x3ff */
9961 /* .. .. ==> 0XF8006214[9:0] = 0x000003FFU */
9962 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9963 /* .. .. reg_arb_disable_aging_wr_portn = 0x0 */
9964 /* .. .. ==> 0XF8006214[16:16] = 0x00000000U */
9965 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9966 /* .. .. reg_arb_disable_urgent_wr_portn = 0x0 */
9967 /* .. .. ==> 0XF8006214[17:17] = 0x00000000U */
9968 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9969 /* .. .. reg_arb_dis_page_match_wr_portn = 0x0 */
9970 /* .. .. ==> 0XF8006214[18:18] = 0x00000000U */
9971 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9972 /* .. .. reg_arb_dis_rmw_portn = 0x1 */
9973 /* .. .. ==> 0XF8006214[19:19] = 0x00000001U */
9974 /* .. .. ==> MASK : 0x00080000U VAL : 0x00080000U */
9975 /* .. .. */
9976 EMIT_MASKWRITE(0XF8006214, 0x000F03FFU, 0x000803FFU),
9977 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
9978 /* .. .. ==> 0XF8006218[9:0] = 0x000003FFU */
9979 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9980 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
9981 /* .. .. ==> 0XF8006218[16:16] = 0x00000000U */
9982 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
9983 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
9984 /* .. .. ==> 0XF8006218[17:17] = 0x00000000U */
9985 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
9986 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
9987 /* .. .. ==> 0XF8006218[18:18] = 0x00000000U */
9988 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
9989 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
9990 /* .. .. ==> 0XF8006218[19:19] = 0x00000000U */
9991 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
9992 /* .. .. */
9993 EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
9994 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
9995 /* .. .. ==> 0XF800621C[9:0] = 0x000003FFU */
9996 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
9997 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
9998 /* .. .. ==> 0XF800621C[16:16] = 0x00000000U */
9999 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
10000 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
10001 /* .. .. ==> 0XF800621C[17:17] = 0x00000000U */
10002 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
10003 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
10004 /* .. .. ==> 0XF800621C[18:18] = 0x00000000U */
10005 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
10006 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
10007 /* .. .. ==> 0XF800621C[19:19] = 0x00000000U */
10008 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
10009 /* .. .. */
10010 EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
10011 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
10012 /* .. .. ==> 0XF8006220[9:0] = 0x000003FFU */
10013 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
10014 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
10015 /* .. .. ==> 0XF8006220[16:16] = 0x00000000U */
10016 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
10017 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
10018 /* .. .. ==> 0XF8006220[17:17] = 0x00000000U */
10019 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
10020 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
10021 /* .. .. ==> 0XF8006220[18:18] = 0x00000000U */
10022 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
10023 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
10024 /* .. .. ==> 0XF8006220[19:19] = 0x00000000U */
10025 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
10026 /* .. .. */
10027 EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
10028 /* .. .. reg_arb_pri_rd_portn = 0x3ff */
10029 /* .. .. ==> 0XF8006224[9:0] = 0x000003FFU */
10030 /* .. .. ==> MASK : 0x000003FFU VAL : 0x000003FFU */
10031 /* .. .. reg_arb_disable_aging_rd_portn = 0x0 */
10032 /* .. .. ==> 0XF8006224[16:16] = 0x00000000U */
10033 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
10034 /* .. .. reg_arb_disable_urgent_rd_portn = 0x0 */
10035 /* .. .. ==> 0XF8006224[17:17] = 0x00000000U */
10036 /* .. .. ==> MASK : 0x00020000U VAL : 0x00000000U */
10037 /* .. .. reg_arb_dis_page_match_rd_portn = 0x0 */
10038 /* .. .. ==> 0XF8006224[18:18] = 0x00000000U */
10039 /* .. .. ==> MASK : 0x00040000U VAL : 0x00000000U */
10040 /* .. .. reg_arb_set_hpr_rd_portn = 0x0 */
10041 /* .. .. ==> 0XF8006224[19:19] = 0x00000000U */
10042 /* .. .. ==> MASK : 0x00080000U VAL : 0x00000000U */
10043 /* .. .. */
10044 EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
10045 /* .. .. reg_ddrc_lpddr2 = 0x0 */
10046 /* .. .. ==> 0XF80062A8[0:0] = 0x00000000U */
10047 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10048 /* .. .. reg_ddrc_per_bank_refresh = 0x0 */
10049 /* .. .. ==> 0XF80062A8[1:1] = 0x00000000U */
10050 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10051 /* .. .. reg_ddrc_derate_enable = 0x0 */
10052 /* .. .. ==> 0XF80062A8[2:2] = 0x00000000U */
10053 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10054 /* .. .. reg_ddrc_mr4_margin = 0x0 */
10055 /* .. .. ==> 0XF80062A8[11:4] = 0x00000000U */
10056 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000000U */
10057 /* .. .. */
10058 EMIT_MASKWRITE(0XF80062A8, 0x00000FF7U, 0x00000000U),
10059 /* .. .. reg_ddrc_mr4_read_interval = 0x0 */
10060 /* .. .. ==> 0XF80062AC[31:0] = 0x00000000U */
10061 /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0x00000000U */
10062 /* .. .. */
10063 EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
10064 /* .. .. reg_ddrc_min_stable_clock_x1 = 0x5 */
10065 /* .. .. ==> 0XF80062B0[3:0] = 0x00000005U */
10066 /* .. .. ==> MASK : 0x0000000FU VAL : 0x00000005U */
10067 /* .. .. reg_ddrc_idle_after_reset_x32 = 0x12 */
10068 /* .. .. ==> 0XF80062B0[11:4] = 0x00000012U */
10069 /* .. .. ==> MASK : 0x00000FF0U VAL : 0x00000120U */
10070 /* .. .. reg_ddrc_t_mrw = 0x5 */
10071 /* .. .. ==> 0XF80062B0[21:12] = 0x00000005U */
10072 /* .. .. ==> MASK : 0x003FF000U VAL : 0x00005000U */
10073 /* .. .. */
10074 EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
10075 /* .. .. reg_ddrc_max_auto_init_x1024 = 0xa6 */
10076 /* .. .. ==> 0XF80062B4[7:0] = 0x000000A6U */
10077 /* .. .. ==> MASK : 0x000000FFU VAL : 0x000000A6U */
10078 /* .. .. reg_ddrc_dev_zqinit_x32 = 0x12 */
10079 /* .. .. ==> 0XF80062B4[17:8] = 0x00000012U */
10080 /* .. .. ==> MASK : 0x0003FF00U VAL : 0x00001200U */
10081 /* .. .. */
10082 EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A6U),
10083 /* .. .. START: POLL ON DCI STATUS */
10084 /* .. .. DONE = 1 */
10085 /* .. .. ==> 0XF8000B74[13:13] = 0x00000001U */
10086 /* .. .. ==> MASK : 0x00002000U VAL : 0x00002000U */
10087 /* .. .. */
10088 EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
10089 /* .. .. FINISH: POLL ON DCI STATUS */
10090 /* .. .. START: UNLOCK DDR */
10091 /* .. .. reg_ddrc_soft_rstb = 0x1 */
10092 /* .. .. ==> 0XF8006000[0:0] = 0x00000001U */
10093 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
10094 /* .. .. reg_ddrc_powerdown_en = 0x0 */
10095 /* .. .. ==> 0XF8006000[1:1] = 0x00000000U */
10096 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10097 /* .. .. reg_ddrc_data_bus_width = 0x0 */
10098 /* .. .. ==> 0XF8006000[3:2] = 0x00000000U */
10099 /* .. .. ==> MASK : 0x0000000CU VAL : 0x00000000U */
10100 /* .. .. reg_ddrc_burst8_refresh = 0x0 */
10101 /* .. .. ==> 0XF8006000[6:4] = 0x00000000U */
10102 /* .. .. ==> MASK : 0x00000070U VAL : 0x00000000U */
10103 /* .. .. reg_ddrc_rdwr_idle_gap = 1 */
10104 /* .. .. ==> 0XF8006000[13:7] = 0x00000001U */
10105 /* .. .. ==> MASK : 0x00003F80U VAL : 0x00000080U */
10106 /* .. .. reg_ddrc_dis_rd_bypass = 0x0 */
10107 /* .. .. ==> 0XF8006000[14:14] = 0x00000000U */
10108 /* .. .. ==> MASK : 0x00004000U VAL : 0x00000000U */
10109 /* .. .. reg_ddrc_dis_act_bypass = 0x0 */
10110 /* .. .. ==> 0XF8006000[15:15] = 0x00000000U */
10111 /* .. .. ==> MASK : 0x00008000U VAL : 0x00000000U */
10112 /* .. .. reg_ddrc_dis_auto_refresh = 0x0 */
10113 /* .. .. ==> 0XF8006000[16:16] = 0x00000000U */
10114 /* .. .. ==> MASK : 0x00010000U VAL : 0x00000000U */
10115 /* .. .. */
10116 EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
10117 /* .. .. FINISH: UNLOCK DDR */
10118 /* .. .. START: CHECK DDR STATUS */
10119 /* .. .. ddrc_reg_operating_mode = 1 */
10120 /* .. .. ==> 0XF8006054[2:0] = 0x00000001U */
10121 /* .. .. ==> MASK : 0x00000007U VAL : 0x00000001U */
10122 /* .. .. */
10123 EMIT_MASKPOLL(0XF8006054, 0x00000007U),
10124 /* .. .. FINISH: CHECK DDR STATUS */
10125 /* .. FINISH: DDR INITIALIZATION */
10126 /* FINISH: top */
10127 /* */
10128 EMIT_EXIT(),
10129
10130 /* */
10131 };
10132
10133 unsigned long ps7_mio_init_data_1_0[] = {
10134 /* START: top */
10135 /* .. START: SLCR SETTINGS */
10136 /* .. UNLOCK_KEY = 0XDF0D */
10137 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
10138 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
10139 /* .. */
10140 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
10141 /* .. FINISH: SLCR SETTINGS */
10142 /* .. START: OCM REMAPPING */
10143 /* .. VREF_EN = 0x1 */
10144 /* .. ==> 0XF8000B00[0:0] = 0x00000001U */
10145 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
10146 /* .. VREF_PULLUP_EN = 0x0 */
10147 /* .. ==> 0XF8000B00[1:1] = 0x00000000U */
10148 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10149 /* .. CLK_PULLUP_EN = 0x0 */
10150 /* .. ==> 0XF8000B00[8:8] = 0x00000000U */
10151 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10152 /* .. SRSTN_PULLUP_EN = 0x0 */
10153 /* .. ==> 0XF8000B00[9:9] = 0x00000000U */
10154 /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
10155 /* .. */
10156 EMIT_MASKWRITE(0XF8000B00, 0x00000303U, 0x00000001U),
10157 /* .. FINISH: OCM REMAPPING */
10158 /* .. START: DDRIOB SETTINGS */
10159 /* .. INP_POWER = 0x0 */
10160 /* .. ==> 0XF8000B40[0:0] = 0x00000000U */
10161 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10162 /* .. INP_TYPE = 0x0 */
10163 /* .. ==> 0XF8000B40[2:1] = 0x00000000U */
10164 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
10165 /* .. DCI_UPDATE = 0x0 */
10166 /* .. ==> 0XF8000B40[3:3] = 0x00000000U */
10167 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10168 /* .. TERM_EN = 0x0 */
10169 /* .. ==> 0XF8000B40[4:4] = 0x00000000U */
10170 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
10171 /* .. DCR_TYPE = 0x0 */
10172 /* .. ==> 0XF8000B40[6:5] = 0x00000000U */
10173 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
10174 /* .. IBUF_DISABLE_MODE = 0x0 */
10175 /* .. ==> 0XF8000B40[7:7] = 0x00000000U */
10176 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10177 /* .. TERM_DISABLE_MODE = 0x0 */
10178 /* .. ==> 0XF8000B40[8:8] = 0x00000000U */
10179 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10180 /* .. OUTPUT_EN = 0x3 */
10181 /* .. ==> 0XF8000B40[10:9] = 0x00000003U */
10182 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10183 /* .. PULLUP_EN = 0x0 */
10184 /* .. ==> 0XF8000B40[11:11] = 0x00000000U */
10185 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10186 /* .. */
10187 EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
10188 /* .. INP_POWER = 0x0 */
10189 /* .. ==> 0XF8000B44[0:0] = 0x00000000U */
10190 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10191 /* .. INP_TYPE = 0x0 */
10192 /* .. ==> 0XF8000B44[2:1] = 0x00000000U */
10193 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
10194 /* .. DCI_UPDATE = 0x0 */
10195 /* .. ==> 0XF8000B44[3:3] = 0x00000000U */
10196 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10197 /* .. TERM_EN = 0x0 */
10198 /* .. ==> 0XF8000B44[4:4] = 0x00000000U */
10199 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
10200 /* .. DCR_TYPE = 0x0 */
10201 /* .. ==> 0XF8000B44[6:5] = 0x00000000U */
10202 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
10203 /* .. IBUF_DISABLE_MODE = 0x0 */
10204 /* .. ==> 0XF8000B44[7:7] = 0x00000000U */
10205 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10206 /* .. TERM_DISABLE_MODE = 0x0 */
10207 /* .. ==> 0XF8000B44[8:8] = 0x00000000U */
10208 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10209 /* .. OUTPUT_EN = 0x3 */
10210 /* .. ==> 0XF8000B44[10:9] = 0x00000003U */
10211 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10212 /* .. PULLUP_EN = 0x0 */
10213 /* .. ==> 0XF8000B44[11:11] = 0x00000000U */
10214 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10215 /* .. */
10216 EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
10217 /* .. INP_POWER = 0x0 */
10218 /* .. ==> 0XF8000B48[0:0] = 0x00000000U */
10219 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10220 /* .. INP_TYPE = 0x1 */
10221 /* .. ==> 0XF8000B48[2:1] = 0x00000001U */
10222 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
10223 /* .. DCI_UPDATE = 0x0 */
10224 /* .. ==> 0XF8000B48[3:3] = 0x00000000U */
10225 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10226 /* .. TERM_EN = 0x1 */
10227 /* .. ==> 0XF8000B48[4:4] = 0x00000001U */
10228 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
10229 /* .. DCR_TYPE = 0x3 */
10230 /* .. ==> 0XF8000B48[6:5] = 0x00000003U */
10231 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
10232 /* .. IBUF_DISABLE_MODE = 0 */
10233 /* .. ==> 0XF8000B48[7:7] = 0x00000000U */
10234 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10235 /* .. TERM_DISABLE_MODE = 0 */
10236 /* .. ==> 0XF8000B48[8:8] = 0x00000000U */
10237 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10238 /* .. OUTPUT_EN = 0x3 */
10239 /* .. ==> 0XF8000B48[10:9] = 0x00000003U */
10240 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10241 /* .. PULLUP_EN = 0x0 */
10242 /* .. ==> 0XF8000B48[11:11] = 0x00000000U */
10243 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10244 /* .. */
10245 EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
10246 /* .. INP_POWER = 0x0 */
10247 /* .. ==> 0XF8000B4C[0:0] = 0x00000000U */
10248 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10249 /* .. INP_TYPE = 0x1 */
10250 /* .. ==> 0XF8000B4C[2:1] = 0x00000001U */
10251 /* .. ==> MASK : 0x00000006U VAL : 0x00000002U */
10252 /* .. DCI_UPDATE = 0x0 */
10253 /* .. ==> 0XF8000B4C[3:3] = 0x00000000U */
10254 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10255 /* .. TERM_EN = 0x1 */
10256 /* .. ==> 0XF8000B4C[4:4] = 0x00000001U */
10257 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
10258 /* .. DCR_TYPE = 0x3 */
10259 /* .. ==> 0XF8000B4C[6:5] = 0x00000003U */
10260 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
10261 /* .. IBUF_DISABLE_MODE = 0 */
10262 /* .. ==> 0XF8000B4C[7:7] = 0x00000000U */
10263 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10264 /* .. TERM_DISABLE_MODE = 0 */
10265 /* .. ==> 0XF8000B4C[8:8] = 0x00000000U */
10266 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10267 /* .. OUTPUT_EN = 0x3 */
10268 /* .. ==> 0XF8000B4C[10:9] = 0x00000003U */
10269 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10270 /* .. PULLUP_EN = 0x0 */
10271 /* .. ==> 0XF8000B4C[11:11] = 0x00000000U */
10272 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10273 /* .. */
10274 EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
10275 /* .. INP_POWER = 0x0 */
10276 /* .. ==> 0XF8000B50[0:0] = 0x00000000U */
10277 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10278 /* .. INP_TYPE = 0x2 */
10279 /* .. ==> 0XF8000B50[2:1] = 0x00000002U */
10280 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
10281 /* .. DCI_UPDATE = 0x0 */
10282 /* .. ==> 0XF8000B50[3:3] = 0x00000000U */
10283 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10284 /* .. TERM_EN = 0x1 */
10285 /* .. ==> 0XF8000B50[4:4] = 0x00000001U */
10286 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
10287 /* .. DCR_TYPE = 0x3 */
10288 /* .. ==> 0XF8000B50[6:5] = 0x00000003U */
10289 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
10290 /* .. IBUF_DISABLE_MODE = 0 */
10291 /* .. ==> 0XF8000B50[7:7] = 0x00000000U */
10292 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10293 /* .. TERM_DISABLE_MODE = 0 */
10294 /* .. ==> 0XF8000B50[8:8] = 0x00000000U */
10295 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10296 /* .. OUTPUT_EN = 0x3 */
10297 /* .. ==> 0XF8000B50[10:9] = 0x00000003U */
10298 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10299 /* .. PULLUP_EN = 0x0 */
10300 /* .. ==> 0XF8000B50[11:11] = 0x00000000U */
10301 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10302 /* .. */
10303 EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
10304 /* .. INP_POWER = 0x0 */
10305 /* .. ==> 0XF8000B54[0:0] = 0x00000000U */
10306 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10307 /* .. INP_TYPE = 0x2 */
10308 /* .. ==> 0XF8000B54[2:1] = 0x00000002U */
10309 /* .. ==> MASK : 0x00000006U VAL : 0x00000004U */
10310 /* .. DCI_UPDATE = 0x0 */
10311 /* .. ==> 0XF8000B54[3:3] = 0x00000000U */
10312 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10313 /* .. TERM_EN = 0x1 */
10314 /* .. ==> 0XF8000B54[4:4] = 0x00000001U */
10315 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
10316 /* .. DCR_TYPE = 0x3 */
10317 /* .. ==> 0XF8000B54[6:5] = 0x00000003U */
10318 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
10319 /* .. IBUF_DISABLE_MODE = 0 */
10320 /* .. ==> 0XF8000B54[7:7] = 0x00000000U */
10321 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10322 /* .. TERM_DISABLE_MODE = 0 */
10323 /* .. ==> 0XF8000B54[8:8] = 0x00000000U */
10324 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10325 /* .. OUTPUT_EN = 0x3 */
10326 /* .. ==> 0XF8000B54[10:9] = 0x00000003U */
10327 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10328 /* .. PULLUP_EN = 0x0 */
10329 /* .. ==> 0XF8000B54[11:11] = 0x00000000U */
10330 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10331 /* .. */
10332 EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
10333 /* .. INP_POWER = 0x0 */
10334 /* .. ==> 0XF8000B58[0:0] = 0x00000000U */
10335 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10336 /* .. INP_TYPE = 0x0 */
10337 /* .. ==> 0XF8000B58[2:1] = 0x00000000U */
10338 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
10339 /* .. DCI_UPDATE = 0x0 */
10340 /* .. ==> 0XF8000B58[3:3] = 0x00000000U */
10341 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10342 /* .. TERM_EN = 0x0 */
10343 /* .. ==> 0XF8000B58[4:4] = 0x00000000U */
10344 /* .. ==> MASK : 0x00000010U VAL : 0x00000000U */
10345 /* .. DCR_TYPE = 0x0 */
10346 /* .. ==> 0XF8000B58[6:5] = 0x00000000U */
10347 /* .. ==> MASK : 0x00000060U VAL : 0x00000000U */
10348 /* .. IBUF_DISABLE_MODE = 0x0 */
10349 /* .. ==> 0XF8000B58[7:7] = 0x00000000U */
10350 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
10351 /* .. TERM_DISABLE_MODE = 0x0 */
10352 /* .. ==> 0XF8000B58[8:8] = 0x00000000U */
10353 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10354 /* .. OUTPUT_EN = 0x3 */
10355 /* .. ==> 0XF8000B58[10:9] = 0x00000003U */
10356 /* .. ==> MASK : 0x00000600U VAL : 0x00000600U */
10357 /* .. PULLUP_EN = 0x0 */
10358 /* .. ==> 0XF8000B58[11:11] = 0x00000000U */
10359 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
10360 /* .. */
10361 EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
10362 /* .. DRIVE_P = 0x1c */
10363 /* .. ==> 0XF8000B5C[6:0] = 0x0000001CU */
10364 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
10365 /* .. DRIVE_N = 0xc */
10366 /* .. ==> 0XF8000B5C[13:7] = 0x0000000CU */
10367 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
10368 /* .. SLEW_P = 0x3 */
10369 /* .. ==> 0XF8000B5C[18:14] = 0x00000003U */
10370 /* .. ==> MASK : 0x0007C000U VAL : 0x0000C000U */
10371 /* .. SLEW_N = 0x3 */
10372 /* .. ==> 0XF8000B5C[23:19] = 0x00000003U */
10373 /* .. ==> MASK : 0x00F80000U VAL : 0x00180000U */
10374 /* .. GTL = 0x0 */
10375 /* .. ==> 0XF8000B5C[26:24] = 0x00000000U */
10376 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
10377 /* .. RTERM = 0x0 */
10378 /* .. ==> 0XF8000B5C[31:27] = 0x00000000U */
10379 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
10380 /* .. */
10381 EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
10382 /* .. DRIVE_P = 0x1c */
10383 /* .. ==> 0XF8000B60[6:0] = 0x0000001CU */
10384 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
10385 /* .. DRIVE_N = 0xc */
10386 /* .. ==> 0XF8000B60[13:7] = 0x0000000CU */
10387 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
10388 /* .. SLEW_P = 0x6 */
10389 /* .. ==> 0XF8000B60[18:14] = 0x00000006U */
10390 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
10391 /* .. SLEW_N = 0x1f */
10392 /* .. ==> 0XF8000B60[23:19] = 0x0000001FU */
10393 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
10394 /* .. GTL = 0x0 */
10395 /* .. ==> 0XF8000B60[26:24] = 0x00000000U */
10396 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
10397 /* .. RTERM = 0x0 */
10398 /* .. ==> 0XF8000B60[31:27] = 0x00000000U */
10399 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
10400 /* .. */
10401 EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
10402 /* .. DRIVE_P = 0x1c */
10403 /* .. ==> 0XF8000B64[6:0] = 0x0000001CU */
10404 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
10405 /* .. DRIVE_N = 0xc */
10406 /* .. ==> 0XF8000B64[13:7] = 0x0000000CU */
10407 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
10408 /* .. SLEW_P = 0x6 */
10409 /* .. ==> 0XF8000B64[18:14] = 0x00000006U */
10410 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
10411 /* .. SLEW_N = 0x1f */
10412 /* .. ==> 0XF8000B64[23:19] = 0x0000001FU */
10413 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
10414 /* .. GTL = 0x0 */
10415 /* .. ==> 0XF8000B64[26:24] = 0x00000000U */
10416 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
10417 /* .. RTERM = 0x0 */
10418 /* .. ==> 0XF8000B64[31:27] = 0x00000000U */
10419 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
10420 /* .. */
10421 EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
10422 /* .. DRIVE_P = 0x1c */
10423 /* .. ==> 0XF8000B68[6:0] = 0x0000001CU */
10424 /* .. ==> MASK : 0x0000007FU VAL : 0x0000001CU */
10425 /* .. DRIVE_N = 0xc */
10426 /* .. ==> 0XF8000B68[13:7] = 0x0000000CU */
10427 /* .. ==> MASK : 0x00003F80U VAL : 0x00000600U */
10428 /* .. SLEW_P = 0x6 */
10429 /* .. ==> 0XF8000B68[18:14] = 0x00000006U */
10430 /* .. ==> MASK : 0x0007C000U VAL : 0x00018000U */
10431 /* .. SLEW_N = 0x1f */
10432 /* .. ==> 0XF8000B68[23:19] = 0x0000001FU */
10433 /* .. ==> MASK : 0x00F80000U VAL : 0x00F80000U */
10434 /* .. GTL = 0x0 */
10435 /* .. ==> 0XF8000B68[26:24] = 0x00000000U */
10436 /* .. ==> MASK : 0x07000000U VAL : 0x00000000U */
10437 /* .. RTERM = 0x0 */
10438 /* .. ==> 0XF8000B68[31:27] = 0x00000000U */
10439 /* .. ==> MASK : 0xF8000000U VAL : 0x00000000U */
10440 /* .. */
10441 EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
10442 /* .. VREF_INT_EN = 0x0 */
10443 /* .. ==> 0XF8000B6C[0:0] = 0x00000000U */
10444 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10445 /* .. VREF_SEL = 0x0 */
10446 /* .. ==> 0XF8000B6C[4:1] = 0x00000000U */
10447 /* .. ==> MASK : 0x0000001EU VAL : 0x00000000U */
10448 /* .. VREF_EXT_EN = 0x3 */
10449 /* .. ==> 0XF8000B6C[6:5] = 0x00000003U */
10450 /* .. ==> MASK : 0x00000060U VAL : 0x00000060U */
10451 /* .. VREF_PULLUP_EN = 0x0 */
10452 /* .. ==> 0XF8000B6C[8:7] = 0x00000000U */
10453 /* .. ==> MASK : 0x00000180U VAL : 0x00000000U */
10454 /* .. REFIO_EN = 0x1 */
10455 /* .. ==> 0XF8000B6C[9:9] = 0x00000001U */
10456 /* .. ==> MASK : 0x00000200U VAL : 0x00000200U */
10457 /* .. REFIO_PULLUP_EN = 0x0 */
10458 /* .. ==> 0XF8000B6C[12:12] = 0x00000000U */
10459 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10460 /* .. DRST_B_PULLUP_EN = 0x0 */
10461 /* .. ==> 0XF8000B6C[13:13] = 0x00000000U */
10462 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10463 /* .. CKE_PULLUP_EN = 0x0 */
10464 /* .. ==> 0XF8000B6C[14:14] = 0x00000000U */
10465 /* .. ==> MASK : 0x00004000U VAL : 0x00000000U */
10466 /* .. */
10467 EMIT_MASKWRITE(0XF8000B6C, 0x000073FFU, 0x00000260U),
10468 /* .. .. START: ASSERT RESET */
10469 /* .. .. RESET = 1 */
10470 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
10471 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
10472 /* .. .. VRN_OUT = 0x1 */
10473 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
10474 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
10475 /* .. .. */
10476 EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000021U),
10477 /* .. .. FINISH: ASSERT RESET */
10478 /* .. .. START: DEASSERT RESET */
10479 /* .. .. RESET = 0 */
10480 /* .. .. ==> 0XF8000B70[0:0] = 0x00000000U */
10481 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10482 /* .. .. VRN_OUT = 0x1 */
10483 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
10484 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
10485 /* .. .. */
10486 EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
10487 /* .. .. FINISH: DEASSERT RESET */
10488 /* .. .. RESET = 0x1 */
10489 /* .. .. ==> 0XF8000B70[0:0] = 0x00000001U */
10490 /* .. .. ==> MASK : 0x00000001U VAL : 0x00000001U */
10491 /* .. .. ENABLE = 0x1 */
10492 /* .. .. ==> 0XF8000B70[1:1] = 0x00000001U */
10493 /* .. .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10494 /* .. .. VRP_TRI = 0x0 */
10495 /* .. .. ==> 0XF8000B70[2:2] = 0x00000000U */
10496 /* .. .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10497 /* .. .. VRN_TRI = 0x0 */
10498 /* .. .. ==> 0XF8000B70[3:3] = 0x00000000U */
10499 /* .. .. ==> MASK : 0x00000008U VAL : 0x00000000U */
10500 /* .. .. VRP_OUT = 0x0 */
10501 /* .. .. ==> 0XF8000B70[4:4] = 0x00000000U */
10502 /* .. .. ==> MASK : 0x00000010U VAL : 0x00000000U */
10503 /* .. .. VRN_OUT = 0x1 */
10504 /* .. .. ==> 0XF8000B70[5:5] = 0x00000001U */
10505 /* .. .. ==> MASK : 0x00000020U VAL : 0x00000020U */
10506 /* .. .. NREF_OPT1 = 0x0 */
10507 /* .. .. ==> 0XF8000B70[7:6] = 0x00000000U */
10508 /* .. .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
10509 /* .. .. NREF_OPT2 = 0x0 */
10510 /* .. .. ==> 0XF8000B70[10:8] = 0x00000000U */
10511 /* .. .. ==> MASK : 0x00000700U VAL : 0x00000000U */
10512 /* .. .. NREF_OPT4 = 0x1 */
10513 /* .. .. ==> 0XF8000B70[13:11] = 0x00000001U */
10514 /* .. .. ==> MASK : 0x00003800U VAL : 0x00000800U */
10515 /* .. .. PREF_OPT1 = 0x0 */
10516 /* .. .. ==> 0XF8000B70[16:14] = 0x00000000U */
10517 /* .. .. ==> MASK : 0x0001C000U VAL : 0x00000000U */
10518 /* .. .. PREF_OPT2 = 0x0 */
10519 /* .. .. ==> 0XF8000B70[19:17] = 0x00000000U */
10520 /* .. .. ==> MASK : 0x000E0000U VAL : 0x00000000U */
10521 /* .. .. UPDATE_CONTROL = 0x0 */
10522 /* .. .. ==> 0XF8000B70[20:20] = 0x00000000U */
10523 /* .. .. ==> MASK : 0x00100000U VAL : 0x00000000U */
10524 /* .. .. INIT_COMPLETE = 0x0 */
10525 /* .. .. ==> 0XF8000B70[21:21] = 0x00000000U */
10526 /* .. .. ==> MASK : 0x00200000U VAL : 0x00000000U */
10527 /* .. .. TST_CLK = 0x0 */
10528 /* .. .. ==> 0XF8000B70[22:22] = 0x00000000U */
10529 /* .. .. ==> MASK : 0x00400000U VAL : 0x00000000U */
10530 /* .. .. TST_HLN = 0x0 */
10531 /* .. .. ==> 0XF8000B70[23:23] = 0x00000000U */
10532 /* .. .. ==> MASK : 0x00800000U VAL : 0x00000000U */
10533 /* .. .. TST_HLP = 0x0 */
10534 /* .. .. ==> 0XF8000B70[24:24] = 0x00000000U */
10535 /* .. .. ==> MASK : 0x01000000U VAL : 0x00000000U */
10536 /* .. .. TST_RST = 0x0 */
10537 /* .. .. ==> 0XF8000B70[25:25] = 0x00000000U */
10538 /* .. .. ==> MASK : 0x02000000U VAL : 0x00000000U */
10539 /* .. .. INT_DCI_EN = 0x0 */
10540 /* .. .. ==> 0XF8000B70[26:26] = 0x00000000U */
10541 /* .. .. ==> MASK : 0x04000000U VAL : 0x00000000U */
10542 /* .. .. */
10543 EMIT_MASKWRITE(0XF8000B70, 0x07FFFFFFU, 0x00000823U),
10544 /* .. FINISH: DDRIOB SETTINGS */
10545 /* .. START: MIO PROGRAMMING */
10546 /* .. TRI_ENABLE = 0 */
10547 /* .. ==> 0XF8000700[0:0] = 0x00000000U */
10548 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10549 /* .. L0_SEL = 0 */
10550 /* .. ==> 0XF8000700[1:1] = 0x00000000U */
10551 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10552 /* .. L1_SEL = 0 */
10553 /* .. ==> 0XF8000700[2:2] = 0x00000000U */
10554 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10555 /* .. L2_SEL = 0 */
10556 /* .. ==> 0XF8000700[4:3] = 0x00000000U */
10557 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10558 /* .. L3_SEL = 0 */
10559 /* .. ==> 0XF8000700[7:5] = 0x00000000U */
10560 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10561 /* .. Speed = 0 */
10562 /* .. ==> 0XF8000700[8:8] = 0x00000000U */
10563 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10564 /* .. IO_Type = 3 */
10565 /* .. ==> 0XF8000700[11:9] = 0x00000003U */
10566 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10567 /* .. PULLUP = 1 */
10568 /* .. ==> 0XF8000700[12:12] = 0x00000001U */
10569 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10570 /* .. DisableRcvr = 0 */
10571 /* .. ==> 0XF8000700[13:13] = 0x00000000U */
10572 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10573 /* .. */
10574 EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
10575 /* .. TRI_ENABLE = 0 */
10576 /* .. ==> 0XF8000704[0:0] = 0x00000000U */
10577 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10578 /* .. L0_SEL = 1 */
10579 /* .. ==> 0XF8000704[1:1] = 0x00000001U */
10580 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10581 /* .. L1_SEL = 0 */
10582 /* .. ==> 0XF8000704[2:2] = 0x00000000U */
10583 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10584 /* .. L2_SEL = 0 */
10585 /* .. ==> 0XF8000704[4:3] = 0x00000000U */
10586 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10587 /* .. L3_SEL = 0 */
10588 /* .. ==> 0XF8000704[7:5] = 0x00000000U */
10589 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10590 /* .. Speed = 1 */
10591 /* .. ==> 0XF8000704[8:8] = 0x00000001U */
10592 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10593 /* .. IO_Type = 3 */
10594 /* .. ==> 0XF8000704[11:9] = 0x00000003U */
10595 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10596 /* .. PULLUP = 0 */
10597 /* .. ==> 0XF8000704[12:12] = 0x00000000U */
10598 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10599 /* .. DisableRcvr = 0 */
10600 /* .. ==> 0XF8000704[13:13] = 0x00000000U */
10601 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10602 /* .. */
10603 EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00000702U),
10604 /* .. TRI_ENABLE = 0 */
10605 /* .. ==> 0XF8000708[0:0] = 0x00000000U */
10606 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10607 /* .. L0_SEL = 1 */
10608 /* .. ==> 0XF8000708[1:1] = 0x00000001U */
10609 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10610 /* .. L1_SEL = 0 */
10611 /* .. ==> 0XF8000708[2:2] = 0x00000000U */
10612 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10613 /* .. L2_SEL = 0 */
10614 /* .. ==> 0XF8000708[4:3] = 0x00000000U */
10615 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10616 /* .. L3_SEL = 0 */
10617 /* .. ==> 0XF8000708[7:5] = 0x00000000U */
10618 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10619 /* .. Speed = 1 */
10620 /* .. ==> 0XF8000708[8:8] = 0x00000001U */
10621 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10622 /* .. IO_Type = 3 */
10623 /* .. ==> 0XF8000708[11:9] = 0x00000003U */
10624 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10625 /* .. PULLUP = 0 */
10626 /* .. ==> 0XF8000708[12:12] = 0x00000000U */
10627 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10628 /* .. DisableRcvr = 0 */
10629 /* .. ==> 0XF8000708[13:13] = 0x00000000U */
10630 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10631 /* .. */
10632 EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000702U),
10633 /* .. TRI_ENABLE = 0 */
10634 /* .. ==> 0XF800070C[0:0] = 0x00000000U */
10635 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10636 /* .. L0_SEL = 1 */
10637 /* .. ==> 0XF800070C[1:1] = 0x00000001U */
10638 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10639 /* .. L1_SEL = 0 */
10640 /* .. ==> 0XF800070C[2:2] = 0x00000000U */
10641 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10642 /* .. L2_SEL = 0 */
10643 /* .. ==> 0XF800070C[4:3] = 0x00000000U */
10644 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10645 /* .. L3_SEL = 0 */
10646 /* .. ==> 0XF800070C[7:5] = 0x00000000U */
10647 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10648 /* .. Speed = 1 */
10649 /* .. ==> 0XF800070C[8:8] = 0x00000001U */
10650 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10651 /* .. IO_Type = 3 */
10652 /* .. ==> 0XF800070C[11:9] = 0x00000003U */
10653 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10654 /* .. PULLUP = 0 */
10655 /* .. ==> 0XF800070C[12:12] = 0x00000000U */
10656 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10657 /* .. DisableRcvr = 0 */
10658 /* .. ==> 0XF800070C[13:13] = 0x00000000U */
10659 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10660 /* .. */
10661 EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000702U),
10662 /* .. TRI_ENABLE = 0 */
10663 /* .. ==> 0XF8000710[0:0] = 0x00000000U */
10664 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10665 /* .. L0_SEL = 1 */
10666 /* .. ==> 0XF8000710[1:1] = 0x00000001U */
10667 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10668 /* .. L1_SEL = 0 */
10669 /* .. ==> 0XF8000710[2:2] = 0x00000000U */
10670 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10671 /* .. L2_SEL = 0 */
10672 /* .. ==> 0XF8000710[4:3] = 0x00000000U */
10673 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10674 /* .. L3_SEL = 0 */
10675 /* .. ==> 0XF8000710[7:5] = 0x00000000U */
10676 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10677 /* .. Speed = 1 */
10678 /* .. ==> 0XF8000710[8:8] = 0x00000001U */
10679 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10680 /* .. IO_Type = 3 */
10681 /* .. ==> 0XF8000710[11:9] = 0x00000003U */
10682 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10683 /* .. PULLUP = 0 */
10684 /* .. ==> 0XF8000710[12:12] = 0x00000000U */
10685 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10686 /* .. DisableRcvr = 0 */
10687 /* .. ==> 0XF8000710[13:13] = 0x00000000U */
10688 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10689 /* .. */
10690 EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000702U),
10691 /* .. TRI_ENABLE = 0 */
10692 /* .. ==> 0XF8000714[0:0] = 0x00000000U */
10693 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10694 /* .. L0_SEL = 1 */
10695 /* .. ==> 0XF8000714[1:1] = 0x00000001U */
10696 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10697 /* .. L1_SEL = 0 */
10698 /* .. ==> 0XF8000714[2:2] = 0x00000000U */
10699 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10700 /* .. L2_SEL = 0 */
10701 /* .. ==> 0XF8000714[4:3] = 0x00000000U */
10702 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10703 /* .. L3_SEL = 0 */
10704 /* .. ==> 0XF8000714[7:5] = 0x00000000U */
10705 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10706 /* .. Speed = 1 */
10707 /* .. ==> 0XF8000714[8:8] = 0x00000001U */
10708 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10709 /* .. IO_Type = 3 */
10710 /* .. ==> 0XF8000714[11:9] = 0x00000003U */
10711 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10712 /* .. PULLUP = 0 */
10713 /* .. ==> 0XF8000714[12:12] = 0x00000000U */
10714 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10715 /* .. DisableRcvr = 0 */
10716 /* .. ==> 0XF8000714[13:13] = 0x00000000U */
10717 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10718 /* .. */
10719 EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000702U),
10720 /* .. TRI_ENABLE = 0 */
10721 /* .. ==> 0XF8000718[0:0] = 0x00000000U */
10722 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10723 /* .. L0_SEL = 1 */
10724 /* .. ==> 0XF8000718[1:1] = 0x00000001U */
10725 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10726 /* .. L1_SEL = 0 */
10727 /* .. ==> 0XF8000718[2:2] = 0x00000000U */
10728 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10729 /* .. L2_SEL = 0 */
10730 /* .. ==> 0XF8000718[4:3] = 0x00000000U */
10731 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10732 /* .. L3_SEL = 0 */
10733 /* .. ==> 0XF8000718[7:5] = 0x00000000U */
10734 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10735 /* .. Speed = 1 */
10736 /* .. ==> 0XF8000718[8:8] = 0x00000001U */
10737 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10738 /* .. IO_Type = 3 */
10739 /* .. ==> 0XF8000718[11:9] = 0x00000003U */
10740 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10741 /* .. PULLUP = 0 */
10742 /* .. ==> 0XF8000718[12:12] = 0x00000000U */
10743 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10744 /* .. DisableRcvr = 0 */
10745 /* .. ==> 0XF8000718[13:13] = 0x00000000U */
10746 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10747 /* .. */
10748 EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000702U),
10749 /* .. TRI_ENABLE = 0 */
10750 /* .. ==> 0XF800071C[0:0] = 0x00000000U */
10751 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10752 /* .. L0_SEL = 0 */
10753 /* .. ==> 0XF800071C[1:1] = 0x00000000U */
10754 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10755 /* .. L1_SEL = 0 */
10756 /* .. ==> 0XF800071C[2:2] = 0x00000000U */
10757 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10758 /* .. L2_SEL = 0 */
10759 /* .. ==> 0XF800071C[4:3] = 0x00000000U */
10760 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10761 /* .. L3_SEL = 0 */
10762 /* .. ==> 0XF800071C[7:5] = 0x00000000U */
10763 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10764 /* .. Speed = 0 */
10765 /* .. ==> 0XF800071C[8:8] = 0x00000000U */
10766 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10767 /* .. IO_Type = 3 */
10768 /* .. ==> 0XF800071C[11:9] = 0x00000003U */
10769 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10770 /* .. PULLUP = 0 */
10771 /* .. ==> 0XF800071C[12:12] = 0x00000000U */
10772 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10773 /* .. DisableRcvr = 0 */
10774 /* .. ==> 0XF800071C[13:13] = 0x00000000U */
10775 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10776 /* .. */
10777 EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
10778 /* .. TRI_ENABLE = 0 */
10779 /* .. ==> 0XF8000720[0:0] = 0x00000000U */
10780 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10781 /* .. L0_SEL = 1 */
10782 /* .. ==> 0XF8000720[1:1] = 0x00000001U */
10783 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
10784 /* .. L1_SEL = 0 */
10785 /* .. ==> 0XF8000720[2:2] = 0x00000000U */
10786 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10787 /* .. L2_SEL = 0 */
10788 /* .. ==> 0XF8000720[4:3] = 0x00000000U */
10789 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10790 /* .. L3_SEL = 0 */
10791 /* .. ==> 0XF8000720[7:5] = 0x00000000U */
10792 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10793 /* .. Speed = 1 */
10794 /* .. ==> 0XF8000720[8:8] = 0x00000001U */
10795 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
10796 /* .. IO_Type = 3 */
10797 /* .. ==> 0XF8000720[11:9] = 0x00000003U */
10798 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10799 /* .. PULLUP = 0 */
10800 /* .. ==> 0XF8000720[12:12] = 0x00000000U */
10801 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
10802 /* .. DisableRcvr = 0 */
10803 /* .. ==> 0XF8000720[13:13] = 0x00000000U */
10804 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10805 /* .. */
10806 EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000702U),
10807 /* .. TRI_ENABLE = 0 */
10808 /* .. ==> 0XF8000724[0:0] = 0x00000000U */
10809 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10810 /* .. L0_SEL = 0 */
10811 /* .. ==> 0XF8000724[1:1] = 0x00000000U */
10812 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10813 /* .. L1_SEL = 0 */
10814 /* .. ==> 0XF8000724[2:2] = 0x00000000U */
10815 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10816 /* .. L2_SEL = 0 */
10817 /* .. ==> 0XF8000724[4:3] = 0x00000000U */
10818 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10819 /* .. L3_SEL = 0 */
10820 /* .. ==> 0XF8000724[7:5] = 0x00000000U */
10821 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10822 /* .. Speed = 0 */
10823 /* .. ==> 0XF8000724[8:8] = 0x00000000U */
10824 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10825 /* .. IO_Type = 3 */
10826 /* .. ==> 0XF8000724[11:9] = 0x00000003U */
10827 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10828 /* .. PULLUP = 1 */
10829 /* .. ==> 0XF8000724[12:12] = 0x00000001U */
10830 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10831 /* .. DisableRcvr = 0 */
10832 /* .. ==> 0XF8000724[13:13] = 0x00000000U */
10833 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10834 /* .. */
10835 EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
10836 /* .. TRI_ENABLE = 0 */
10837 /* .. ==> 0XF8000728[0:0] = 0x00000000U */
10838 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10839 /* .. L0_SEL = 0 */
10840 /* .. ==> 0XF8000728[1:1] = 0x00000000U */
10841 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10842 /* .. L1_SEL = 0 */
10843 /* .. ==> 0XF8000728[2:2] = 0x00000000U */
10844 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10845 /* .. L2_SEL = 0 */
10846 /* .. ==> 0XF8000728[4:3] = 0x00000000U */
10847 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10848 /* .. L3_SEL = 0 */
10849 /* .. ==> 0XF8000728[7:5] = 0x00000000U */
10850 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10851 /* .. Speed = 0 */
10852 /* .. ==> 0XF8000728[8:8] = 0x00000000U */
10853 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10854 /* .. IO_Type = 3 */
10855 /* .. ==> 0XF8000728[11:9] = 0x00000003U */
10856 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10857 /* .. PULLUP = 1 */
10858 /* .. ==> 0XF8000728[12:12] = 0x00000001U */
10859 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10860 /* .. DisableRcvr = 0 */
10861 /* .. ==> 0XF8000728[13:13] = 0x00000000U */
10862 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10863 /* .. */
10864 EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
10865 /* .. TRI_ENABLE = 0 */
10866 /* .. ==> 0XF800072C[0:0] = 0x00000000U */
10867 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10868 /* .. L0_SEL = 0 */
10869 /* .. ==> 0XF800072C[1:1] = 0x00000000U */
10870 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10871 /* .. L1_SEL = 0 */
10872 /* .. ==> 0XF800072C[2:2] = 0x00000000U */
10873 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10874 /* .. L2_SEL = 0 */
10875 /* .. ==> 0XF800072C[4:3] = 0x00000000U */
10876 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10877 /* .. L3_SEL = 0 */
10878 /* .. ==> 0XF800072C[7:5] = 0x00000000U */
10879 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10880 /* .. Speed = 0 */
10881 /* .. ==> 0XF800072C[8:8] = 0x00000000U */
10882 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10883 /* .. IO_Type = 3 */
10884 /* .. ==> 0XF800072C[11:9] = 0x00000003U */
10885 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10886 /* .. PULLUP = 1 */
10887 /* .. ==> 0XF800072C[12:12] = 0x00000001U */
10888 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10889 /* .. DisableRcvr = 0 */
10890 /* .. ==> 0XF800072C[13:13] = 0x00000000U */
10891 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10892 /* .. */
10893 EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
10894 /* .. TRI_ENABLE = 0 */
10895 /* .. ==> 0XF8000730[0:0] = 0x00000000U */
10896 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10897 /* .. L0_SEL = 0 */
10898 /* .. ==> 0XF8000730[1:1] = 0x00000000U */
10899 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10900 /* .. L1_SEL = 0 */
10901 /* .. ==> 0XF8000730[2:2] = 0x00000000U */
10902 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10903 /* .. L2_SEL = 0 */
10904 /* .. ==> 0XF8000730[4:3] = 0x00000000U */
10905 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10906 /* .. L3_SEL = 0 */
10907 /* .. ==> 0XF8000730[7:5] = 0x00000000U */
10908 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10909 /* .. Speed = 0 */
10910 /* .. ==> 0XF8000730[8:8] = 0x00000000U */
10911 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10912 /* .. IO_Type = 3 */
10913 /* .. ==> 0XF8000730[11:9] = 0x00000003U */
10914 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10915 /* .. PULLUP = 1 */
10916 /* .. ==> 0XF8000730[12:12] = 0x00000001U */
10917 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10918 /* .. DisableRcvr = 0 */
10919 /* .. ==> 0XF8000730[13:13] = 0x00000000U */
10920 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10921 /* .. */
10922 EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001600U),
10923 /* .. TRI_ENABLE = 0 */
10924 /* .. ==> 0XF8000734[0:0] = 0x00000000U */
10925 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10926 /* .. L0_SEL = 0 */
10927 /* .. ==> 0XF8000734[1:1] = 0x00000000U */
10928 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10929 /* .. L1_SEL = 0 */
10930 /* .. ==> 0XF8000734[2:2] = 0x00000000U */
10931 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10932 /* .. L2_SEL = 0 */
10933 /* .. ==> 0XF8000734[4:3] = 0x00000000U */
10934 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10935 /* .. L3_SEL = 0 */
10936 /* .. ==> 0XF8000734[7:5] = 0x00000000U */
10937 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10938 /* .. Speed = 0 */
10939 /* .. ==> 0XF8000734[8:8] = 0x00000000U */
10940 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10941 /* .. IO_Type = 3 */
10942 /* .. ==> 0XF8000734[11:9] = 0x00000003U */
10943 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10944 /* .. PULLUP = 1 */
10945 /* .. ==> 0XF8000734[12:12] = 0x00000001U */
10946 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10947 /* .. DisableRcvr = 0 */
10948 /* .. ==> 0XF8000734[13:13] = 0x00000000U */
10949 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10950 /* .. */
10951 EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001600U),
10952 /* .. TRI_ENABLE = 0 */
10953 /* .. ==> 0XF8000738[0:0] = 0x00000000U */
10954 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10955 /* .. L0_SEL = 0 */
10956 /* .. ==> 0XF8000738[1:1] = 0x00000000U */
10957 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10958 /* .. L1_SEL = 0 */
10959 /* .. ==> 0XF8000738[2:2] = 0x00000000U */
10960 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10961 /* .. L2_SEL = 0 */
10962 /* .. ==> 0XF8000738[4:3] = 0x00000000U */
10963 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10964 /* .. L3_SEL = 0 */
10965 /* .. ==> 0XF8000738[7:5] = 0x00000000U */
10966 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10967 /* .. Speed = 0 */
10968 /* .. ==> 0XF8000738[8:8] = 0x00000000U */
10969 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10970 /* .. IO_Type = 3 */
10971 /* .. ==> 0XF8000738[11:9] = 0x00000003U */
10972 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
10973 /* .. PULLUP = 1 */
10974 /* .. ==> 0XF8000738[12:12] = 0x00000001U */
10975 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
10976 /* .. DisableRcvr = 0 */
10977 /* .. ==> 0XF8000738[13:13] = 0x00000000U */
10978 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
10979 /* .. */
10980 EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x00001600U),
10981 /* .. TRI_ENABLE = 0 */
10982 /* .. ==> 0XF800073C[0:0] = 0x00000000U */
10983 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
10984 /* .. L0_SEL = 0 */
10985 /* .. ==> 0XF800073C[1:1] = 0x00000000U */
10986 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
10987 /* .. L1_SEL = 0 */
10988 /* .. ==> 0XF800073C[2:2] = 0x00000000U */
10989 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
10990 /* .. L2_SEL = 0 */
10991 /* .. ==> 0XF800073C[4:3] = 0x00000000U */
10992 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
10993 /* .. L3_SEL = 0 */
10994 /* .. ==> 0XF800073C[7:5] = 0x00000000U */
10995 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
10996 /* .. Speed = 0 */
10997 /* .. ==> 0XF800073C[8:8] = 0x00000000U */
10998 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
10999 /* .. IO_Type = 3 */
11000 /* .. ==> 0XF800073C[11:9] = 0x00000003U */
11001 /* .. ==> MASK : 0x00000E00U VAL : 0x00000600U */
11002 /* .. PULLUP = 1 */
11003 /* .. ==> 0XF800073C[12:12] = 0x00000001U */
11004 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
11005 /* .. DisableRcvr = 0 */
11006 /* .. ==> 0XF800073C[13:13] = 0x00000000U */
11007 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11008 /* .. */
11009 EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x00001600U),
11010 /* .. TRI_ENABLE = 0 */
11011 /* .. ==> 0XF8000740[0:0] = 0x00000000U */
11012 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11013 /* .. L0_SEL = 1 */
11014 /* .. ==> 0XF8000740[1:1] = 0x00000001U */
11015 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11016 /* .. L1_SEL = 0 */
11017 /* .. ==> 0XF8000740[2:2] = 0x00000000U */
11018 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11019 /* .. L2_SEL = 0 */
11020 /* .. ==> 0XF8000740[4:3] = 0x00000000U */
11021 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11022 /* .. L3_SEL = 0 */
11023 /* .. ==> 0XF8000740[7:5] = 0x00000000U */
11024 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11025 /* .. Speed = 1 */
11026 /* .. ==> 0XF8000740[8:8] = 0x00000001U */
11027 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11028 /* .. IO_Type = 4 */
11029 /* .. ==> 0XF8000740[11:9] = 0x00000004U */
11030 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11031 /* .. PULLUP = 0 */
11032 /* .. ==> 0XF8000740[12:12] = 0x00000000U */
11033 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11034 /* .. DisableRcvr = 1 */
11035 /* .. ==> 0XF8000740[13:13] = 0x00000001U */
11036 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11037 /* .. */
11038 EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00002902U),
11039 /* .. TRI_ENABLE = 0 */
11040 /* .. ==> 0XF8000744[0:0] = 0x00000000U */
11041 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11042 /* .. L0_SEL = 1 */
11043 /* .. ==> 0XF8000744[1:1] = 0x00000001U */
11044 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11045 /* .. L1_SEL = 0 */
11046 /* .. ==> 0XF8000744[2:2] = 0x00000000U */
11047 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11048 /* .. L2_SEL = 0 */
11049 /* .. ==> 0XF8000744[4:3] = 0x00000000U */
11050 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11051 /* .. L3_SEL = 0 */
11052 /* .. ==> 0XF8000744[7:5] = 0x00000000U */
11053 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11054 /* .. Speed = 1 */
11055 /* .. ==> 0XF8000744[8:8] = 0x00000001U */
11056 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11057 /* .. IO_Type = 4 */
11058 /* .. ==> 0XF8000744[11:9] = 0x00000004U */
11059 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11060 /* .. PULLUP = 0 */
11061 /* .. ==> 0XF8000744[12:12] = 0x00000000U */
11062 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11063 /* .. DisableRcvr = 1 */
11064 /* .. ==> 0XF8000744[13:13] = 0x00000001U */
11065 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11066 /* .. */
11067 EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00002902U),
11068 /* .. TRI_ENABLE = 0 */
11069 /* .. ==> 0XF8000748[0:0] = 0x00000000U */
11070 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11071 /* .. L0_SEL = 1 */
11072 /* .. ==> 0XF8000748[1:1] = 0x00000001U */
11073 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11074 /* .. L1_SEL = 0 */
11075 /* .. ==> 0XF8000748[2:2] = 0x00000000U */
11076 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11077 /* .. L2_SEL = 0 */
11078 /* .. ==> 0XF8000748[4:3] = 0x00000000U */
11079 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11080 /* .. L3_SEL = 0 */
11081 /* .. ==> 0XF8000748[7:5] = 0x00000000U */
11082 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11083 /* .. Speed = 1 */
11084 /* .. ==> 0XF8000748[8:8] = 0x00000001U */
11085 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11086 /* .. IO_Type = 4 */
11087 /* .. ==> 0XF8000748[11:9] = 0x00000004U */
11088 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11089 /* .. PULLUP = 0 */
11090 /* .. ==> 0XF8000748[12:12] = 0x00000000U */
11091 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11092 /* .. DisableRcvr = 1 */
11093 /* .. ==> 0XF8000748[13:13] = 0x00000001U */
11094 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11095 /* .. */
11096 EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00002902U),
11097 /* .. TRI_ENABLE = 0 */
11098 /* .. ==> 0XF800074C[0:0] = 0x00000000U */
11099 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11100 /* .. L0_SEL = 1 */
11101 /* .. ==> 0XF800074C[1:1] = 0x00000001U */
11102 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11103 /* .. L1_SEL = 0 */
11104 /* .. ==> 0XF800074C[2:2] = 0x00000000U */
11105 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11106 /* .. L2_SEL = 0 */
11107 /* .. ==> 0XF800074C[4:3] = 0x00000000U */
11108 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11109 /* .. L3_SEL = 0 */
11110 /* .. ==> 0XF800074C[7:5] = 0x00000000U */
11111 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11112 /* .. Speed = 1 */
11113 /* .. ==> 0XF800074C[8:8] = 0x00000001U */
11114 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11115 /* .. IO_Type = 4 */
11116 /* .. ==> 0XF800074C[11:9] = 0x00000004U */
11117 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11118 /* .. PULLUP = 0 */
11119 /* .. ==> 0XF800074C[12:12] = 0x00000000U */
11120 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11121 /* .. DisableRcvr = 1 */
11122 /* .. ==> 0XF800074C[13:13] = 0x00000001U */
11123 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11124 /* .. */
11125 EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00002902U),
11126 /* .. TRI_ENABLE = 0 */
11127 /* .. ==> 0XF8000750[0:0] = 0x00000000U */
11128 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11129 /* .. L0_SEL = 1 */
11130 /* .. ==> 0XF8000750[1:1] = 0x00000001U */
11131 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11132 /* .. L1_SEL = 0 */
11133 /* .. ==> 0XF8000750[2:2] = 0x00000000U */
11134 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11135 /* .. L2_SEL = 0 */
11136 /* .. ==> 0XF8000750[4:3] = 0x00000000U */
11137 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11138 /* .. L3_SEL = 0 */
11139 /* .. ==> 0XF8000750[7:5] = 0x00000000U */
11140 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11141 /* .. Speed = 1 */
11142 /* .. ==> 0XF8000750[8:8] = 0x00000001U */
11143 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11144 /* .. IO_Type = 4 */
11145 /* .. ==> 0XF8000750[11:9] = 0x00000004U */
11146 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11147 /* .. PULLUP = 0 */
11148 /* .. ==> 0XF8000750[12:12] = 0x00000000U */
11149 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11150 /* .. DisableRcvr = 1 */
11151 /* .. ==> 0XF8000750[13:13] = 0x00000001U */
11152 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11153 /* .. */
11154 EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00002902U),
11155 /* .. TRI_ENABLE = 0 */
11156 /* .. ==> 0XF8000754[0:0] = 0x00000000U */
11157 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11158 /* .. L0_SEL = 1 */
11159 /* .. ==> 0XF8000754[1:1] = 0x00000001U */
11160 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11161 /* .. L1_SEL = 0 */
11162 /* .. ==> 0XF8000754[2:2] = 0x00000000U */
11163 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11164 /* .. L2_SEL = 0 */
11165 /* .. ==> 0XF8000754[4:3] = 0x00000000U */
11166 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11167 /* .. L3_SEL = 0 */
11168 /* .. ==> 0XF8000754[7:5] = 0x00000000U */
11169 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11170 /* .. Speed = 1 */
11171 /* .. ==> 0XF8000754[8:8] = 0x00000001U */
11172 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11173 /* .. IO_Type = 4 */
11174 /* .. ==> 0XF8000754[11:9] = 0x00000004U */
11175 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11176 /* .. PULLUP = 0 */
11177 /* .. ==> 0XF8000754[12:12] = 0x00000000U */
11178 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11179 /* .. DisableRcvr = 1 */
11180 /* .. ==> 0XF8000754[13:13] = 0x00000001U */
11181 /* .. ==> MASK : 0x00002000U VAL : 0x00002000U */
11182 /* .. */
11183 EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00002902U),
11184 /* .. TRI_ENABLE = 1 */
11185 /* .. ==> 0XF8000758[0:0] = 0x00000001U */
11186 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11187 /* .. L0_SEL = 1 */
11188 /* .. ==> 0XF8000758[1:1] = 0x00000001U */
11189 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11190 /* .. L1_SEL = 0 */
11191 /* .. ==> 0XF8000758[2:2] = 0x00000000U */
11192 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11193 /* .. L2_SEL = 0 */
11194 /* .. ==> 0XF8000758[4:3] = 0x00000000U */
11195 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11196 /* .. L3_SEL = 0 */
11197 /* .. ==> 0XF8000758[7:5] = 0x00000000U */
11198 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11199 /* .. Speed = 1 */
11200 /* .. ==> 0XF8000758[8:8] = 0x00000001U */
11201 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11202 /* .. IO_Type = 4 */
11203 /* .. ==> 0XF8000758[11:9] = 0x00000004U */
11204 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11205 /* .. PULLUP = 0 */
11206 /* .. ==> 0XF8000758[12:12] = 0x00000000U */
11207 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11208 /* .. DisableRcvr = 0 */
11209 /* .. ==> 0XF8000758[13:13] = 0x00000000U */
11210 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11211 /* .. */
11212 EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00000903U),
11213 /* .. TRI_ENABLE = 1 */
11214 /* .. ==> 0XF800075C[0:0] = 0x00000001U */
11215 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11216 /* .. L0_SEL = 1 */
11217 /* .. ==> 0XF800075C[1:1] = 0x00000001U */
11218 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11219 /* .. L1_SEL = 0 */
11220 /* .. ==> 0XF800075C[2:2] = 0x00000000U */
11221 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11222 /* .. L2_SEL = 0 */
11223 /* .. ==> 0XF800075C[4:3] = 0x00000000U */
11224 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11225 /* .. L3_SEL = 0 */
11226 /* .. ==> 0XF800075C[7:5] = 0x00000000U */
11227 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11228 /* .. Speed = 1 */
11229 /* .. ==> 0XF800075C[8:8] = 0x00000001U */
11230 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11231 /* .. IO_Type = 4 */
11232 /* .. ==> 0XF800075C[11:9] = 0x00000004U */
11233 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11234 /* .. PULLUP = 0 */
11235 /* .. ==> 0XF800075C[12:12] = 0x00000000U */
11236 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11237 /* .. DisableRcvr = 0 */
11238 /* .. ==> 0XF800075C[13:13] = 0x00000000U */
11239 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11240 /* .. */
11241 EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00000903U),
11242 /* .. TRI_ENABLE = 1 */
11243 /* .. ==> 0XF8000760[0:0] = 0x00000001U */
11244 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11245 /* .. L0_SEL = 1 */
11246 /* .. ==> 0XF8000760[1:1] = 0x00000001U */
11247 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11248 /* .. L1_SEL = 0 */
11249 /* .. ==> 0XF8000760[2:2] = 0x00000000U */
11250 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11251 /* .. L2_SEL = 0 */
11252 /* .. ==> 0XF8000760[4:3] = 0x00000000U */
11253 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11254 /* .. L3_SEL = 0 */
11255 /* .. ==> 0XF8000760[7:5] = 0x00000000U */
11256 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11257 /* .. Speed = 1 */
11258 /* .. ==> 0XF8000760[8:8] = 0x00000001U */
11259 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11260 /* .. IO_Type = 4 */
11261 /* .. ==> 0XF8000760[11:9] = 0x00000004U */
11262 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11263 /* .. PULLUP = 0 */
11264 /* .. ==> 0XF8000760[12:12] = 0x00000000U */
11265 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11266 /* .. DisableRcvr = 0 */
11267 /* .. ==> 0XF8000760[13:13] = 0x00000000U */
11268 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11269 /* .. */
11270 EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00000903U),
11271 /* .. TRI_ENABLE = 1 */
11272 /* .. ==> 0XF8000764[0:0] = 0x00000001U */
11273 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11274 /* .. L0_SEL = 1 */
11275 /* .. ==> 0XF8000764[1:1] = 0x00000001U */
11276 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11277 /* .. L1_SEL = 0 */
11278 /* .. ==> 0XF8000764[2:2] = 0x00000000U */
11279 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11280 /* .. L2_SEL = 0 */
11281 /* .. ==> 0XF8000764[4:3] = 0x00000000U */
11282 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11283 /* .. L3_SEL = 0 */
11284 /* .. ==> 0XF8000764[7:5] = 0x00000000U */
11285 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11286 /* .. Speed = 1 */
11287 /* .. ==> 0XF8000764[8:8] = 0x00000001U */
11288 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11289 /* .. IO_Type = 4 */
11290 /* .. ==> 0XF8000764[11:9] = 0x00000004U */
11291 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11292 /* .. PULLUP = 0 */
11293 /* .. ==> 0XF8000764[12:12] = 0x00000000U */
11294 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11295 /* .. DisableRcvr = 0 */
11296 /* .. ==> 0XF8000764[13:13] = 0x00000000U */
11297 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11298 /* .. */
11299 EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00000903U),
11300 /* .. TRI_ENABLE = 1 */
11301 /* .. ==> 0XF8000768[0:0] = 0x00000001U */
11302 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11303 /* .. L0_SEL = 1 */
11304 /* .. ==> 0XF8000768[1:1] = 0x00000001U */
11305 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11306 /* .. L1_SEL = 0 */
11307 /* .. ==> 0XF8000768[2:2] = 0x00000000U */
11308 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11309 /* .. L2_SEL = 0 */
11310 /* .. ==> 0XF8000768[4:3] = 0x00000000U */
11311 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11312 /* .. L3_SEL = 0 */
11313 /* .. ==> 0XF8000768[7:5] = 0x00000000U */
11314 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11315 /* .. Speed = 1 */
11316 /* .. ==> 0XF8000768[8:8] = 0x00000001U */
11317 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11318 /* .. IO_Type = 4 */
11319 /* .. ==> 0XF8000768[11:9] = 0x00000004U */
11320 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11321 /* .. PULLUP = 0 */
11322 /* .. ==> 0XF8000768[12:12] = 0x00000000U */
11323 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11324 /* .. DisableRcvr = 0 */
11325 /* .. ==> 0XF8000768[13:13] = 0x00000000U */
11326 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11327 /* .. */
11328 EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00000903U),
11329 /* .. TRI_ENABLE = 1 */
11330 /* .. ==> 0XF800076C[0:0] = 0x00000001U */
11331 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11332 /* .. L0_SEL = 1 */
11333 /* .. ==> 0XF800076C[1:1] = 0x00000001U */
11334 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
11335 /* .. L1_SEL = 0 */
11336 /* .. ==> 0XF800076C[2:2] = 0x00000000U */
11337 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11338 /* .. L2_SEL = 0 */
11339 /* .. ==> 0XF800076C[4:3] = 0x00000000U */
11340 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11341 /* .. L3_SEL = 0 */
11342 /* .. ==> 0XF800076C[7:5] = 0x00000000U */
11343 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11344 /* .. Speed = 1 */
11345 /* .. ==> 0XF800076C[8:8] = 0x00000001U */
11346 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11347 /* .. IO_Type = 4 */
11348 /* .. ==> 0XF800076C[11:9] = 0x00000004U */
11349 /* .. ==> MASK : 0x00000E00U VAL : 0x00000800U */
11350 /* .. PULLUP = 0 */
11351 /* .. ==> 0XF800076C[12:12] = 0x00000000U */
11352 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11353 /* .. DisableRcvr = 0 */
11354 /* .. ==> 0XF800076C[13:13] = 0x00000000U */
11355 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11356 /* .. */
11357 EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00000903U),
11358 /* .. TRI_ENABLE = 0 */
11359 /* .. ==> 0XF8000770[0:0] = 0x00000000U */
11360 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11361 /* .. L0_SEL = 0 */
11362 /* .. ==> 0XF8000770[1:1] = 0x00000000U */
11363 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11364 /* .. L1_SEL = 1 */
11365 /* .. ==> 0XF8000770[2:2] = 0x00000001U */
11366 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11367 /* .. L2_SEL = 0 */
11368 /* .. ==> 0XF8000770[4:3] = 0x00000000U */
11369 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11370 /* .. L3_SEL = 0 */
11371 /* .. ==> 0XF8000770[7:5] = 0x00000000U */
11372 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11373 /* .. Speed = 1 */
11374 /* .. ==> 0XF8000770[8:8] = 0x00000001U */
11375 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11376 /* .. IO_Type = 1 */
11377 /* .. ==> 0XF8000770[11:9] = 0x00000001U */
11378 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11379 /* .. PULLUP = 0 */
11380 /* .. ==> 0XF8000770[12:12] = 0x00000000U */
11381 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11382 /* .. DisableRcvr = 0 */
11383 /* .. ==> 0XF8000770[13:13] = 0x00000000U */
11384 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11385 /* .. */
11386 EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00000304U),
11387 /* .. TRI_ENABLE = 1 */
11388 /* .. ==> 0XF8000774[0:0] = 0x00000001U */
11389 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11390 /* .. L0_SEL = 0 */
11391 /* .. ==> 0XF8000774[1:1] = 0x00000000U */
11392 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11393 /* .. L1_SEL = 1 */
11394 /* .. ==> 0XF8000774[2:2] = 0x00000001U */
11395 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11396 /* .. L2_SEL = 0 */
11397 /* .. ==> 0XF8000774[4:3] = 0x00000000U */
11398 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11399 /* .. L3_SEL = 0 */
11400 /* .. ==> 0XF8000774[7:5] = 0x00000000U */
11401 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11402 /* .. Speed = 1 */
11403 /* .. ==> 0XF8000774[8:8] = 0x00000001U */
11404 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11405 /* .. IO_Type = 1 */
11406 /* .. ==> 0XF8000774[11:9] = 0x00000001U */
11407 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11408 /* .. PULLUP = 0 */
11409 /* .. ==> 0XF8000774[12:12] = 0x00000000U */
11410 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11411 /* .. DisableRcvr = 0 */
11412 /* .. ==> 0XF8000774[13:13] = 0x00000000U */
11413 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11414 /* .. */
11415 EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00000305U),
11416 /* .. TRI_ENABLE = 0 */
11417 /* .. ==> 0XF8000778[0:0] = 0x00000000U */
11418 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11419 /* .. L0_SEL = 0 */
11420 /* .. ==> 0XF8000778[1:1] = 0x00000000U */
11421 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11422 /* .. L1_SEL = 1 */
11423 /* .. ==> 0XF8000778[2:2] = 0x00000001U */
11424 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11425 /* .. L2_SEL = 0 */
11426 /* .. ==> 0XF8000778[4:3] = 0x00000000U */
11427 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11428 /* .. L3_SEL = 0 */
11429 /* .. ==> 0XF8000778[7:5] = 0x00000000U */
11430 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11431 /* .. Speed = 1 */
11432 /* .. ==> 0XF8000778[8:8] = 0x00000001U */
11433 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11434 /* .. IO_Type = 1 */
11435 /* .. ==> 0XF8000778[11:9] = 0x00000001U */
11436 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11437 /* .. PULLUP = 0 */
11438 /* .. ==> 0XF8000778[12:12] = 0x00000000U */
11439 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11440 /* .. DisableRcvr = 0 */
11441 /* .. ==> 0XF8000778[13:13] = 0x00000000U */
11442 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11443 /* .. */
11444 EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00000304U),
11445 /* .. TRI_ENABLE = 1 */
11446 /* .. ==> 0XF800077C[0:0] = 0x00000001U */
11447 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11448 /* .. L0_SEL = 0 */
11449 /* .. ==> 0XF800077C[1:1] = 0x00000000U */
11450 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11451 /* .. L1_SEL = 1 */
11452 /* .. ==> 0XF800077C[2:2] = 0x00000001U */
11453 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11454 /* .. L2_SEL = 0 */
11455 /* .. ==> 0XF800077C[4:3] = 0x00000000U */
11456 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11457 /* .. L3_SEL = 0 */
11458 /* .. ==> 0XF800077C[7:5] = 0x00000000U */
11459 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11460 /* .. Speed = 1 */
11461 /* .. ==> 0XF800077C[8:8] = 0x00000001U */
11462 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11463 /* .. IO_Type = 1 */
11464 /* .. ==> 0XF800077C[11:9] = 0x00000001U */
11465 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11466 /* .. PULLUP = 0 */
11467 /* .. ==> 0XF800077C[12:12] = 0x00000000U */
11468 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11469 /* .. DisableRcvr = 0 */
11470 /* .. ==> 0XF800077C[13:13] = 0x00000000U */
11471 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11472 /* .. */
11473 EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00000305U),
11474 /* .. TRI_ENABLE = 0 */
11475 /* .. ==> 0XF8000780[0:0] = 0x00000000U */
11476 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11477 /* .. L0_SEL = 0 */
11478 /* .. ==> 0XF8000780[1:1] = 0x00000000U */
11479 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11480 /* .. L1_SEL = 1 */
11481 /* .. ==> 0XF8000780[2:2] = 0x00000001U */
11482 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11483 /* .. L2_SEL = 0 */
11484 /* .. ==> 0XF8000780[4:3] = 0x00000000U */
11485 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11486 /* .. L3_SEL = 0 */
11487 /* .. ==> 0XF8000780[7:5] = 0x00000000U */
11488 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11489 /* .. Speed = 1 */
11490 /* .. ==> 0XF8000780[8:8] = 0x00000001U */
11491 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11492 /* .. IO_Type = 1 */
11493 /* .. ==> 0XF8000780[11:9] = 0x00000001U */
11494 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11495 /* .. PULLUP = 0 */
11496 /* .. ==> 0XF8000780[12:12] = 0x00000000U */
11497 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11498 /* .. DisableRcvr = 0 */
11499 /* .. ==> 0XF8000780[13:13] = 0x00000000U */
11500 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11501 /* .. */
11502 EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00000304U),
11503 /* .. TRI_ENABLE = 0 */
11504 /* .. ==> 0XF8000784[0:0] = 0x00000000U */
11505 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11506 /* .. L0_SEL = 0 */
11507 /* .. ==> 0XF8000784[1:1] = 0x00000000U */
11508 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11509 /* .. L1_SEL = 1 */
11510 /* .. ==> 0XF8000784[2:2] = 0x00000001U */
11511 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11512 /* .. L2_SEL = 0 */
11513 /* .. ==> 0XF8000784[4:3] = 0x00000000U */
11514 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11515 /* .. L3_SEL = 0 */
11516 /* .. ==> 0XF8000784[7:5] = 0x00000000U */
11517 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11518 /* .. Speed = 1 */
11519 /* .. ==> 0XF8000784[8:8] = 0x00000001U */
11520 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11521 /* .. IO_Type = 1 */
11522 /* .. ==> 0XF8000784[11:9] = 0x00000001U */
11523 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11524 /* .. PULLUP = 0 */
11525 /* .. ==> 0XF8000784[12:12] = 0x00000000U */
11526 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11527 /* .. DisableRcvr = 0 */
11528 /* .. ==> 0XF8000784[13:13] = 0x00000000U */
11529 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11530 /* .. */
11531 EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00000304U),
11532 /* .. TRI_ENABLE = 0 */
11533 /* .. ==> 0XF8000788[0:0] = 0x00000000U */
11534 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11535 /* .. L0_SEL = 0 */
11536 /* .. ==> 0XF8000788[1:1] = 0x00000000U */
11537 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11538 /* .. L1_SEL = 1 */
11539 /* .. ==> 0XF8000788[2:2] = 0x00000001U */
11540 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11541 /* .. L2_SEL = 0 */
11542 /* .. ==> 0XF8000788[4:3] = 0x00000000U */
11543 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11544 /* .. L3_SEL = 0 */
11545 /* .. ==> 0XF8000788[7:5] = 0x00000000U */
11546 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11547 /* .. Speed = 1 */
11548 /* .. ==> 0XF8000788[8:8] = 0x00000001U */
11549 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11550 /* .. IO_Type = 1 */
11551 /* .. ==> 0XF8000788[11:9] = 0x00000001U */
11552 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11553 /* .. PULLUP = 0 */
11554 /* .. ==> 0XF8000788[12:12] = 0x00000000U */
11555 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11556 /* .. DisableRcvr = 0 */
11557 /* .. ==> 0XF8000788[13:13] = 0x00000000U */
11558 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11559 /* .. */
11560 EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00000304U),
11561 /* .. TRI_ENABLE = 0 */
11562 /* .. ==> 0XF800078C[0:0] = 0x00000000U */
11563 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11564 /* .. L0_SEL = 0 */
11565 /* .. ==> 0XF800078C[1:1] = 0x00000000U */
11566 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11567 /* .. L1_SEL = 1 */
11568 /* .. ==> 0XF800078C[2:2] = 0x00000001U */
11569 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11570 /* .. L2_SEL = 0 */
11571 /* .. ==> 0XF800078C[4:3] = 0x00000000U */
11572 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11573 /* .. L3_SEL = 0 */
11574 /* .. ==> 0XF800078C[7:5] = 0x00000000U */
11575 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11576 /* .. Speed = 1 */
11577 /* .. ==> 0XF800078C[8:8] = 0x00000001U */
11578 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11579 /* .. IO_Type = 1 */
11580 /* .. ==> 0XF800078C[11:9] = 0x00000001U */
11581 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11582 /* .. PULLUP = 0 */
11583 /* .. ==> 0XF800078C[12:12] = 0x00000000U */
11584 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11585 /* .. DisableRcvr = 0 */
11586 /* .. ==> 0XF800078C[13:13] = 0x00000000U */
11587 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11588 /* .. */
11589 EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00000304U),
11590 /* .. TRI_ENABLE = 1 */
11591 /* .. ==> 0XF8000790[0:0] = 0x00000001U */
11592 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11593 /* .. L0_SEL = 0 */
11594 /* .. ==> 0XF8000790[1:1] = 0x00000000U */
11595 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11596 /* .. L1_SEL = 1 */
11597 /* .. ==> 0XF8000790[2:2] = 0x00000001U */
11598 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11599 /* .. L2_SEL = 0 */
11600 /* .. ==> 0XF8000790[4:3] = 0x00000000U */
11601 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11602 /* .. L3_SEL = 0 */
11603 /* .. ==> 0XF8000790[7:5] = 0x00000000U */
11604 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11605 /* .. Speed = 1 */
11606 /* .. ==> 0XF8000790[8:8] = 0x00000001U */
11607 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11608 /* .. IO_Type = 1 */
11609 /* .. ==> 0XF8000790[11:9] = 0x00000001U */
11610 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11611 /* .. PULLUP = 0 */
11612 /* .. ==> 0XF8000790[12:12] = 0x00000000U */
11613 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11614 /* .. DisableRcvr = 0 */
11615 /* .. ==> 0XF8000790[13:13] = 0x00000000U */
11616 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11617 /* .. */
11618 EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00000305U),
11619 /* .. TRI_ENABLE = 0 */
11620 /* .. ==> 0XF8000794[0:0] = 0x00000000U */
11621 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11622 /* .. L0_SEL = 0 */
11623 /* .. ==> 0XF8000794[1:1] = 0x00000000U */
11624 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11625 /* .. L1_SEL = 1 */
11626 /* .. ==> 0XF8000794[2:2] = 0x00000001U */
11627 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11628 /* .. L2_SEL = 0 */
11629 /* .. ==> 0XF8000794[4:3] = 0x00000000U */
11630 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11631 /* .. L3_SEL = 0 */
11632 /* .. ==> 0XF8000794[7:5] = 0x00000000U */
11633 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11634 /* .. Speed = 1 */
11635 /* .. ==> 0XF8000794[8:8] = 0x00000001U */
11636 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11637 /* .. IO_Type = 1 */
11638 /* .. ==> 0XF8000794[11:9] = 0x00000001U */
11639 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11640 /* .. PULLUP = 0 */
11641 /* .. ==> 0XF8000794[12:12] = 0x00000000U */
11642 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11643 /* .. DisableRcvr = 0 */
11644 /* .. ==> 0XF8000794[13:13] = 0x00000000U */
11645 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11646 /* .. */
11647 EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00000304U),
11648 /* .. TRI_ENABLE = 0 */
11649 /* .. ==> 0XF8000798[0:0] = 0x00000000U */
11650 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11651 /* .. L0_SEL = 0 */
11652 /* .. ==> 0XF8000798[1:1] = 0x00000000U */
11653 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11654 /* .. L1_SEL = 1 */
11655 /* .. ==> 0XF8000798[2:2] = 0x00000001U */
11656 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11657 /* .. L2_SEL = 0 */
11658 /* .. ==> 0XF8000798[4:3] = 0x00000000U */
11659 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11660 /* .. L3_SEL = 0 */
11661 /* .. ==> 0XF8000798[7:5] = 0x00000000U */
11662 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11663 /* .. Speed = 1 */
11664 /* .. ==> 0XF8000798[8:8] = 0x00000001U */
11665 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11666 /* .. IO_Type = 1 */
11667 /* .. ==> 0XF8000798[11:9] = 0x00000001U */
11668 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11669 /* .. PULLUP = 0 */
11670 /* .. ==> 0XF8000798[12:12] = 0x00000000U */
11671 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11672 /* .. DisableRcvr = 0 */
11673 /* .. ==> 0XF8000798[13:13] = 0x00000000U */
11674 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11675 /* .. */
11676 EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00000304U),
11677 /* .. TRI_ENABLE = 0 */
11678 /* .. ==> 0XF800079C[0:0] = 0x00000000U */
11679 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11680 /* .. L0_SEL = 0 */
11681 /* .. ==> 0XF800079C[1:1] = 0x00000000U */
11682 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11683 /* .. L1_SEL = 1 */
11684 /* .. ==> 0XF800079C[2:2] = 0x00000001U */
11685 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
11686 /* .. L2_SEL = 0 */
11687 /* .. ==> 0XF800079C[4:3] = 0x00000000U */
11688 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11689 /* .. L3_SEL = 0 */
11690 /* .. ==> 0XF800079C[7:5] = 0x00000000U */
11691 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11692 /* .. Speed = 1 */
11693 /* .. ==> 0XF800079C[8:8] = 0x00000001U */
11694 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11695 /* .. IO_Type = 1 */
11696 /* .. ==> 0XF800079C[11:9] = 0x00000001U */
11697 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11698 /* .. PULLUP = 0 */
11699 /* .. ==> 0XF800079C[12:12] = 0x00000000U */
11700 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11701 /* .. DisableRcvr = 0 */
11702 /* .. ==> 0XF800079C[13:13] = 0x00000000U */
11703 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11704 /* .. */
11705 EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00000304U),
11706 /* .. TRI_ENABLE = 0 */
11707 /* .. ==> 0XF80007A0[0:0] = 0x00000000U */
11708 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11709 /* .. L0_SEL = 0 */
11710 /* .. ==> 0XF80007A0[1:1] = 0x00000000U */
11711 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11712 /* .. L1_SEL = 0 */
11713 /* .. ==> 0XF80007A0[2:2] = 0x00000000U */
11714 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11715 /* .. L2_SEL = 0 */
11716 /* .. ==> 0XF80007A0[4:3] = 0x00000000U */
11717 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11718 /* .. L3_SEL = 4 */
11719 /* .. ==> 0XF80007A0[7:5] = 0x00000004U */
11720 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11721 /* .. Speed = 1 */
11722 /* .. ==> 0XF80007A0[8:8] = 0x00000001U */
11723 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11724 /* .. IO_Type = 1 */
11725 /* .. ==> 0XF80007A0[11:9] = 0x00000001U */
11726 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11727 /* .. PULLUP = 0 */
11728 /* .. ==> 0XF80007A0[12:12] = 0x00000000U */
11729 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11730 /* .. DisableRcvr = 0 */
11731 /* .. ==> 0XF80007A0[13:13] = 0x00000000U */
11732 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11733 /* .. */
11734 EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00000380U),
11735 /* .. TRI_ENABLE = 0 */
11736 /* .. ==> 0XF80007A4[0:0] = 0x00000000U */
11737 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11738 /* .. L0_SEL = 0 */
11739 /* .. ==> 0XF80007A4[1:1] = 0x00000000U */
11740 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11741 /* .. L1_SEL = 0 */
11742 /* .. ==> 0XF80007A4[2:2] = 0x00000000U */
11743 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11744 /* .. L2_SEL = 0 */
11745 /* .. ==> 0XF80007A4[4:3] = 0x00000000U */
11746 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11747 /* .. L3_SEL = 4 */
11748 /* .. ==> 0XF80007A4[7:5] = 0x00000004U */
11749 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11750 /* .. Speed = 1 */
11751 /* .. ==> 0XF80007A4[8:8] = 0x00000001U */
11752 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11753 /* .. IO_Type = 1 */
11754 /* .. ==> 0XF80007A4[11:9] = 0x00000001U */
11755 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11756 /* .. PULLUP = 0 */
11757 /* .. ==> 0XF80007A4[12:12] = 0x00000000U */
11758 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11759 /* .. DisableRcvr = 0 */
11760 /* .. ==> 0XF80007A4[13:13] = 0x00000000U */
11761 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11762 /* .. */
11763 EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00000380U),
11764 /* .. TRI_ENABLE = 0 */
11765 /* .. ==> 0XF80007A8[0:0] = 0x00000000U */
11766 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11767 /* .. L0_SEL = 0 */
11768 /* .. ==> 0XF80007A8[1:1] = 0x00000000U */
11769 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11770 /* .. L1_SEL = 0 */
11771 /* .. ==> 0XF80007A8[2:2] = 0x00000000U */
11772 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11773 /* .. L2_SEL = 0 */
11774 /* .. ==> 0XF80007A8[4:3] = 0x00000000U */
11775 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11776 /* .. L3_SEL = 4 */
11777 /* .. ==> 0XF80007A8[7:5] = 0x00000004U */
11778 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11779 /* .. Speed = 1 */
11780 /* .. ==> 0XF80007A8[8:8] = 0x00000001U */
11781 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11782 /* .. IO_Type = 1 */
11783 /* .. ==> 0XF80007A8[11:9] = 0x00000001U */
11784 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11785 /* .. PULLUP = 0 */
11786 /* .. ==> 0XF80007A8[12:12] = 0x00000000U */
11787 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11788 /* .. DisableRcvr = 0 */
11789 /* .. ==> 0XF80007A8[13:13] = 0x00000000U */
11790 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11791 /* .. */
11792 EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00000380U),
11793 /* .. TRI_ENABLE = 0 */
11794 /* .. ==> 0XF80007AC[0:0] = 0x00000000U */
11795 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11796 /* .. L0_SEL = 0 */
11797 /* .. ==> 0XF80007AC[1:1] = 0x00000000U */
11798 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11799 /* .. L1_SEL = 0 */
11800 /* .. ==> 0XF80007AC[2:2] = 0x00000000U */
11801 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11802 /* .. L2_SEL = 0 */
11803 /* .. ==> 0XF80007AC[4:3] = 0x00000000U */
11804 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11805 /* .. L3_SEL = 4 */
11806 /* .. ==> 0XF80007AC[7:5] = 0x00000004U */
11807 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11808 /* .. Speed = 1 */
11809 /* .. ==> 0XF80007AC[8:8] = 0x00000001U */
11810 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11811 /* .. IO_Type = 1 */
11812 /* .. ==> 0XF80007AC[11:9] = 0x00000001U */
11813 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11814 /* .. PULLUP = 0 */
11815 /* .. ==> 0XF80007AC[12:12] = 0x00000000U */
11816 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11817 /* .. DisableRcvr = 0 */
11818 /* .. ==> 0XF80007AC[13:13] = 0x00000000U */
11819 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11820 /* .. */
11821 EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00000380U),
11822 /* .. TRI_ENABLE = 0 */
11823 /* .. ==> 0XF80007B0[0:0] = 0x00000000U */
11824 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11825 /* .. L0_SEL = 0 */
11826 /* .. ==> 0XF80007B0[1:1] = 0x00000000U */
11827 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11828 /* .. L1_SEL = 0 */
11829 /* .. ==> 0XF80007B0[2:2] = 0x00000000U */
11830 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11831 /* .. L2_SEL = 0 */
11832 /* .. ==> 0XF80007B0[4:3] = 0x00000000U */
11833 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11834 /* .. L3_SEL = 4 */
11835 /* .. ==> 0XF80007B0[7:5] = 0x00000004U */
11836 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11837 /* .. Speed = 1 */
11838 /* .. ==> 0XF80007B0[8:8] = 0x00000001U */
11839 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11840 /* .. IO_Type = 1 */
11841 /* .. ==> 0XF80007B0[11:9] = 0x00000001U */
11842 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11843 /* .. PULLUP = 0 */
11844 /* .. ==> 0XF80007B0[12:12] = 0x00000000U */
11845 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11846 /* .. DisableRcvr = 0 */
11847 /* .. ==> 0XF80007B0[13:13] = 0x00000000U */
11848 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11849 /* .. */
11850 EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00000380U),
11851 /* .. TRI_ENABLE = 0 */
11852 /* .. ==> 0XF80007B4[0:0] = 0x00000000U */
11853 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11854 /* .. L0_SEL = 0 */
11855 /* .. ==> 0XF80007B4[1:1] = 0x00000000U */
11856 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11857 /* .. L1_SEL = 0 */
11858 /* .. ==> 0XF80007B4[2:2] = 0x00000000U */
11859 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11860 /* .. L2_SEL = 0 */
11861 /* .. ==> 0XF80007B4[4:3] = 0x00000000U */
11862 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11863 /* .. L3_SEL = 4 */
11864 /* .. ==> 0XF80007B4[7:5] = 0x00000004U */
11865 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
11866 /* .. Speed = 1 */
11867 /* .. ==> 0XF80007B4[8:8] = 0x00000001U */
11868 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
11869 /* .. IO_Type = 1 */
11870 /* .. ==> 0XF80007B4[11:9] = 0x00000001U */
11871 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11872 /* .. PULLUP = 0 */
11873 /* .. ==> 0XF80007B4[12:12] = 0x00000000U */
11874 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11875 /* .. DisableRcvr = 0 */
11876 /* .. ==> 0XF80007B4[13:13] = 0x00000000U */
11877 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11878 /* .. */
11879 EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00000380U),
11880 /* .. TRI_ENABLE = 0 */
11881 /* .. ==> 0XF80007B8[0:0] = 0x00000000U */
11882 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11883 /* .. L0_SEL = 0 */
11884 /* .. ==> 0XF80007B8[1:1] = 0x00000000U */
11885 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11886 /* .. L1_SEL = 0 */
11887 /* .. ==> 0XF80007B8[2:2] = 0x00000000U */
11888 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11889 /* .. L2_SEL = 0 */
11890 /* .. ==> 0XF80007B8[4:3] = 0x00000000U */
11891 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11892 /* .. L3_SEL = 0 */
11893 /* .. ==> 0XF80007B8[7:5] = 0x00000000U */
11894 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11895 /* .. Speed = 0 */
11896 /* .. ==> 0XF80007B8[8:8] = 0x00000000U */
11897 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
11898 /* .. IO_Type = 1 */
11899 /* .. ==> 0XF80007B8[11:9] = 0x00000001U */
11900 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11901 /* .. PULLUP = 1 */
11902 /* .. ==> 0XF80007B8[12:12] = 0x00000001U */
11903 /* .. ==> MASK : 0x00001000U VAL : 0x00001000U */
11904 /* .. DisableRcvr = 0 */
11905 /* .. ==> 0XF80007B8[13:13] = 0x00000000U */
11906 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11907 /* .. */
11908 EMIT_MASKWRITE(0XF80007B8, 0x00003FFFU, 0x00001200U),
11909 /* .. TRI_ENABLE = 1 */
11910 /* .. ==> 0XF80007BC[0:0] = 0x00000001U */
11911 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11912 /* .. Speed = 0 */
11913 /* .. ==> 0XF80007BC[8:8] = 0x00000000U */
11914 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
11915 /* .. IO_Type = 1 */
11916 /* .. ==> 0XF80007BC[11:9] = 0x00000001U */
11917 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11918 /* .. PULLUP = 0 */
11919 /* .. ==> 0XF80007BC[12:12] = 0x00000000U */
11920 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11921 /* .. DisableRcvr = 0 */
11922 /* .. ==> 0XF80007BC[13:13] = 0x00000000U */
11923 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11924 /* .. */
11925 EMIT_MASKWRITE(0XF80007BC, 0x00003F01U, 0x00000201U),
11926 /* .. TRI_ENABLE = 0 */
11927 /* .. ==> 0XF80007C0[0:0] = 0x00000000U */
11928 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11929 /* .. L0_SEL = 0 */
11930 /* .. ==> 0XF80007C0[1:1] = 0x00000000U */
11931 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11932 /* .. L1_SEL = 0 */
11933 /* .. ==> 0XF80007C0[2:2] = 0x00000000U */
11934 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11935 /* .. L2_SEL = 0 */
11936 /* .. ==> 0XF80007C0[4:3] = 0x00000000U */
11937 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11938 /* .. L3_SEL = 7 */
11939 /* .. ==> 0XF80007C0[7:5] = 0x00000007U */
11940 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
11941 /* .. Speed = 0 */
11942 /* .. ==> 0XF80007C0[8:8] = 0x00000000U */
11943 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
11944 /* .. IO_Type = 1 */
11945 /* .. ==> 0XF80007C0[11:9] = 0x00000001U */
11946 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11947 /* .. PULLUP = 0 */
11948 /* .. ==> 0XF80007C0[12:12] = 0x00000000U */
11949 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11950 /* .. DisableRcvr = 0 */
11951 /* .. ==> 0XF80007C0[13:13] = 0x00000000U */
11952 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11953 /* .. */
11954 EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x000002E0U),
11955 /* .. TRI_ENABLE = 1 */
11956 /* .. ==> 0XF80007C4[0:0] = 0x00000001U */
11957 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
11958 /* .. L0_SEL = 0 */
11959 /* .. ==> 0XF80007C4[1:1] = 0x00000000U */
11960 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11961 /* .. L1_SEL = 0 */
11962 /* .. ==> 0XF80007C4[2:2] = 0x00000000U */
11963 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11964 /* .. L2_SEL = 0 */
11965 /* .. ==> 0XF80007C4[4:3] = 0x00000000U */
11966 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11967 /* .. L3_SEL = 7 */
11968 /* .. ==> 0XF80007C4[7:5] = 0x00000007U */
11969 /* .. ==> MASK : 0x000000E0U VAL : 0x000000E0U */
11970 /* .. Speed = 0 */
11971 /* .. ==> 0XF80007C4[8:8] = 0x00000000U */
11972 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
11973 /* .. IO_Type = 1 */
11974 /* .. ==> 0XF80007C4[11:9] = 0x00000001U */
11975 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
11976 /* .. PULLUP = 0 */
11977 /* .. ==> 0XF80007C4[12:12] = 0x00000000U */
11978 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
11979 /* .. DisableRcvr = 0 */
11980 /* .. ==> 0XF80007C4[13:13] = 0x00000000U */
11981 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
11982 /* .. */
11983 EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x000002E1U),
11984 /* .. TRI_ENABLE = 0 */
11985 /* .. ==> 0XF80007C8[0:0] = 0x00000000U */
11986 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
11987 /* .. L0_SEL = 0 */
11988 /* .. ==> 0XF80007C8[1:1] = 0x00000000U */
11989 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
11990 /* .. L1_SEL = 0 */
11991 /* .. ==> 0XF80007C8[2:2] = 0x00000000U */
11992 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
11993 /* .. L2_SEL = 0 */
11994 /* .. ==> 0XF80007C8[4:3] = 0x00000000U */
11995 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
11996 /* .. L3_SEL = 0 */
11997 /* .. ==> 0XF80007C8[7:5] = 0x00000000U */
11998 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
11999 /* .. Speed = 0 */
12000 /* .. ==> 0XF80007C8[8:8] = 0x00000000U */
12001 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12002 /* .. IO_Type = 1 */
12003 /* .. ==> 0XF80007C8[11:9] = 0x00000001U */
12004 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
12005 /* .. PULLUP = 0 */
12006 /* .. ==> 0XF80007C8[12:12] = 0x00000000U */
12007 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
12008 /* .. DisableRcvr = 0 */
12009 /* .. ==> 0XF80007C8[13:13] = 0x00000000U */
12010 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
12011 /* .. */
12012 EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00000200U),
12013 /* .. TRI_ENABLE = 0 */
12014 /* .. ==> 0XF80007CC[0:0] = 0x00000000U */
12015 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
12016 /* .. L0_SEL = 0 */
12017 /* .. ==> 0XF80007CC[1:1] = 0x00000000U */
12018 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
12019 /* .. L1_SEL = 0 */
12020 /* .. ==> 0XF80007CC[2:2] = 0x00000000U */
12021 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
12022 /* .. L2_SEL = 0 */
12023 /* .. ==> 0XF80007CC[4:3] = 0x00000000U */
12024 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
12025 /* .. L3_SEL = 0 */
12026 /* .. ==> 0XF80007CC[7:5] = 0x00000000U */
12027 /* .. ==> MASK : 0x000000E0U VAL : 0x00000000U */
12028 /* .. Speed = 0 */
12029 /* .. ==> 0XF80007CC[8:8] = 0x00000000U */
12030 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12031 /* .. IO_Type = 1 */
12032 /* .. ==> 0XF80007CC[11:9] = 0x00000001U */
12033 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
12034 /* .. PULLUP = 0 */
12035 /* .. ==> 0XF80007CC[12:12] = 0x00000000U */
12036 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
12037 /* .. DisableRcvr = 0 */
12038 /* .. ==> 0XF80007CC[13:13] = 0x00000000U */
12039 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
12040 /* .. */
12041 EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00000200U),
12042 /* .. TRI_ENABLE = 0 */
12043 /* .. ==> 0XF80007D0[0:0] = 0x00000000U */
12044 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
12045 /* .. L0_SEL = 0 */
12046 /* .. ==> 0XF80007D0[1:1] = 0x00000000U */
12047 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
12048 /* .. L1_SEL = 0 */
12049 /* .. ==> 0XF80007D0[2:2] = 0x00000000U */
12050 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
12051 /* .. L2_SEL = 0 */
12052 /* .. ==> 0XF80007D0[4:3] = 0x00000000U */
12053 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
12054 /* .. L3_SEL = 4 */
12055 /* .. ==> 0XF80007D0[7:5] = 0x00000004U */
12056 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
12057 /* .. Speed = 0 */
12058 /* .. ==> 0XF80007D0[8:8] = 0x00000000U */
12059 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12060 /* .. IO_Type = 1 */
12061 /* .. ==> 0XF80007D0[11:9] = 0x00000001U */
12062 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
12063 /* .. PULLUP = 0 */
12064 /* .. ==> 0XF80007D0[12:12] = 0x00000000U */
12065 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
12066 /* .. DisableRcvr = 0 */
12067 /* .. ==> 0XF80007D0[13:13] = 0x00000000U */
12068 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
12069 /* .. */
12070 EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00000280U),
12071 /* .. TRI_ENABLE = 0 */
12072 /* .. ==> 0XF80007D4[0:0] = 0x00000000U */
12073 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
12074 /* .. L0_SEL = 0 */
12075 /* .. ==> 0XF80007D4[1:1] = 0x00000000U */
12076 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
12077 /* .. L1_SEL = 0 */
12078 /* .. ==> 0XF80007D4[2:2] = 0x00000000U */
12079 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
12080 /* .. L2_SEL = 0 */
12081 /* .. ==> 0XF80007D4[4:3] = 0x00000000U */
12082 /* .. ==> MASK : 0x00000018U VAL : 0x00000000U */
12083 /* .. L3_SEL = 4 */
12084 /* .. ==> 0XF80007D4[7:5] = 0x00000004U */
12085 /* .. ==> MASK : 0x000000E0U VAL : 0x00000080U */
12086 /* .. Speed = 0 */
12087 /* .. ==> 0XF80007D4[8:8] = 0x00000000U */
12088 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12089 /* .. IO_Type = 1 */
12090 /* .. ==> 0XF80007D4[11:9] = 0x00000001U */
12091 /* .. ==> MASK : 0x00000E00U VAL : 0x00000200U */
12092 /* .. PULLUP = 0 */
12093 /* .. ==> 0XF80007D4[12:12] = 0x00000000U */
12094 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
12095 /* .. DisableRcvr = 0 */
12096 /* .. ==> 0XF80007D4[13:13] = 0x00000000U */
12097 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
12098 /* .. */
12099 EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00000280U),
12100 /* .. SDIO0_WP_SEL = 55 */
12101 /* .. ==> 0XF8000830[5:0] = 0x00000037U */
12102 /* .. ==> MASK : 0x0000003FU VAL : 0x00000037U */
12103 /* .. SDIO0_CD_SEL = 47 */
12104 /* .. ==> 0XF8000830[21:16] = 0x0000002FU */
12105 /* .. ==> MASK : 0x003F0000U VAL : 0x002F0000U */
12106 /* .. */
12107 EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002F0037U),
12108 /* .. FINISH: MIO PROGRAMMING */
12109 /* .. START: LOCK IT BACK */
12110 /* .. LOCK_KEY = 0X767B */
12111 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
12112 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
12113 /* .. */
12114 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
12115 /* .. FINISH: LOCK IT BACK */
12116 /* FINISH: top */
12117 /* */
12118 EMIT_EXIT(),
12119
12120 /* */
12121 };
12122
12123 unsigned long ps7_peripherals_init_data_1_0[] = {
12124 /* START: top */
12125 /* .. START: SLCR SETTINGS */
12126 /* .. UNLOCK_KEY = 0XDF0D */
12127 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
12128 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
12129 /* .. */
12130 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
12131 /* .. FINISH: SLCR SETTINGS */
12132 /* .. START: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
12133 /* .. IBUF_DISABLE_MODE = 0x1 */
12134 /* .. ==> 0XF8000B48[7:7] = 0x00000001U */
12135 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
12136 /* .. TERM_DISABLE_MODE = 0x1 */
12137 /* .. ==> 0XF8000B48[8:8] = 0x00000001U */
12138 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
12139 /* .. */
12140 EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
12141 /* .. IBUF_DISABLE_MODE = 0x1 */
12142 /* .. ==> 0XF8000B4C[7:7] = 0x00000001U */
12143 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
12144 /* .. TERM_DISABLE_MODE = 0x1 */
12145 /* .. ==> 0XF8000B4C[8:8] = 0x00000001U */
12146 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
12147 /* .. */
12148 EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
12149 /* .. IBUF_DISABLE_MODE = 0x1 */
12150 /* .. ==> 0XF8000B50[7:7] = 0x00000001U */
12151 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
12152 /* .. TERM_DISABLE_MODE = 0x1 */
12153 /* .. ==> 0XF8000B50[8:8] = 0x00000001U */
12154 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
12155 /* .. */
12156 EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
12157 /* .. IBUF_DISABLE_MODE = 0x1 */
12158 /* .. ==> 0XF8000B54[7:7] = 0x00000001U */
12159 /* .. ==> MASK : 0x00000080U VAL : 0x00000080U */
12160 /* .. TERM_DISABLE_MODE = 0x1 */
12161 /* .. ==> 0XF8000B54[8:8] = 0x00000001U */
12162 /* .. ==> MASK : 0x00000100U VAL : 0x00000100U */
12163 /* .. */
12164 EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
12165 /* .. FINISH: DDR TERM/IBUF_DISABLE_MODE SETTINGS */
12166 /* .. START: LOCK IT BACK */
12167 /* .. LOCK_KEY = 0X767B */
12168 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
12169 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
12170 /* .. */
12171 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
12172 /* .. FINISH: LOCK IT BACK */
12173 /* .. START: SRAM/NOR SET OPMODE */
12174 /* .. FINISH: SRAM/NOR SET OPMODE */
12175 /* .. START: UART REGISTERS */
12176 /* .. BDIV = 0x6 */
12177 /* .. ==> 0XE0001034[7:0] = 0x00000006U */
12178 /* .. ==> MASK : 0x000000FFU VAL : 0x00000006U */
12179 /* .. */
12180 EMIT_MASKWRITE(0XE0001034, 0x000000FFU, 0x00000006U),
12181 /* .. CD = 0x7c */
12182 /* .. ==> 0XE0001018[15:0] = 0x0000007CU */
12183 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000007CU */
12184 /* .. */
12185 EMIT_MASKWRITE(0XE0001018, 0x0000FFFFU, 0x0000007CU),
12186 /* .. STPBRK = 0x0 */
12187 /* .. ==> 0XE0001000[8:8] = 0x00000000U */
12188 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12189 /* .. STTBRK = 0x0 */
12190 /* .. ==> 0XE0001000[7:7] = 0x00000000U */
12191 /* .. ==> MASK : 0x00000080U VAL : 0x00000000U */
12192 /* .. RSTTO = 0x0 */
12193 /* .. ==> 0XE0001000[6:6] = 0x00000000U */
12194 /* .. ==> MASK : 0x00000040U VAL : 0x00000000U */
12195 /* .. TXDIS = 0x0 */
12196 /* .. ==> 0XE0001000[5:5] = 0x00000000U */
12197 /* .. ==> MASK : 0x00000020U VAL : 0x00000000U */
12198 /* .. TXEN = 0x1 */
12199 /* .. ==> 0XE0001000[4:4] = 0x00000001U */
12200 /* .. ==> MASK : 0x00000010U VAL : 0x00000010U */
12201 /* .. RXDIS = 0x0 */
12202 /* .. ==> 0XE0001000[3:3] = 0x00000000U */
12203 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
12204 /* .. RXEN = 0x1 */
12205 /* .. ==> 0XE0001000[2:2] = 0x00000001U */
12206 /* .. ==> MASK : 0x00000004U VAL : 0x00000004U */
12207 /* .. TXRES = 0x1 */
12208 /* .. ==> 0XE0001000[1:1] = 0x00000001U */
12209 /* .. ==> MASK : 0x00000002U VAL : 0x00000002U */
12210 /* .. RXRES = 0x1 */
12211 /* .. ==> 0XE0001000[0:0] = 0x00000001U */
12212 /* .. ==> MASK : 0x00000001U VAL : 0x00000001U */
12213 /* .. */
12214 EMIT_MASKWRITE(0XE0001000, 0x000001FFU, 0x00000017U),
12215 /* .. IRMODE = 0x0 */
12216 /* .. ==> 0XE0001004[11:11] = 0x00000000U */
12217 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
12218 /* .. UCLKEN = 0x0 */
12219 /* .. ==> 0XE0001004[10:10] = 0x00000000U */
12220 /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
12221 /* .. CHMODE = 0x0 */
12222 /* .. ==> 0XE0001004[9:8] = 0x00000000U */
12223 /* .. ==> MASK : 0x00000300U VAL : 0x00000000U */
12224 /* .. NBSTOP = 0x0 */
12225 /* .. ==> 0XE0001004[7:6] = 0x00000000U */
12226 /* .. ==> MASK : 0x000000C0U VAL : 0x00000000U */
12227 /* .. PAR = 0x4 */
12228 /* .. ==> 0XE0001004[5:3] = 0x00000004U */
12229 /* .. ==> MASK : 0x00000038U VAL : 0x00000020U */
12230 /* .. CHRL = 0x0 */
12231 /* .. ==> 0XE0001004[2:1] = 0x00000000U */
12232 /* .. ==> MASK : 0x00000006U VAL : 0x00000000U */
12233 /* .. CLKS = 0x0 */
12234 /* .. ==> 0XE0001004[0:0] = 0x00000000U */
12235 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
12236 /* .. */
12237 EMIT_MASKWRITE(0XE0001004, 0x00000FFFU, 0x00000020U),
12238 /* .. FINISH: UART REGISTERS */
12239 /* .. START: QSPI REGISTERS */
12240 /* .. Holdb_dr = 1 */
12241 /* .. ==> 0XE000D000[19:19] = 0x00000001U */
12242 /* .. ==> MASK : 0x00080000U VAL : 0x00080000U */
12243 /* .. */
12244 EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
12245 /* .. FINISH: QSPI REGISTERS */
12246 /* .. START: PL POWER ON RESET REGISTERS */
12247 /* .. PCFG_POR_CNT_4K = 0 */
12248 /* .. ==> 0XF8007000[29:29] = 0x00000000U */
12249 /* .. ==> MASK : 0x20000000U VAL : 0x00000000U */
12250 /* .. */
12251 EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
12252 /* .. FINISH: PL POWER ON RESET REGISTERS */
12253 /* .. START: SMC TIMING CALCULATION REGISTER UPDATE */
12254 /* .. .. START: NAND SET CYCLE */
12255 /* .. .. FINISH: NAND SET CYCLE */
12256 /* .. .. START: OPMODE */
12257 /* .. .. FINISH: OPMODE */
12258 /* .. .. START: DIRECT COMMAND */
12259 /* .. .. FINISH: DIRECT COMMAND */
12260 /* .. .. START: SRAM/NOR CS0 SET CYCLE */
12261 /* .. .. FINISH: SRAM/NOR CS0 SET CYCLE */
12262 /* .. .. START: DIRECT COMMAND */
12263 /* .. .. FINISH: DIRECT COMMAND */
12264 /* .. .. START: NOR CS0 BASE ADDRESS */
12265 /* .. .. FINISH: NOR CS0 BASE ADDRESS */
12266 /* .. .. START: SRAM/NOR CS1 SET CYCLE */
12267 /* .. .. FINISH: SRAM/NOR CS1 SET CYCLE */
12268 /* .. .. START: DIRECT COMMAND */
12269 /* .. .. FINISH: DIRECT COMMAND */
12270 /* .. .. START: NOR CS1 BASE ADDRESS */
12271 /* .. .. FINISH: NOR CS1 BASE ADDRESS */
12272 /* .. .. START: USB RESET */
12273 /* .. .. .. START: USB0 RESET */
12274 /* .. .. .. .. START: DIR MODE BANK 0 */
12275 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
12276 /* .. .. .. .. START: DIR MODE BANK 1 */
12277 /* .. .. .. .. DIRECTION_1 = 0x4000 */
12278 /* .. .. .. .. ==> 0XE000A244[21:0] = 0x00004000U */
12279 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
12280 /* .. .. .. .. */
12281 EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00004000U),
12282 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
12283 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12284 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12285 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12286 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12287 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12288 /* .. .. .. .. MASK_1_LSW = 0xbfff */
12289 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
12290 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
12291 /* .. .. .. .. DATA_1_LSW = 0x4000 */
12292 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
12293 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
12294 /* .. .. .. .. */
12295 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
12296 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12297 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12298 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12299 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
12300 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
12301 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
12302 /* .. .. .. .. OP_ENABLE_1 = 0x4000 */
12303 /* .. .. .. .. ==> 0XE000A248[21:0] = 0x00004000U */
12304 /* .. .. .. .. ==> MASK : 0x003FFFFFU VAL : 0x00004000U */
12305 /* .. .. .. .. */
12306 EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00004000U),
12307 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
12308 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12309 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12310 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12311 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12312 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
12313 /* .. .. .. .. MASK_1_LSW = 0xbfff */
12314 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
12315 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
12316 /* .. .. .. .. DATA_1_LSW = 0x0 */
12317 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00000000U */
12318 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00000000U */
12319 /* .. .. .. .. */
12320 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF0000U),
12321 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12322 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12323 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12324 /* .. .. .. .. START: ADD 1 MS DELAY */
12325 /* .. .. .. .. */
12326 EMIT_MASKDELAY(0XF8F00200, 1),
12327 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12328 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12329 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12330 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12331 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12332 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12333 /* .. .. .. .. MASK_1_LSW = 0xbfff */
12334 /* .. .. .. .. ==> 0XE000A008[31:16] = 0x0000BFFFU */
12335 /* .. .. .. .. ==> MASK : 0xFFFF0000U VAL : 0xBFFF0000U */
12336 /* .. .. .. .. DATA_1_LSW = 0x4000 */
12337 /* .. .. .. .. ==> 0XE000A008[15:0] = 0x00004000U */
12338 /* .. .. .. .. ==> MASK : 0x0000FFFFU VAL : 0x00004000U */
12339 /* .. .. .. .. */
12340 EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0xBFFF4000U),
12341 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12342 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12343 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12344 /* .. .. .. FINISH: USB0 RESET */
12345 /* .. .. .. START: USB1 RESET */
12346 /* .. .. .. .. START: DIR MODE BANK 0 */
12347 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
12348 /* .. .. .. .. START: DIR MODE BANK 1 */
12349 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
12350 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12351 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12352 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12353 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12354 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12355 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12356 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12357 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12358 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
12359 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
12360 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
12361 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
12362 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12363 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12364 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12365 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12366 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
12367 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12368 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12369 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12370 /* .. .. .. .. START: ADD 1 MS DELAY */
12371 /* .. .. .. .. */
12372 EMIT_MASKDELAY(0XF8F00200, 1),
12373 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12374 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12375 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12376 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12377 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12378 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12379 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12380 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12381 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12382 /* .. .. .. FINISH: USB1 RESET */
12383 /* .. .. FINISH: USB RESET */
12384 /* .. .. START: ENET RESET */
12385 /* .. .. .. START: ENET0 RESET */
12386 /* .. .. .. .. START: DIR MODE BANK 0 */
12387 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
12388 /* .. .. .. .. START: DIR MODE BANK 1 */
12389 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
12390 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12391 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12392 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12393 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12394 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12395 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12396 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12397 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12398 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
12399 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
12400 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
12401 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
12402 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12403 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12404 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12405 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12406 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
12407 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12408 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12409 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12410 /* .. .. .. .. START: ADD 1 MS DELAY */
12411 /* .. .. .. .. */
12412 EMIT_MASKDELAY(0XF8F00200, 1),
12413 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12414 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12415 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12416 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12417 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12418 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12419 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12420 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12421 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12422 /* .. .. .. FINISH: ENET0 RESET */
12423 /* .. .. .. START: ENET1 RESET */
12424 /* .. .. .. .. START: DIR MODE BANK 0 */
12425 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
12426 /* .. .. .. .. START: DIR MODE BANK 1 */
12427 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
12428 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12429 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12430 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12431 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12432 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12433 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12434 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12435 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12436 /* .. .. .. .. START: OUTPUT ENABLE BANK 0 */
12437 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
12438 /* .. .. .. .. START: OUTPUT ENABLE BANK 1 */
12439 /* .. .. .. .. FINISH: OUTPUT ENABLE BANK 1 */
12440 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12441 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12442 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12443 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12444 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
12445 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12446 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12447 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12448 /* .. .. .. .. START: ADD 1 MS DELAY */
12449 /* .. .. .. .. */
12450 EMIT_MASKDELAY(0XF8F00200, 1),
12451 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12452 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12453 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12454 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12455 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12456 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12457 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12458 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12459 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12460 /* .. .. .. FINISH: ENET1 RESET */
12461 /* .. .. FINISH: ENET RESET */
12462 /* .. .. START: I2C RESET */
12463 /* .. .. .. START: I2C0 RESET */
12464 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
12465 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
12466 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
12467 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
12468 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12469 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12470 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12471 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12472 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12473 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12474 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12475 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12476 /* .. .. .. .. START: OUTPUT ENABLE */
12477 /* .. .. .. .. FINISH: OUTPUT ENABLE */
12478 /* .. .. .. .. START: OUTPUT ENABLE */
12479 /* .. .. .. .. FINISH: OUTPUT ENABLE */
12480 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12481 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12482 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12483 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12484 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
12485 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12486 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12487 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12488 /* .. .. .. .. START: ADD 1 MS DELAY */
12489 /* .. .. .. .. */
12490 EMIT_MASKDELAY(0XF8F00200, 1),
12491 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12492 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12493 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12494 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12495 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12496 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12497 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12498 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12499 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12500 /* .. .. .. FINISH: I2C0 RESET */
12501 /* .. .. .. START: I2C1 RESET */
12502 /* .. .. .. .. START: DIR MODE GPIO BANK0 */
12503 /* .. .. .. .. FINISH: DIR MODE GPIO BANK0 */
12504 /* .. .. .. .. START: DIR MODE GPIO BANK1 */
12505 /* .. .. .. .. FINISH: DIR MODE GPIO BANK1 */
12506 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12507 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12508 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12509 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12510 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12511 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12512 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12513 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12514 /* .. .. .. .. START: OUTPUT ENABLE */
12515 /* .. .. .. .. FINISH: OUTPUT ENABLE */
12516 /* .. .. .. .. START: OUTPUT ENABLE */
12517 /* .. .. .. .. FINISH: OUTPUT ENABLE */
12518 /* .. .. .. .. START: MASK_DATA_0_LSW LOW BANK [15:0] */
12519 /* .. .. .. .. FINISH: MASK_DATA_0_LSW LOW BANK [15:0] */
12520 /* .. .. .. .. START: MASK_DATA_0_MSW LOW BANK [31:16] */
12521 /* .. .. .. .. FINISH: MASK_DATA_0_MSW LOW BANK [31:16] */
12522 /* .. .. .. .. START: MASK_DATA_1_LSW LOW BANK [47:32] */
12523 /* .. .. .. .. FINISH: MASK_DATA_1_LSW LOW BANK [47:32] */
12524 /* .. .. .. .. START: MASK_DATA_1_MSW LOW BANK [53:48] */
12525 /* .. .. .. .. FINISH: MASK_DATA_1_MSW LOW BANK [53:48] */
12526 /* .. .. .. .. START: ADD 1 MS DELAY */
12527 /* .. .. .. .. */
12528 EMIT_MASKDELAY(0XF8F00200, 1),
12529 /* .. .. .. .. FINISH: ADD 1 MS DELAY */
12530 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12531 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12532 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
12533 /* .. .. .. .. FINISH: MASK_DATA_0_MSW HIGH BANK [31:16] */
12534 /* .. .. .. .. START: MASK_DATA_1_LSW HIGH BANK [47:32] */
12535 /* .. .. .. .. FINISH: MASK_DATA_1_LSW HIGH BANK [47:32] */
12536 /* .. .. .. .. START: MASK_DATA_1_MSW HIGH BANK [53:48] */
12537 /* .. .. .. .. FINISH: MASK_DATA_1_MSW HIGH BANK [53:48] */
12538 /* .. .. .. FINISH: I2C1 RESET */
12539 /* .. .. FINISH: I2C RESET */
12540 /* .. .. START: NOR CHIP SELECT */
12541 /* .. .. .. START: DIR MODE BANK 0 */
12542 /* .. .. .. FINISH: DIR MODE BANK 0 */
12543 /* .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
12544 /* .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
12545 /* .. .. .. START: OUTPUT ENABLE BANK 0 */
12546 /* .. .. .. FINISH: OUTPUT ENABLE BANK 0 */
12547 /* .. .. FINISH: NOR CHIP SELECT */
12548 /* .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE */
12549 /* FINISH: top */
12550 /* */
12551 EMIT_EXIT(),
12552
12553 /* */
12554 };
12555
12556 unsigned long ps7_post_config_1_0[] = {
12557 /* START: top */
12558 /* .. START: SLCR SETTINGS */
12559 /* .. UNLOCK_KEY = 0XDF0D */
12560 /* .. ==> 0XF8000008[15:0] = 0x0000DF0DU */
12561 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU */
12562 /* .. */
12563 EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU),
12564 /* .. FINISH: SLCR SETTINGS */
12565 /* .. START: ENABLING LEVEL SHIFTER */
12566 /* .. USER_INP_ICT_EN_0 = 3 */
12567 /* .. ==> 0XF8000900[1:0] = 0x00000003U */
12568 /* .. ==> MASK : 0x00000003U VAL : 0x00000003U */
12569 /* .. USER_INP_ICT_EN_1 = 3 */
12570 /* .. ==> 0XF8000900[3:2] = 0x00000003U */
12571 /* .. ==> MASK : 0x0000000CU VAL : 0x0000000CU */
12572 /* .. */
12573 EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
12574 /* .. FINISH: ENABLING LEVEL SHIFTER */
12575 /* .. START: FPGA RESETS TO 0 */
12576 /* .. reserved_3 = 0 */
12577 /* .. ==> 0XF8000240[31:25] = 0x00000000U */
12578 /* .. ==> MASK : 0xFE000000U VAL : 0x00000000U */
12579 /* .. FPGA_ACP_RST = 0 */
12580 /* .. ==> 0XF8000240[24:24] = 0x00000000U */
12581 /* .. ==> MASK : 0x01000000U VAL : 0x00000000U */
12582 /* .. FPGA_AXDS3_RST = 0 */
12583 /* .. ==> 0XF8000240[23:23] = 0x00000000U */
12584 /* .. ==> MASK : 0x00800000U VAL : 0x00000000U */
12585 /* .. FPGA_AXDS2_RST = 0 */
12586 /* .. ==> 0XF8000240[22:22] = 0x00000000U */
12587 /* .. ==> MASK : 0x00400000U VAL : 0x00000000U */
12588 /* .. FPGA_AXDS1_RST = 0 */
12589 /* .. ==> 0XF8000240[21:21] = 0x00000000U */
12590 /* .. ==> MASK : 0x00200000U VAL : 0x00000000U */
12591 /* .. FPGA_AXDS0_RST = 0 */
12592 /* .. ==> 0XF8000240[20:20] = 0x00000000U */
12593 /* .. ==> MASK : 0x00100000U VAL : 0x00000000U */
12594 /* .. reserved_2 = 0 */
12595 /* .. ==> 0XF8000240[19:18] = 0x00000000U */
12596 /* .. ==> MASK : 0x000C0000U VAL : 0x00000000U */
12597 /* .. FSSW1_FPGA_RST = 0 */
12598 /* .. ==> 0XF8000240[17:17] = 0x00000000U */
12599 /* .. ==> MASK : 0x00020000U VAL : 0x00000000U */
12600 /* .. FSSW0_FPGA_RST = 0 */
12601 /* .. ==> 0XF8000240[16:16] = 0x00000000U */
12602 /* .. ==> MASK : 0x00010000U VAL : 0x00000000U */
12603 /* .. reserved_1 = 0 */
12604 /* .. ==> 0XF8000240[15:14] = 0x00000000U */
12605 /* .. ==> MASK : 0x0000C000U VAL : 0x00000000U */
12606 /* .. FPGA_FMSW1_RST = 0 */
12607 /* .. ==> 0XF8000240[13:13] = 0x00000000U */
12608 /* .. ==> MASK : 0x00002000U VAL : 0x00000000U */
12609 /* .. FPGA_FMSW0_RST = 0 */
12610 /* .. ==> 0XF8000240[12:12] = 0x00000000U */
12611 /* .. ==> MASK : 0x00001000U VAL : 0x00000000U */
12612 /* .. FPGA_DMA3_RST = 0 */
12613 /* .. ==> 0XF8000240[11:11] = 0x00000000U */
12614 /* .. ==> MASK : 0x00000800U VAL : 0x00000000U */
12615 /* .. FPGA_DMA2_RST = 0 */
12616 /* .. ==> 0XF8000240[10:10] = 0x00000000U */
12617 /* .. ==> MASK : 0x00000400U VAL : 0x00000000U */
12618 /* .. FPGA_DMA1_RST = 0 */
12619 /* .. ==> 0XF8000240[9:9] = 0x00000000U */
12620 /* .. ==> MASK : 0x00000200U VAL : 0x00000000U */
12621 /* .. FPGA_DMA0_RST = 0 */
12622 /* .. ==> 0XF8000240[8:8] = 0x00000000U */
12623 /* .. ==> MASK : 0x00000100U VAL : 0x00000000U */
12624 /* .. reserved = 0 */
12625 /* .. ==> 0XF8000240[7:4] = 0x00000000U */
12626 /* .. ==> MASK : 0x000000F0U VAL : 0x00000000U */
12627 /* .. FPGA3_OUT_RST = 0 */
12628 /* .. ==> 0XF8000240[3:3] = 0x00000000U */
12629 /* .. ==> MASK : 0x00000008U VAL : 0x00000000U */
12630 /* .. FPGA2_OUT_RST = 0 */
12631 /* .. ==> 0XF8000240[2:2] = 0x00000000U */
12632 /* .. ==> MASK : 0x00000004U VAL : 0x00000000U */
12633 /* .. FPGA1_OUT_RST = 0 */
12634 /* .. ==> 0XF8000240[1:1] = 0x00000000U */
12635 /* .. ==> MASK : 0x00000002U VAL : 0x00000000U */
12636 /* .. FPGA0_OUT_RST = 0 */
12637 /* .. ==> 0XF8000240[0:0] = 0x00000000U */
12638 /* .. ==> MASK : 0x00000001U VAL : 0x00000000U */
12639 /* .. */
12640 EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
12641 /* .. FINISH: FPGA RESETS TO 0 */
12642 /* .. START: AFI REGISTERS */
12643 /* .. .. START: AFI0 REGISTERS */
12644 /* .. .. FINISH: AFI0 REGISTERS */
12645 /* .. .. START: AFI1 REGISTERS */
12646 /* .. .. FINISH: AFI1 REGISTERS */
12647 /* .. .. START: AFI2 REGISTERS */
12648 /* .. .. FINISH: AFI2 REGISTERS */
12649 /* .. .. START: AFI3 REGISTERS */
12650 /* .. .. FINISH: AFI3 REGISTERS */
12651 /* .. FINISH: AFI REGISTERS */
12652 /* .. START: LOCK IT BACK */
12653 /* .. LOCK_KEY = 0X767B */
12654 /* .. ==> 0XF8000004[15:0] = 0x0000767BU */
12655 /* .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU */
12656 /* .. */
12657 EMIT_MASKWRITE(0XF8000004, 0x0000FFFFU, 0x0000767BU),
12658 /* .. FINISH: LOCK IT BACK */
12659 /* FINISH: top */
12660 /* */
12661 EMIT_EXIT(),
12662
12663 /* */
12664 };
12665
12666
12667 #include "xil_io.h"
12668
12669 unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0;
12670 unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0;
12671 unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0;
12672 unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0;
12673 unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
12674
ps7_post_config(void)12675 int ps7_post_config(void)
12676 {
12677 /* Get the PS_VERSION on run time */
12678 unsigned long si_ver = ps7GetSiliconVersion();
12679 int ret = -1;
12680 if (si_ver == PCW_SILICON_VERSION_1) {
12681 ret = ps7_config(ps7_post_config_1_0);
12682 if (ret != PS7_INIT_SUCCESS)
12683 return ret;
12684 } else if (si_ver == PCW_SILICON_VERSION_2) {
12685 ret = ps7_config(ps7_post_config_2_0);
12686 if (ret != PS7_INIT_SUCCESS)
12687 return ret;
12688 } else {
12689 ret = ps7_config(ps7_post_config_3_0);
12690 if (ret != PS7_INIT_SUCCESS)
12691 return ret;
12692 }
12693 return PS7_INIT_SUCCESS;
12694 }
12695
ps7_init(void)12696 int ps7_init(void)
12697 {
12698 /* Get the PS_VERSION on run time */
12699 unsigned long si_ver = ps7GetSiliconVersion();
12700 int ret;
12701 /*int pcw_ver = 0; */
12702
12703 if (si_ver == PCW_SILICON_VERSION_1) {
12704 ps7_mio_init_data = ps7_mio_init_data_1_0;
12705 ps7_pll_init_data = ps7_pll_init_data_1_0;
12706 ps7_clock_init_data = ps7_clock_init_data_1_0;
12707 ps7_ddr_init_data = ps7_ddr_init_data_1_0;
12708 ps7_peripherals_init_data = ps7_peripherals_init_data_1_0;
12709 /*pcw_ver = 1; */
12710
12711 } else if (si_ver == PCW_SILICON_VERSION_2) {
12712 ps7_mio_init_data = ps7_mio_init_data_2_0;
12713 ps7_pll_init_data = ps7_pll_init_data_2_0;
12714 ps7_clock_init_data = ps7_clock_init_data_2_0;
12715 ps7_ddr_init_data = ps7_ddr_init_data_2_0;
12716 ps7_peripherals_init_data = ps7_peripherals_init_data_2_0;
12717 /*pcw_ver = 2; */
12718
12719 } else {
12720 ps7_mio_init_data = ps7_mio_init_data_3_0;
12721 ps7_pll_init_data = ps7_pll_init_data_3_0;
12722 ps7_clock_init_data = ps7_clock_init_data_3_0;
12723 ps7_ddr_init_data = ps7_ddr_init_data_3_0;
12724 ps7_peripherals_init_data = ps7_peripherals_init_data_3_0;
12725 /*pcw_ver = 3; */
12726 }
12727
12728 /* MIO init */
12729 ret = ps7_config(ps7_mio_init_data);
12730 if (ret != PS7_INIT_SUCCESS)
12731 return ret;
12732
12733 /* PLL init */
12734 ret = ps7_config(ps7_pll_init_data);
12735 if (ret != PS7_INIT_SUCCESS)
12736 return ret;
12737
12738 /* Clock init */
12739 ret = ps7_config(ps7_clock_init_data);
12740 if (ret != PS7_INIT_SUCCESS)
12741 return ret;
12742
12743 /* DDR init */
12744 ret = ps7_config(ps7_ddr_init_data);
12745 if (ret != PS7_INIT_SUCCESS)
12746 return ret;
12747
12748 /* Peripherals init */
12749 ret = ps7_config(ps7_peripherals_init_data);
12750 if (ret != PS7_INIT_SUCCESS)
12751 return ret;
12752 return PS7_INIT_SUCCESS;
12753 }
12754
12755