Name Date Size #Lines LOC

..07-Mar-2021-

KconfigH A D07-Mar-2021434 2517

MAINTAINERSH A D07-Mar-2021175 76

MakefileH A D07-Mar-2021250 115

READMEH A D07-Mar-20212.9 KiB9271

work_92105.cH A D07-Mar-20211.7 KiB7750

work_92105_display.cH A D02-Mar-20238.9 KiB350207

work_92105_display.hH A D07-Mar-2021401 141

work_92105_spl.cH A D07-Mar-20211.9 KiB8562

README

1Work_92105 from Work Microwave is an LPC3250- based board with the
2following features:
3
4    - 64MB SDR DRAM
5    - 1 GB SLC NAND, managed through MLC controller.
6    - Ethernet
7    - Ethernet + PHY SMSC8710
8    - I2C:
9      - EEPROM (24M01-compatible)
10      - RTC (DS1374-compatible)
11      - Temperature sensor (DS620)
12      - DACs (2 x MAX518)
13    - SPI (through SSP interface)
14      - Port expander MAX6957
15    - LCD display (HD44780-compatible), controlled
16      through the port expander and DACs
17
18Standard SPL and U-Boot binaries
19--------------------------------
20
21The default 'make' (or the 'make all') command will produce the
22following files:
23
241. spl/u-boot-spl.bin	SPL, intended to run from SRAM at address 0.
25			This file can be loaded in SRAM through a JTAG
26			debugger or through the LPC32XX Service Boot
27			mechanism.
28
292. u-boot.bin		The raw U-Boot image, which can be loaded in
30			DDR through a JTAG debugger (for instance by
31			breaking SPL after DDR init), or by a running
32			U-Boot through e.g. 'loady' or 'tftp' and then
33			executed with 'go'.
34
353. u-boot.img		A U-Boot image with a mkimage header prepended.
36			SPL assumes (even when loaded through JTAG or
37			Service Boot) that such an image will be found
38			at offset 0x00040000 in NAND.
39
40NAND cold-boot binaries
41-----------------------
42
43The board can boot entirely from power-on with only SPL and U-Boot in
44NAND. The LPC32XX-specific 'make lpc32xx-full.bin' command will produce
45(in addition to spl/u-boot-spl.bin and u-boot.img if they were not made
46already) the following files:
47
484. lpc32xx-spl.img	spl/u-boot-spl.bin, with a LPC32XX boot header
49			prepended. This header is required for the ROM
50			code to load SPL into SRAM and branch into it.
51			The content of this file is expected to reside
52			in NAND at addresses 0x00000000 and 0x00020000
53			(two copies).
54
555. lpc32xx-boot-0.bin	lpc32xx-spl.img, padded with 0xFF bytes to a
56			size of 0x20000 bytes. This file covers exactly
57			the reserved area for the first bootloader copy
58			in NAND.
59
606. lpc32xx-boot-1.bin	Same as lpc32xx-boot-0.bin. This is intended to
61			be used as the second bootloader copy.
62
637. lpc32xx-full.bin	lpc32xx-boot-0.bin, lpc32xx-boot-1.bin and
64			u-boot.img concatenated. This file represents
65			the content of whole bootloader as present in
66			NAND at offset 00x00000000.
67
68Flashing instructions
69---------------------
70
71The following assumes a working U-Boot on the target, with the ability
72to load files into DDR.
73
74To update the whole bootloader:
75
76	nand erase 0x00000000 0x80000
77	(load lpc32xx-full.bin at location $loadaddr)
78	nand write $loadaddr 0x00000000 $filesize
79
80To update SPL only (note the double nand write) :
81
82	nand erase 0x00000000 0x40000
83	(load lpc32xx-spl.img or lpc32xx-boot-N.bin at location $loadaddr)
84	nand write $loadaddr 0x00000000 $filesize
85	nand write $loadaddr 0x00020000 $filesize
86
87To update U-Boot only:
88
89	nand erase 0x00040000 0x40000
90	(load u-boot.img at location $loadaddr)
91	nand write $loadaddr 0x00040000 $filesize
92