1e595107eSHao Zhang /* 2e595107eSHao Zhang * Keystone2: DDR3 initialization 3e595107eSHao Zhang * 4e595107eSHao Zhang * (C) Copyright 2012-2014 5e595107eSHao Zhang * Texas Instruments Incorporated, <www.ti.com> 6e595107eSHao Zhang * 7e595107eSHao Zhang * SPDX-License-Identifier: GPL-2.0+ 8e595107eSHao Zhang */ 9e595107eSHao Zhang 10e595107eSHao Zhang #include <common.h> 11b1babef8SHao Zhang #include "ddr3_cfg.h" 12e595107eSHao Zhang #include <asm/arch/ddr3.h> 13e595107eSHao Zhang #include <asm/arch/hardware.h> 14e595107eSHao Zhang 15e595107eSHao Zhang struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); 16e595107eSHao Zhang struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); 17e595107eSHao Zhang 1866c98a0cSVitaly Andrianov u32 ddr3_init(void) 19e595107eSHao Zhang { 2066c98a0cSVitaly Andrianov u32 ddr3_size; 21*d9a76e77SVitaly Andrianov struct ddr3_spd_cb spd_cb; 22e595107eSHao Zhang 23*d9a76e77SVitaly Andrianov if (ddr3_get_dimm_params_from_spd(&spd_cb)) { 24*d9a76e77SVitaly Andrianov printf("Sorry, I don't know how to configure DDR3A.\n" 25*d9a76e77SVitaly Andrianov "Bye :(\n"); 26*d9a76e77SVitaly Andrianov for (;;) 27e595107eSHao Zhang ; 28e595107eSHao Zhang } 296c343825SMurali Karicheri 30*d9a76e77SVitaly Andrianov printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name); 31*d9a76e77SVitaly Andrianov 32*d9a76e77SVitaly Andrianov if ((cpu_revision() > 1) || 33*d9a76e77SVitaly Andrianov (__raw_readl(KS2_RSTCTRL_RSTYPE) & 0x1)) { 34*d9a76e77SVitaly Andrianov printf("DDR3 speed %d\n", spd_cb.ddrspdclock); 35*d9a76e77SVitaly Andrianov if (spd_cb.ddrspdclock == 1600) 36*d9a76e77SVitaly Andrianov init_pll(&ddr3a_400); 37*d9a76e77SVitaly Andrianov else 38*d9a76e77SVitaly Andrianov init_pll(&ddr3a_333); 39*d9a76e77SVitaly Andrianov } 40*d9a76e77SVitaly Andrianov 41*d9a76e77SVitaly Andrianov if (cpu_revision() > 0) { 42*d9a76e77SVitaly Andrianov if (cpu_revision() > 1) { 43*d9a76e77SVitaly Andrianov /* PG 2.0 */ 44*d9a76e77SVitaly Andrianov /* Reset DDR3A PHY after PLL enabled */ 45*d9a76e77SVitaly Andrianov ddr3_reset_ddrphy(); 46*d9a76e77SVitaly Andrianov spd_cb.phy_cfg.zq0cr1 |= 0x10000; 47*d9a76e77SVitaly Andrianov spd_cb.phy_cfg.zq1cr1 |= 0x10000; 48*d9a76e77SVitaly Andrianov spd_cb.phy_cfg.zq2cr1 |= 0x10000; 49*d9a76e77SVitaly Andrianov } 50*d9a76e77SVitaly Andrianov ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); 51*d9a76e77SVitaly Andrianov 52*d9a76e77SVitaly Andrianov ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); 53*d9a76e77SVitaly Andrianov 54*d9a76e77SVitaly Andrianov ddr3_size = spd_cb.ddr_size_gbyte; 55*d9a76e77SVitaly Andrianov } else { 56*d9a76e77SVitaly Andrianov ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &spd_cb.phy_cfg); 57*d9a76e77SVitaly Andrianov spd_cb.emif_cfg.sdcfg |= 0x1000; 58*d9a76e77SVitaly Andrianov ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &spd_cb.emif_cfg); 59*d9a76e77SVitaly Andrianov ddr3_size = spd_cb.ddr_size_gbyte / 2; 60*d9a76e77SVitaly Andrianov } 61*d9a76e77SVitaly Andrianov printf("DRAM: %d GiB (includes reported below)\n", ddr3_size); 62*d9a76e77SVitaly Andrianov 636c343825SMurali Karicheri /* Apply the workaround for PG 1.0 and 1.1 Silicons */ 646c343825SMurali Karicheri if (cpu_revision() <= 1) 656c343825SMurali Karicheri ddr3_err_reset_workaround(); 6689f44bb0SVitaly Andrianov 6789f44bb0SVitaly Andrianov return ddr3_size; 6889f44bb0SVitaly Andrianov } 69