1e595107eSHao Zhang /* 2e595107eSHao Zhang * Keystone2: DDR3 initialization 3e595107eSHao Zhang * 4e595107eSHao Zhang * (C) Copyright 2012-2014 5e595107eSHao Zhang * Texas Instruments Incorporated, <www.ti.com> 6e595107eSHao Zhang * 7e595107eSHao Zhang * SPDX-License-Identifier: GPL-2.0+ 8e595107eSHao Zhang */ 9e595107eSHao Zhang 10e595107eSHao Zhang #include <common.h> 11*b1babef8SHao Zhang #include "ddr3_cfg.h" 12e595107eSHao Zhang #include <asm/arch/ddr3.h> 13e595107eSHao Zhang #include <asm/arch/hardware.h> 14e595107eSHao Zhang 15e595107eSHao Zhang struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); 16e595107eSHao Zhang struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); 17e595107eSHao Zhang 18e595107eSHao Zhang void ddr3_init(void) 19e595107eSHao Zhang { 20e595107eSHao Zhang char dimm_name[32]; 21e595107eSHao Zhang 22*b1babef8SHao Zhang ddr3_get_dimm_params(dimm_name); 23e595107eSHao Zhang 24e595107eSHao Zhang printf("Detected SO-DIMM [%s]\n", dimm_name); 25e595107eSHao Zhang 26e595107eSHao Zhang if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { 27e595107eSHao Zhang init_pll(&ddr3a_400); 28e595107eSHao Zhang if (cpu_revision() > 0) { 29e595107eSHao Zhang if (cpu_revision() > 1) { 30e595107eSHao Zhang /* PG 2.0 */ 31e595107eSHao Zhang /* Reset DDR3A PHY after PLL enabled */ 32e595107eSHao Zhang ddr3_reset_ddrphy(); 33*b1babef8SHao Zhang ddr3phy_1600_8g.zq0cr1 |= 0x10000; 34*b1babef8SHao Zhang ddr3phy_1600_8g.zq1cr1 |= 0x10000; 35*b1babef8SHao Zhang ddr3phy_1600_8g.zq2cr1 |= 0x10000; 36e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 37*b1babef8SHao Zhang &ddr3phy_1600_8g); 38e595107eSHao Zhang } else { 39e595107eSHao Zhang /* PG 1.1 */ 40e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 41*b1babef8SHao Zhang &ddr3phy_1600_8g); 42e595107eSHao Zhang } 43e595107eSHao Zhang 44e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 45*b1babef8SHao Zhang &ddr3_1600_8g); 46e595107eSHao Zhang printf("DRAM: Capacity 8 GiB (includes reported below)\n"); 47e595107eSHao Zhang } else { 48*b1babef8SHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); 49*b1babef8SHao Zhang ddr3_1600_8g.sdcfg |= 0x1000; 50e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 51*b1babef8SHao Zhang &ddr3_1600_8g); 52e595107eSHao Zhang printf("DRAM: Capacity 4 GiB (includes reported below)\n"); 53e595107eSHao Zhang } 54e595107eSHao Zhang } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { 55e595107eSHao Zhang init_pll(&ddr3a_333); 56e595107eSHao Zhang if (cpu_revision() > 0) { 57e595107eSHao Zhang if (cpu_revision() > 1) { 58e595107eSHao Zhang /* PG 2.0 */ 59e595107eSHao Zhang /* Reset DDR3A PHY after PLL enabled */ 60e595107eSHao Zhang ddr3_reset_ddrphy(); 61*b1babef8SHao Zhang ddr3phy_1333_2g.zq0cr1 |= 0x10000; 62*b1babef8SHao Zhang ddr3phy_1333_2g.zq1cr1 |= 0x10000; 63*b1babef8SHao Zhang ddr3phy_1333_2g.zq2cr1 |= 0x10000; 64e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 65*b1babef8SHao Zhang &ddr3phy_1333_2g); 66e595107eSHao Zhang } else { 67e595107eSHao Zhang /* PG 1.1 */ 68e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 69*b1babef8SHao Zhang &ddr3phy_1333_2g); 70e595107eSHao Zhang } 71e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 72*b1babef8SHao Zhang &ddr3_1333_2g); 73e595107eSHao Zhang } else { 74*b1babef8SHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g); 75*b1babef8SHao Zhang ddr3_1333_2g.sdcfg |= 0x1000; 76e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 77*b1babef8SHao Zhang &ddr3_1333_2g); 78e595107eSHao Zhang } 79e595107eSHao Zhang } else { 80e595107eSHao Zhang printf("Unknown SO-DIMM. Cannot configure DDR3\n"); 81e595107eSHao Zhang while (1) 82e595107eSHao Zhang ; 83e595107eSHao Zhang } 84e595107eSHao Zhang } 85