1e595107eSHao Zhang /* 2e595107eSHao Zhang * Keystone2: DDR3 initialization 3e595107eSHao Zhang * 4e595107eSHao Zhang * (C) Copyright 2012-2014 5e595107eSHao Zhang * Texas Instruments Incorporated, <www.ti.com> 6e595107eSHao Zhang * 7e595107eSHao Zhang * SPDX-License-Identifier: GPL-2.0+ 8e595107eSHao Zhang */ 9e595107eSHao Zhang 10e595107eSHao Zhang #include <common.h> 11b1babef8SHao Zhang #include "ddr3_cfg.h" 12e595107eSHao Zhang #include <asm/arch/ddr3.h> 13e595107eSHao Zhang #include <asm/arch/hardware.h> 14e595107eSHao Zhang 15*89f44bb0SVitaly Andrianov static int ddr3_size; 16*89f44bb0SVitaly Andrianov 17e595107eSHao Zhang struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); 18e595107eSHao Zhang struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); 19e595107eSHao Zhang 20e595107eSHao Zhang void ddr3_init(void) 21e595107eSHao Zhang { 22e595107eSHao Zhang char dimm_name[32]; 23e595107eSHao Zhang 24b1babef8SHao Zhang ddr3_get_dimm_params(dimm_name); 25e595107eSHao Zhang 26e595107eSHao Zhang printf("Detected SO-DIMM [%s]\n", dimm_name); 27e595107eSHao Zhang 28e595107eSHao Zhang if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { 29e595107eSHao Zhang init_pll(&ddr3a_400); 30e595107eSHao Zhang if (cpu_revision() > 0) { 31e595107eSHao Zhang if (cpu_revision() > 1) { 32e595107eSHao Zhang /* PG 2.0 */ 33e595107eSHao Zhang /* Reset DDR3A PHY after PLL enabled */ 34e595107eSHao Zhang ddr3_reset_ddrphy(); 35b1babef8SHao Zhang ddr3phy_1600_8g.zq0cr1 |= 0x10000; 36b1babef8SHao Zhang ddr3phy_1600_8g.zq1cr1 |= 0x10000; 37b1babef8SHao Zhang ddr3phy_1600_8g.zq2cr1 |= 0x10000; 38e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 39b1babef8SHao Zhang &ddr3phy_1600_8g); 40e595107eSHao Zhang } else { 41e595107eSHao Zhang /* PG 1.1 */ 42e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 43b1babef8SHao Zhang &ddr3phy_1600_8g); 44e595107eSHao Zhang } 45e595107eSHao Zhang 46e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 47b1babef8SHao Zhang &ddr3_1600_8g); 48e595107eSHao Zhang printf("DRAM: Capacity 8 GiB (includes reported below)\n"); 49*89f44bb0SVitaly Andrianov ddr3_size = 8; 50e595107eSHao Zhang } else { 51b1babef8SHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); 52b1babef8SHao Zhang ddr3_1600_8g.sdcfg |= 0x1000; 53e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 54b1babef8SHao Zhang &ddr3_1600_8g); 55e595107eSHao Zhang printf("DRAM: Capacity 4 GiB (includes reported below)\n"); 56*89f44bb0SVitaly Andrianov ddr3_size = 4; 57e595107eSHao Zhang } 58e595107eSHao Zhang } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { 59e595107eSHao Zhang init_pll(&ddr3a_333); 60e595107eSHao Zhang if (cpu_revision() > 0) { 61e595107eSHao Zhang if (cpu_revision() > 1) { 62e595107eSHao Zhang /* PG 2.0 */ 63e595107eSHao Zhang /* Reset DDR3A PHY after PLL enabled */ 64e595107eSHao Zhang ddr3_reset_ddrphy(); 65b1babef8SHao Zhang ddr3phy_1333_2g.zq0cr1 |= 0x10000; 66b1babef8SHao Zhang ddr3phy_1333_2g.zq1cr1 |= 0x10000; 67b1babef8SHao Zhang ddr3phy_1333_2g.zq2cr1 |= 0x10000; 68e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 69b1babef8SHao Zhang &ddr3phy_1333_2g); 70e595107eSHao Zhang } else { 71e595107eSHao Zhang /* PG 1.1 */ 72e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 73b1babef8SHao Zhang &ddr3phy_1333_2g); 74e595107eSHao Zhang } 75e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 76b1babef8SHao Zhang &ddr3_1333_2g); 77*89f44bb0SVitaly Andrianov ddr3_size = 2; 78*89f44bb0SVitaly Andrianov printf("DRAM: 2 GiB"); 79e595107eSHao Zhang } else { 80b1babef8SHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g); 81b1babef8SHao Zhang ddr3_1333_2g.sdcfg |= 0x1000; 82e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 83b1babef8SHao Zhang &ddr3_1333_2g); 84*89f44bb0SVitaly Andrianov ddr3_size = 1; 85*89f44bb0SVitaly Andrianov printf("DRAM: 1 GiB"); 86e595107eSHao Zhang } 87e595107eSHao Zhang } else { 88e595107eSHao Zhang printf("Unknown SO-DIMM. Cannot configure DDR3\n"); 89e595107eSHao Zhang while (1) 90e595107eSHao Zhang ; 91e595107eSHao Zhang } 926c343825SMurali Karicheri 936c343825SMurali Karicheri /* Apply the workaround for PG 1.0 and 1.1 Silicons */ 946c343825SMurali Karicheri if (cpu_revision() <= 1) 956c343825SMurali Karicheri ddr3_err_reset_workaround(); 96e595107eSHao Zhang } 97*89f44bb0SVitaly Andrianov 98*89f44bb0SVitaly Andrianov /** 99*89f44bb0SVitaly Andrianov * ddr3_get_size - return ddr3 size in GiB 100*89f44bb0SVitaly Andrianov */ 101*89f44bb0SVitaly Andrianov int ddr3_get_size(void) 102*89f44bb0SVitaly Andrianov { 103*89f44bb0SVitaly Andrianov return ddr3_size; 104*89f44bb0SVitaly Andrianov } 105