1e595107eSHao Zhang /* 2e595107eSHao Zhang * Keystone2: DDR3 initialization 3e595107eSHao Zhang * 4e595107eSHao Zhang * (C) Copyright 2012-2014 5e595107eSHao Zhang * Texas Instruments Incorporated, <www.ti.com> 6e595107eSHao Zhang * 7e595107eSHao Zhang * SPDX-License-Identifier: GPL-2.0+ 8e595107eSHao Zhang */ 9e595107eSHao Zhang 10e595107eSHao Zhang #include <common.h> 11b1babef8SHao Zhang #include "ddr3_cfg.h" 12e595107eSHao Zhang #include <asm/arch/ddr3.h> 13e595107eSHao Zhang #include <asm/arch/hardware.h> 14e595107eSHao Zhang 15e595107eSHao Zhang struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); 16e595107eSHao Zhang struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); 17e595107eSHao Zhang 18*66c98a0cSVitaly Andrianov u32 ddr3_init(void) 19e595107eSHao Zhang { 20e595107eSHao Zhang char dimm_name[32]; 21*66c98a0cSVitaly Andrianov u32 ddr3_size; 22e595107eSHao Zhang 23b1babef8SHao Zhang ddr3_get_dimm_params(dimm_name); 24e595107eSHao Zhang 25e595107eSHao Zhang printf("Detected SO-DIMM [%s]\n", dimm_name); 26e595107eSHao Zhang 27e595107eSHao Zhang if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { 28e595107eSHao Zhang init_pll(&ddr3a_400); 29e595107eSHao Zhang if (cpu_revision() > 0) { 30e595107eSHao Zhang if (cpu_revision() > 1) { 31e595107eSHao Zhang /* PG 2.0 */ 32e595107eSHao Zhang /* Reset DDR3A PHY after PLL enabled */ 33e595107eSHao Zhang ddr3_reset_ddrphy(); 34b1babef8SHao Zhang ddr3phy_1600_8g.zq0cr1 |= 0x10000; 35b1babef8SHao Zhang ddr3phy_1600_8g.zq1cr1 |= 0x10000; 36b1babef8SHao Zhang ddr3phy_1600_8g.zq2cr1 |= 0x10000; 37e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 38b1babef8SHao Zhang &ddr3phy_1600_8g); 39e595107eSHao Zhang } else { 40e595107eSHao Zhang /* PG 1.1 */ 41e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 42b1babef8SHao Zhang &ddr3phy_1600_8g); 43e595107eSHao Zhang } 44e595107eSHao Zhang 45e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 46b1babef8SHao Zhang &ddr3_1600_8g); 47e595107eSHao Zhang printf("DRAM: Capacity 8 GiB (includes reported below)\n"); 4889f44bb0SVitaly Andrianov ddr3_size = 8; 49e595107eSHao Zhang } else { 50b1babef8SHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); 51b1babef8SHao Zhang ddr3_1600_8g.sdcfg |= 0x1000; 52e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 53b1babef8SHao Zhang &ddr3_1600_8g); 54e595107eSHao Zhang printf("DRAM: Capacity 4 GiB (includes reported below)\n"); 5589f44bb0SVitaly Andrianov ddr3_size = 4; 56e595107eSHao Zhang } 57e595107eSHao Zhang } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { 58e595107eSHao Zhang init_pll(&ddr3a_333); 59e595107eSHao Zhang if (cpu_revision() > 0) { 60e595107eSHao Zhang if (cpu_revision() > 1) { 61e595107eSHao Zhang /* PG 2.0 */ 62e595107eSHao Zhang /* Reset DDR3A PHY after PLL enabled */ 63e595107eSHao Zhang ddr3_reset_ddrphy(); 64b1babef8SHao Zhang ddr3phy_1333_2g.zq0cr1 |= 0x10000; 65b1babef8SHao Zhang ddr3phy_1333_2g.zq1cr1 |= 0x10000; 66b1babef8SHao Zhang ddr3phy_1333_2g.zq2cr1 |= 0x10000; 67e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 68b1babef8SHao Zhang &ddr3phy_1333_2g); 69e595107eSHao Zhang } else { 70e595107eSHao Zhang /* PG 1.1 */ 71e595107eSHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, 72b1babef8SHao Zhang &ddr3phy_1333_2g); 73e595107eSHao Zhang } 74e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 75b1babef8SHao Zhang &ddr3_1333_2g); 7689f44bb0SVitaly Andrianov ddr3_size = 2; 7789f44bb0SVitaly Andrianov printf("DRAM: 2 GiB"); 78e595107eSHao Zhang } else { 79b1babef8SHao Zhang ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g); 80b1babef8SHao Zhang ddr3_1333_2g.sdcfg |= 0x1000; 81e595107eSHao Zhang ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, 82b1babef8SHao Zhang &ddr3_1333_2g); 8389f44bb0SVitaly Andrianov ddr3_size = 1; 8489f44bb0SVitaly Andrianov printf("DRAM: 1 GiB"); 85e595107eSHao Zhang } 86e595107eSHao Zhang } else { 87e595107eSHao Zhang printf("Unknown SO-DIMM. Cannot configure DDR3\n"); 88e595107eSHao Zhang while (1) 89e595107eSHao Zhang ; 90e595107eSHao Zhang } 916c343825SMurali Karicheri 926c343825SMurali Karicheri /* Apply the workaround for PG 1.0 and 1.1 Silicons */ 936c343825SMurali Karicheri if (cpu_revision() <= 1) 946c343825SMurali Karicheri ddr3_err_reset_workaround(); 9589f44bb0SVitaly Andrianov 9689f44bb0SVitaly Andrianov return ddr3_size; 9789f44bb0SVitaly Andrianov } 98