1 /* 2 * board/renesas/alt/alt.c 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <dm.h> 12 #include <dm/platform_data/serial_sh.h> 13 #include <asm/processor.h> 14 #include <asm/mach-types.h> 15 #include <asm/io.h> 16 #include <asm/errno.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/gpio.h> 19 #include <asm/arch/rmobile.h> 20 #include <asm/arch/rcar-mstp.h> 21 #include <asm/arch/mmc.h> 22 #include <asm/arch/sh_sdhi.h> 23 #include <netdev.h> 24 #include <miiphy.h> 25 #include <i2c.h> 26 #include <div64.h> 27 #include "qos.h" 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define CLK2MHZ(clk) (clk / 1000 / 1000) 32 void s_init(void) 33 { 34 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 35 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 36 37 /* Watchdog init */ 38 writel(0xA5A5A500, &rwdt->rwtcsra); 39 writel(0xA5A5A500, &swdt->swtcsra); 40 41 /* QoS */ 42 qos_init(); 43 } 44 45 #define TMU0_MSTP125 (1 << 25) 46 #define SCIF2_MSTP719 (1 << 19) 47 #define ETHER_MSTP813 (1 << 13) 48 #define IIC1_MSTP323 (1 << 23) 49 #define MMC0_MSTP315 (1 << 15) 50 #define SDHI0_MSTP314 (1 << 14) 51 #define SDHI1_MSTP312 (1 << 12) 52 53 #define SD1CKCR 0xE6150078 54 #define SD1_97500KHZ 0x7 55 56 int board_early_init_f(void) 57 { 58 /* TMU */ 59 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 60 61 /* SCIF2 */ 62 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); 63 64 /* ETHER */ 65 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 66 67 /* IIC1 / sh-i2c ch1 */ 68 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); 69 70 #ifdef CONFIG_SH_MMCIF 71 /* MMC */ 72 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); 73 #endif 74 75 #ifdef CONFIG_SH_SDHI 76 /* SDHI0, 1 */ 77 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312); 78 79 /* 80 * SD0 clock is set to 97.5MHz by default. 81 * Set SD1 to the 97.5MHz as well. 82 */ 83 writel(SD1_97500KHZ, SD1CKCR); 84 #endif 85 return 0; 86 } 87 88 int board_init(void) 89 { 90 /* adress of boot parameters */ 91 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 92 93 /* Init PFC controller */ 94 r8a7794_pinmux_init(); 95 96 /* Ether Enable */ 97 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 98 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 99 gpio_request(GPIO_FN_ETH_RXD0, NULL); 100 gpio_request(GPIO_FN_ETH_RXD1, NULL); 101 gpio_request(GPIO_FN_ETH_LINK, NULL); 102 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 103 gpio_request(GPIO_FN_ETH_MDIO, NULL); 104 gpio_request(GPIO_FN_ETH_TXD1, NULL); 105 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 106 gpio_request(GPIO_FN_ETH_MAGIC, NULL); 107 gpio_request(GPIO_FN_ETH_TXD0, NULL); 108 gpio_request(GPIO_FN_ETH_MDC, NULL); 109 gpio_request(GPIO_FN_IRQ8, NULL); 110 111 /* PHY reset */ 112 gpio_request(GPIO_GP_1_24, NULL); 113 gpio_direction_output(GPIO_GP_1_24, 0); 114 mdelay(20); 115 gpio_set_value(GPIO_GP_1_24, 1); 116 udelay(1); 117 118 return 0; 119 } 120 121 #define CXR24 0xEE7003C0 /* MAC address high register */ 122 #define CXR25 0xEE7003C8 /* MAC address low register */ 123 int board_eth_init(bd_t *bis) 124 { 125 #ifdef CONFIG_SH_ETHER 126 int ret = -ENODEV; 127 u32 val; 128 unsigned char enetaddr[6]; 129 130 ret = sh_eth_initialize(bis); 131 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 132 return ret; 133 134 /* Set Mac address */ 135 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 136 enetaddr[2] << 8 | enetaddr[3]; 137 writel(val, CXR24); 138 139 val = enetaddr[4] << 8 | enetaddr[5]; 140 writel(val, CXR25); 141 142 return ret; 143 #else 144 return 0; 145 #endif 146 } 147 148 int board_mmc_init(bd_t *bis) 149 { 150 int ret = -ENODEV; 151 152 #ifdef CONFIG_SH_MMCIF 153 gpio_request(GPIO_GP_4_31, NULL); 154 gpio_set_value(GPIO_GP_4_31, 1); 155 156 ret = mmcif_mmc_init(); 157 #endif 158 159 #ifdef CONFIG_SH_SDHI 160 gpio_request(GPIO_FN_SD0_DATA0, NULL); 161 gpio_request(GPIO_FN_SD0_DATA1, NULL); 162 gpio_request(GPIO_FN_SD0_DATA2, NULL); 163 gpio_request(GPIO_FN_SD0_DATA3, NULL); 164 gpio_request(GPIO_FN_SD0_CLK, NULL); 165 gpio_request(GPIO_FN_SD0_CMD, NULL); 166 gpio_request(GPIO_FN_SD0_CD, NULL); 167 gpio_request(GPIO_FN_SD1_DATA0, NULL); 168 gpio_request(GPIO_FN_SD1_DATA1, NULL); 169 gpio_request(GPIO_FN_SD1_DATA2, NULL); 170 gpio_request(GPIO_FN_SD1_DATA3, NULL); 171 gpio_request(GPIO_FN_SD1_CLK, NULL); 172 gpio_request(GPIO_FN_SD1_CMD, NULL); 173 gpio_request(GPIO_FN_SD1_CD, NULL); 174 175 /* SDHI 0 */ 176 gpio_request(GPIO_GP_2_26, NULL); 177 gpio_request(GPIO_GP_2_29, NULL); 178 gpio_direction_output(GPIO_GP_2_26, 1); 179 gpio_direction_output(GPIO_GP_2_29, 1); 180 181 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, 182 SH_SDHI_QUIRK_16BIT_BUF); 183 if (ret) 184 return ret; 185 186 /* SDHI 1 */ 187 gpio_request(GPIO_GP_4_26, NULL); 188 gpio_request(GPIO_GP_4_29, NULL); 189 gpio_direction_output(GPIO_GP_4_26, 1); 190 gpio_direction_output(GPIO_GP_4_29, 1); 191 192 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); 193 #endif 194 return ret; 195 } 196 197 int dram_init(void) 198 { 199 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 200 201 return 0; 202 } 203 204 const struct rmobile_sysinfo sysinfo = { 205 CONFIG_RMOBILE_BOARD_STRING 206 }; 207 208 void reset_cpu(ulong addr) 209 { 210 u8 val; 211 212 i2c_set_bus_num(1); /* PowerIC connected to ch1 */ 213 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 214 val |= 0x02; 215 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 216 } 217 218 static const struct sh_serial_platdata serial_platdata = { 219 .base = SCIF2_BASE, 220 .type = PORT_SCIF, 221 .clk = 14745600, 222 .clk_mode = EXT_CLK, 223 }; 224 225 U_BOOT_DEVICE(alt_serials) = { 226 .name = "serial_sh", 227 .platdata = &serial_platdata, 228 }; 229