1 /* 2 * board/renesas/alt/alt.c 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <asm/processor.h> 12 #include <asm/mach-types.h> 13 #include <asm/io.h> 14 #include <asm/errno.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/rmobile.h> 18 #include <asm/arch/rcar-mstp.h> 19 #include <asm/arch/mmc.h> 20 #include <netdev.h> 21 #include <miiphy.h> 22 #include <i2c.h> 23 #include <div64.h> 24 #include "qos.h" 25 26 DECLARE_GLOBAL_DATA_PTR; 27 28 #define CLK2MHZ(clk) (clk / 1000 / 1000) 29 void s_init(void) 30 { 31 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 32 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 33 34 /* Watchdog init */ 35 writel(0xA5A5A500, &rwdt->rwtcsra); 36 writel(0xA5A5A500, &swdt->swtcsra); 37 38 /* QoS */ 39 qos_init(); 40 } 41 42 #define TMU0_MSTP125 (1 << 25) 43 #define SCIF2_MSTP719 (1 << 19) 44 #define ETHER_MSTP813 (1 << 13) 45 #define IIC1_MSTP323 (1 << 23) 46 #define MMC0_MSTP315 (1 << 15) 47 48 int board_early_init_f(void) 49 { 50 /* TMU */ 51 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 52 53 /* SCIF2 */ 54 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); 55 56 /* ETHER */ 57 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 58 59 /* IIC1 / sh-i2c ch1 */ 60 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); 61 62 #ifdef CONFIG_SH_MMCIF 63 /* MMC */ 64 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); 65 #endif 66 return 0; 67 } 68 69 int board_init(void) 70 { 71 /* adress of boot parameters */ 72 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 73 74 /* Init PFC controller */ 75 r8a7794_pinmux_init(); 76 77 /* Ether Enable */ 78 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 79 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 80 gpio_request(GPIO_FN_ETH_RXD0, NULL); 81 gpio_request(GPIO_FN_ETH_RXD1, NULL); 82 gpio_request(GPIO_FN_ETH_LINK, NULL); 83 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 84 gpio_request(GPIO_FN_ETH_MDIO, NULL); 85 gpio_request(GPIO_FN_ETH_TXD1, NULL); 86 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 87 gpio_request(GPIO_FN_ETH_MAGIC, NULL); 88 gpio_request(GPIO_FN_ETH_TXD0, NULL); 89 gpio_request(GPIO_FN_ETH_MDC, NULL); 90 gpio_request(GPIO_FN_IRQ8, NULL); 91 92 /* PHY reset */ 93 gpio_request(GPIO_GP_1_24, NULL); 94 gpio_direction_output(GPIO_GP_1_24, 0); 95 mdelay(20); 96 gpio_set_value(GPIO_GP_1_24, 1); 97 udelay(1); 98 99 return 0; 100 } 101 102 #define CXR24 0xEE7003C0 /* MAC address high register */ 103 #define CXR25 0xEE7003C8 /* MAC address low register */ 104 int board_eth_init(bd_t *bis) 105 { 106 #ifdef CONFIG_SH_ETHER 107 int ret = -ENODEV; 108 u32 val; 109 unsigned char enetaddr[6]; 110 111 ret = sh_eth_initialize(bis); 112 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 113 return ret; 114 115 /* Set Mac address */ 116 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 117 enetaddr[2] << 8 | enetaddr[3]; 118 writel(val, CXR24); 119 120 val = enetaddr[4] << 8 | enetaddr[5]; 121 writel(val, CXR25); 122 123 return ret; 124 #else 125 return 0; 126 #endif 127 } 128 129 int board_mmc_init(bd_t *bis) 130 { 131 int ret = 0; 132 133 #ifdef CONFIG_SH_MMCIF 134 gpio_request(GPIO_GP_4_31, NULL); 135 gpio_set_value(GPIO_GP_4_31, 1); 136 137 ret = mmcif_mmc_init(); 138 #endif 139 return ret; 140 } 141 142 int dram_init(void) 143 { 144 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 145 146 return 0; 147 } 148 149 const struct rmobile_sysinfo sysinfo = { 150 CONFIG_RMOBILE_BOARD_STRING 151 }; 152 153 void reset_cpu(ulong addr) 154 { 155 u8 val; 156 157 i2c_set_bus_num(1); /* PowerIC connected to ch1 */ 158 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 159 val |= 0x02; 160 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 161 } 162