1 /* 2 * board/renesas/alt/alt.c 3 * 4 * Copyright (C) 2014 Renesas Electronics Corporation 5 * 6 * SPDX-License-Identifier: GPL-2.0 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <asm/processor.h> 12 #include <asm/mach-types.h> 13 #include <asm/io.h> 14 #include <asm/errno.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/arch/rmobile.h> 18 #include <netdev.h> 19 #include <miiphy.h> 20 #include <i2c.h> 21 #include <div64.h> 22 #include "qos.h" 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 #define CLK2MHZ(clk) (clk / 1000 / 1000) 27 void s_init(void) 28 { 29 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; 30 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; 31 32 /* Watchdog init */ 33 writel(0xA5A5A500, &rwdt->rwtcsra); 34 writel(0xA5A5A500, &swdt->swtcsra); 35 36 /* QoS */ 37 qos_init(); 38 } 39 40 #define MSTPSR1 0xE6150038 41 #define SMSTPCR1 0xE6150134 42 #define TMU0_MSTP125 (1 << 25) 43 44 #define MSTPSR7 0xE61501C4 45 #define SMSTPCR7 0xE615014C 46 #define SCIF0_MSTP719 (1 << 19) 47 48 #define MSTPSR8 0xE61509A0 49 #define SMSTPCR8 0xE6150990 50 #define ETHER_MSTP813 (1 << 13) 51 52 #define mstp_setbits(type, addr, saddr, set) \ 53 out_##type((saddr), in_##type(addr) | (set)) 54 #define mstp_clrbits(type, addr, saddr, clear) \ 55 out_##type((saddr), in_##type(addr) & ~(clear)) 56 #define mstp_setbits_le32(addr, saddr, set) \ 57 mstp_setbits(le32, addr, saddr, set) 58 #define mstp_clrbits_le32(addr, saddr, clear) \ 59 mstp_clrbits(le32, addr, saddr, clear) 60 61 int board_early_init_f(void) 62 { 63 /* TMU */ 64 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 65 66 /* SCIF0 */ 67 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719); 68 69 /* ETHER */ 70 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); 71 72 return 0; 73 } 74 75 void arch_preboot_os(void) 76 { 77 /* Disable TMU0 */ 78 mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); 79 } 80 81 int board_init(void) 82 { 83 /* adress of boot parameters */ 84 gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100; 85 86 /* Init PFC controller */ 87 r8a7794_pinmux_init(); 88 89 /* Ether Enable */ 90 gpio_request(GPIO_FN_ETH_CRS_DV, NULL); 91 gpio_request(GPIO_FN_ETH_RX_ER, NULL); 92 gpio_request(GPIO_FN_ETH_RXD0, NULL); 93 gpio_request(GPIO_FN_ETH_RXD1, NULL); 94 gpio_request(GPIO_FN_ETH_LINK, NULL); 95 gpio_request(GPIO_FN_ETH_REFCLK, NULL); 96 gpio_request(GPIO_FN_ETH_MDIO, NULL); 97 gpio_request(GPIO_FN_ETH_TXD1, NULL); 98 gpio_request(GPIO_FN_ETH_TX_EN, NULL); 99 gpio_request(GPIO_FN_ETH_MAGIC, NULL); 100 gpio_request(GPIO_FN_ETH_TXD0, NULL); 101 gpio_request(GPIO_FN_ETH_MDC, NULL); 102 gpio_request(GPIO_FN_IRQ8, NULL); 103 104 /* PHY reset */ 105 gpio_request(GPIO_GP_1_24, NULL); 106 gpio_direction_output(GPIO_GP_1_24, 0); 107 mdelay(20); 108 gpio_set_value(GPIO_GP_1_24, 1); 109 udelay(1); 110 111 return 0; 112 } 113 114 #define CXR24 0xEE7003C0 /* MAC address high register */ 115 #define CXR25 0xEE7003C8 /* MAC address low register */ 116 int board_eth_init(bd_t *bis) 117 { 118 #ifdef CONFIG_SH_ETHER 119 int ret = -ENODEV; 120 u32 val; 121 unsigned char enetaddr[6]; 122 123 ret = sh_eth_initialize(bis); 124 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) 125 return ret; 126 127 /* Set Mac address */ 128 val = enetaddr[0] << 24 | enetaddr[1] << 16 | 129 enetaddr[2] << 8 | enetaddr[3]; 130 writel(val, CXR24); 131 132 val = enetaddr[4] << 8 | enetaddr[5]; 133 writel(val, CXR25); 134 135 return ret; 136 #else 137 return 0; 138 #endif 139 } 140 141 int dram_init(void) 142 { 143 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; 144 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 145 146 return 0; 147 } 148 149 const struct rmobile_sysinfo sysinfo = { 150 CONFIG_RMOBILE_BOARD_STRING 151 }; 152 153 void dram_init_banksize(void) 154 { 155 gd->bd->bi_dram[0].start = ALT_SDRAM_BASE; 156 gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE; 157 } 158 159 int board_late_init(void) 160 { 161 return 0; 162 } 163 164 void reset_cpu(ulong addr) 165 { 166 u8 val; 167 168 i2c_set_bus_num(1); /* PowerIC connected to ch3 */ 169 i2c_init(400000, 0); 170 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 171 val |= 0x02; 172 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); 173 } 174