1 /* Copyright 2014 Freescale Semiconductor, Inc. 2 * 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 #include <common.h> 7 #include <asm/spl.h> 8 #include <malloc.h> 9 #include <ns16550.h> 10 #include <nand.h> 11 #include <mmc.h> 12 #include <fsl_esdhc.h> 13 #include <i2c.h> 14 #include "../common/qixis.h" 15 #include "t4240qds_qixis.h" 16 17 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000 18 19 DECLARE_GLOBAL_DATA_PTR; 20 21 phys_size_t get_effective_memsize(void) 22 { 23 return CONFIG_SYS_L3_SIZE; 24 } 25 26 unsigned long get_board_sys_clk(void) 27 { 28 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 29 30 switch (sysclk_conf & 0x0F) { 31 case QIXIS_SYSCLK_83: 32 return 83333333; 33 case QIXIS_SYSCLK_100: 34 return 100000000; 35 case QIXIS_SYSCLK_125: 36 return 125000000; 37 case QIXIS_SYSCLK_133: 38 return 133333333; 39 case QIXIS_SYSCLK_150: 40 return 150000000; 41 case QIXIS_SYSCLK_160: 42 return 160000000; 43 case QIXIS_SYSCLK_166: 44 return 166666666; 45 } 46 return 66666666; 47 } 48 49 unsigned long get_board_ddr_clk(void) 50 { 51 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 52 53 switch ((ddrclk_conf & 0x30) >> 4) { 54 case QIXIS_DDRCLK_100: 55 return 100000000; 56 case QIXIS_DDRCLK_125: 57 return 125000000; 58 case QIXIS_DDRCLK_133: 59 return 133333333; 60 } 61 return 66666666; 62 } 63 64 void board_init_f(ulong bootflag) 65 { 66 u32 plat_ratio, sys_clk, ccb_clk; 67 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; 68 #ifdef CONFIG_SPL_NAND_BOOT 69 u32 porsr1, pinctl; 70 #endif 71 72 #ifdef CONFIG_SPL_NAND_BOOT 73 porsr1 = in_be32(&gur->porsr1); 74 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000); 75 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl); 76 #endif 77 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ 78 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); 79 80 /* Update GD pointer */ 81 gd = (gd_t *)(CONFIG_SPL_GD_ADDR); 82 83 /* compiler optimization barrier needed for GCC >= 3.4 */ 84 __asm__ __volatile__("" : : : "memory"); 85 86 console_init_f(); 87 88 /* initialize selected port with appropriate baud rate */ 89 sys_clk = get_board_sys_clk(); 90 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; 91 ccb_clk = sys_clk * plat_ratio / 2; 92 93 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, 94 ccb_clk / 16 / CONFIG_BAUDRATE); 95 96 #ifdef CONFIG_SPL_MMC_BOOT 97 puts("\nSD boot...\n"); 98 #elif defined(CONFIG_SPL_NAND_BOOT) 99 puts("\nNAND boot...\n"); 100 #endif 101 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0); 102 } 103 104 void board_init_r(gd_t *gd, ulong dest_addr) 105 { 106 bd_t *bd; 107 108 bd = (bd_t *)(gd + sizeof(gd_t)); 109 memset(bd, 0, sizeof(bd_t)); 110 gd->bd = bd; 111 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR; 112 bd->bi_memsize = CONFIG_SYS_L3_SIZE; 113 114 probecpu(); 115 get_clocks(); 116 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, 117 CONFIG_SPL_RELOC_MALLOC_SIZE); 118 119 #ifdef CONFIG_SPL_NAND_BOOT 120 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 121 (uchar *)CONFIG_ENV_ADDR); 122 #endif 123 #ifdef CONFIG_SPL_MMC_BOOT 124 mmc_initialize(bd); 125 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, 126 (uchar *)CONFIG_ENV_ADDR); 127 #endif 128 129 gd->env_addr = (ulong)(CONFIG_ENV_ADDR); 130 gd->env_valid = 1; 131 132 i2c_init_all(); 133 134 gd->ram_size = initdram(0); 135 136 #ifdef CONFIG_SPL_MMC_BOOT 137 mmc_boot(); 138 #elif defined(CONFIG_SPL_NAND_BOOT) 139 nand_boot(); 140 #endif 141 } 142