1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright 2014 Freescale Semiconductor, Inc.
3 */
4
5 #include <common.h>
6 #include <console.h>
7 #include <environment.h>
8 #include <asm/spl.h>
9 #include <malloc.h>
10 #include <ns16550.h>
11 #include <nand.h>
12 #include <mmc.h>
13 #include <fsl_esdhc.h>
14 #include <i2c.h>
15 #include "../common/qixis.h"
16 #include "t4240qds_qixis.h"
17
18 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
19
20 DECLARE_GLOBAL_DATA_PTR;
21
get_effective_memsize(void)22 phys_size_t get_effective_memsize(void)
23 {
24 return CONFIG_SYS_L3_SIZE;
25 }
26
get_board_sys_clk(void)27 unsigned long get_board_sys_clk(void)
28 {
29 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
30
31 switch (sysclk_conf & 0x0F) {
32 case QIXIS_SYSCLK_83:
33 return 83333333;
34 case QIXIS_SYSCLK_100:
35 return 100000000;
36 case QIXIS_SYSCLK_125:
37 return 125000000;
38 case QIXIS_SYSCLK_133:
39 return 133333333;
40 case QIXIS_SYSCLK_150:
41 return 150000000;
42 case QIXIS_SYSCLK_160:
43 return 160000000;
44 case QIXIS_SYSCLK_166:
45 return 166666666;
46 }
47 return 66666666;
48 }
49
get_board_ddr_clk(void)50 unsigned long get_board_ddr_clk(void)
51 {
52 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
53
54 switch ((ddrclk_conf & 0x30) >> 4) {
55 case QIXIS_DDRCLK_100:
56 return 100000000;
57 case QIXIS_DDRCLK_125:
58 return 125000000;
59 case QIXIS_DDRCLK_133:
60 return 133333333;
61 }
62 return 66666666;
63 }
64
board_init_f(ulong bootflag)65 void board_init_f(ulong bootflag)
66 {
67 u32 plat_ratio, sys_clk, ccb_clk;
68 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
69 #ifdef CONFIG_SPL_NAND_BOOT
70 u32 porsr1, pinctl;
71 #endif
72
73 #ifdef CONFIG_SPL_NAND_BOOT
74 porsr1 = in_be32(&gur->porsr1);
75 pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
76 out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
77 #endif
78 /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
79 memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
80
81 /* Update GD pointer */
82 gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
83
84 /* compiler optimization barrier needed for GCC >= 3.4 */
85 __asm__ __volatile__("" : : : "memory");
86
87 console_init_f();
88
89 /* initialize selected port with appropriate baud rate */
90 sys_clk = get_board_sys_clk();
91 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
92 ccb_clk = sys_clk * plat_ratio / 2;
93
94 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
95 ccb_clk / 16 / CONFIG_BAUDRATE);
96
97 #ifdef CONFIG_SPL_MMC_BOOT
98 puts("\nSD boot...\n");
99 #elif defined(CONFIG_SPL_NAND_BOOT)
100 puts("\nNAND boot...\n");
101 #endif
102 relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
103 }
104
board_init_r(gd_t * gd,ulong dest_addr)105 void board_init_r(gd_t *gd, ulong dest_addr)
106 {
107 bd_t *bd;
108
109 bd = (bd_t *)(gd + sizeof(gd_t));
110 memset(bd, 0, sizeof(bd_t));
111 gd->bd = bd;
112 bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
113 bd->bi_memsize = CONFIG_SYS_L3_SIZE;
114
115 arch_cpu_init();
116 get_clocks();
117 mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
118 CONFIG_SPL_RELOC_MALLOC_SIZE);
119 gd->flags |= GD_FLG_FULL_MALLOC_INIT;
120
121 #ifdef CONFIG_SPL_NAND_BOOT
122 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
123 (uchar *)CONFIG_ENV_ADDR);
124 #endif
125 #ifdef CONFIG_SPL_MMC_BOOT
126 mmc_initialize(bd);
127 mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
128 (uchar *)CONFIG_ENV_ADDR);
129 #endif
130
131 gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
132 gd->env_valid = ENV_VALID;
133
134 i2c_init_all();
135
136 dram_init();
137
138 #ifdef CONFIG_SPL_MMC_BOOT
139 mmc_boot();
140 #elif defined(CONFIG_SPL_NAND_BOOT)
141 nand_boot();
142 #endif
143 }
144