1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <command.h> 9 #include <netdev.h> 10 #include <asm/mmu.h> 11 #include <asm/processor.h> 12 #include <asm/cache.h> 13 #include <asm/immap_85xx.h> 14 #include <asm/fsl_law.h> 15 #include <asm/fsl_ddr_sdram.h> 16 #include <asm/fsl_serdes.h> 17 #include <asm/fsl_portals.h> 18 #include <asm/fsl_liodn.h> 19 #include <malloc.h> 20 #include <fm_eth.h> 21 #include <fsl_mdio.h> 22 #include <miiphy.h> 23 #include <phy.h> 24 #include <asm/fsl_dtsec.h> 25 #include <asm/fsl_serdes.h> 26 #include "../common/qixis.h" 27 #include "../common/fman.h" 28 29 #include "t4240qds_qixis.h" 30 31 #define EMI_NONE 0xFFFFFFFF 32 #define EMI1_RGMII 0 33 #define EMI1_SLOT1 1 34 #define EMI1_SLOT2 2 35 #define EMI1_SLOT3 3 36 #define EMI1_SLOT4 4 37 #define EMI1_SLOT5 5 38 #define EMI1_SLOT7 7 39 #define EMI2 8 40 /* Slot6 and Slot8 do not have EMI connections */ 41 42 static int mdio_mux[NUM_FM_PORTS]; 43 44 static const char *mdio_names[] = { 45 "T4240QDS_MDIO0", 46 "T4240QDS_MDIO1", 47 "T4240QDS_MDIO2", 48 "T4240QDS_MDIO3", 49 "T4240QDS_MDIO4", 50 "T4240QDS_MDIO5", 51 "NULL", 52 "T4240QDS_MDIO7", 53 "T4240QDS_10GC", 54 }; 55 56 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2}; 57 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4}; 58 static u8 slot_qsgmii_phyaddr[5][4] = { 59 {0, 0, 0, 0},/* not used, to make index match slot No. */ 60 {0, 1, 2, 3}, 61 {4, 5, 6, 7}, 62 {8, 9, 0xa, 0xb}, 63 {0xc, 0xd, 0xe, 0xf}, 64 }; 65 static u8 qsgmiiphy_fix[NUM_FM_PORTS] = {0}; 66 67 static const char *t4240qds_mdio_name_for_muxval(u8 muxval) 68 { 69 return mdio_names[muxval]; 70 } 71 72 struct mii_dev *mii_dev_for_muxval(u8 muxval) 73 { 74 struct mii_dev *bus; 75 const char *name = t4240qds_mdio_name_for_muxval(muxval); 76 77 if (!name) { 78 printf("No bus for muxval %x\n", muxval); 79 return NULL; 80 } 81 82 bus = miiphy_get_dev_by_name(name); 83 84 if (!bus) { 85 printf("No bus by name %s\n", name); 86 return NULL; 87 } 88 89 return bus; 90 } 91 92 struct t4240qds_mdio { 93 u8 muxval; 94 struct mii_dev *realbus; 95 }; 96 97 static void t4240qds_mux_mdio(u8 muxval) 98 { 99 u8 brdcfg4; 100 if ((muxval < 6) || (muxval == 7)) { 101 brdcfg4 = QIXIS_READ(brdcfg[4]); 102 brdcfg4 &= ~BRDCFG4_EMISEL_MASK; 103 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); 104 QIXIS_WRITE(brdcfg[4], brdcfg4); 105 } 106 } 107 108 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad, 109 int regnum) 110 { 111 struct t4240qds_mdio *priv = bus->priv; 112 113 t4240qds_mux_mdio(priv->muxval); 114 115 return priv->realbus->read(priv->realbus, addr, devad, regnum); 116 } 117 118 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad, 119 int regnum, u16 value) 120 { 121 struct t4240qds_mdio *priv = bus->priv; 122 123 t4240qds_mux_mdio(priv->muxval); 124 125 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 126 } 127 128 static int t4240qds_mdio_reset(struct mii_dev *bus) 129 { 130 struct t4240qds_mdio *priv = bus->priv; 131 132 return priv->realbus->reset(priv->realbus); 133 } 134 135 static int t4240qds_mdio_init(char *realbusname, u8 muxval) 136 { 137 struct t4240qds_mdio *pmdio; 138 struct mii_dev *bus = mdio_alloc(); 139 140 if (!bus) { 141 printf("Failed to allocate T4240QDS MDIO bus\n"); 142 return -1; 143 } 144 145 pmdio = malloc(sizeof(*pmdio)); 146 if (!pmdio) { 147 printf("Failed to allocate T4240QDS private data\n"); 148 free(bus); 149 return -1; 150 } 151 152 bus->read = t4240qds_mdio_read; 153 bus->write = t4240qds_mdio_write; 154 bus->reset = t4240qds_mdio_reset; 155 sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval)); 156 157 pmdio->realbus = miiphy_get_dev_by_name(realbusname); 158 159 if (!pmdio->realbus) { 160 printf("No bus with name %s\n", realbusname); 161 free(bus); 162 free(pmdio); 163 return -1; 164 } 165 166 pmdio->muxval = muxval; 167 bus->priv = pmdio; 168 169 return mdio_register(bus); 170 } 171 172 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, 173 enum fm_port port, int offset) 174 { 175 int interface = fm_info_get_enet_if(port); 176 177 if (interface == PHY_INTERFACE_MODE_SGMII || 178 interface == PHY_INTERFACE_MODE_QSGMII) { 179 switch (port) { 180 case FM1_DTSEC1: 181 if (qsgmiiphy_fix[port]) 182 fdt_set_phy_handle(blob, prop, pa, 183 "sgmii_phy21"); 184 break; 185 case FM1_DTSEC2: 186 if (qsgmiiphy_fix[port]) 187 fdt_set_phy_handle(blob, prop, pa, 188 "sgmii_phy22"); 189 break; 190 case FM1_DTSEC3: 191 if (qsgmiiphy_fix[port]) 192 fdt_set_phy_handle(blob, prop, pa, 193 "sgmii_phy23"); 194 break; 195 case FM1_DTSEC4: 196 if (qsgmiiphy_fix[port]) 197 fdt_set_phy_handle(blob, prop, pa, 198 "sgmii_phy24"); 199 break; 200 case FM1_DTSEC6: 201 if (qsgmiiphy_fix[port]) 202 fdt_set_phy_handle(blob, prop, pa, 203 "sgmii_phy12"); 204 break; 205 case FM1_DTSEC9: 206 if (qsgmiiphy_fix[port]) 207 fdt_set_phy_handle(blob, prop, pa, 208 "sgmii_phy14"); 209 else 210 fdt_set_phy_handle(blob, prop, pa, 211 "phy_sgmii4"); 212 break; 213 case FM1_DTSEC10: 214 if (qsgmiiphy_fix[port]) 215 fdt_set_phy_handle(blob, prop, pa, 216 "sgmii_phy13"); 217 else 218 fdt_set_phy_handle(blob, prop, pa, 219 "phy_sgmii3"); 220 break; 221 case FM2_DTSEC1: 222 if (qsgmiiphy_fix[port]) 223 fdt_set_phy_handle(blob, prop, pa, 224 "sgmii_phy41"); 225 break; 226 case FM2_DTSEC2: 227 if (qsgmiiphy_fix[port]) 228 fdt_set_phy_handle(blob, prop, pa, 229 "sgmii_phy42"); 230 break; 231 case FM2_DTSEC3: 232 if (qsgmiiphy_fix[port]) 233 fdt_set_phy_handle(blob, prop, pa, 234 "sgmii_phy43"); 235 break; 236 case FM2_DTSEC4: 237 if (qsgmiiphy_fix[port]) 238 fdt_set_phy_handle(blob, prop, pa, 239 "sgmii_phy44"); 240 break; 241 case FM2_DTSEC6: 242 if (qsgmiiphy_fix[port]) 243 fdt_set_phy_handle(blob, prop, pa, 244 "sgmii_phy32"); 245 break; 246 case FM2_DTSEC9: 247 if (qsgmiiphy_fix[port]) 248 fdt_set_phy_handle(blob, prop, pa, 249 "sgmii_phy34"); 250 else 251 fdt_set_phy_handle(blob, prop, pa, 252 "phy_sgmii12"); 253 break; 254 case FM2_DTSEC10: 255 if (qsgmiiphy_fix[port]) 256 fdt_set_phy_handle(blob, prop, pa, 257 "sgmii_phy33"); 258 else 259 fdt_set_phy_handle(blob, prop, pa, 260 "phy_sgmii11"); 261 break; 262 default: 263 break; 264 } 265 } 266 } 267 268 void fdt_fixup_board_enet(void *fdt) 269 { 270 int i; 271 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 272 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 273 274 prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 275 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) { 276 switch (fm_info_get_enet_if(i)) { 277 case PHY_INTERFACE_MODE_SGMII: 278 case PHY_INTERFACE_MODE_QSGMII: 279 switch (mdio_mux[i]) { 280 case EMI1_SLOT1: 281 fdt_status_okay_by_alias(fdt, "emi1_slot1"); 282 break; 283 case EMI1_SLOT2: 284 fdt_status_okay_by_alias(fdt, "emi1_slot2"); 285 break; 286 case EMI1_SLOT3: 287 fdt_status_okay_by_alias(fdt, "emi1_slot3"); 288 break; 289 case EMI1_SLOT4: 290 fdt_status_okay_by_alias(fdt, "emi1_slot4"); 291 break; 292 default: 293 break; 294 } 295 break; 296 case PHY_INTERFACE_MODE_XGMII: 297 /* check if it's XFI interface for 10g */ 298 if ((prtcl2 == 56) || (prtcl2 == 57)) { 299 fdt_status_okay_by_alias(fdt, "emi2_xfislot3"); 300 break; 301 } 302 switch (i) { 303 case FM1_10GEC1: 304 fdt_status_okay_by_alias(fdt, "emi2_xauislot1"); 305 break; 306 case FM1_10GEC2: 307 fdt_status_okay_by_alias(fdt, "emi2_xauislot2"); 308 break; 309 case FM2_10GEC1: 310 fdt_status_okay_by_alias(fdt, "emi2_xauislot3"); 311 break; 312 case FM2_10GEC2: 313 fdt_status_okay_by_alias(fdt, "emi2_xauislot4"); 314 break; 315 default: 316 break; 317 } 318 break; 319 default: 320 break; 321 } 322 } 323 } 324 325 static void initialize_qsgmiiphy_fix(void) 326 { 327 int i; 328 unsigned short reg; 329 330 for (i = 1; i <= 4; i++) { 331 /* 332 * Try to read if a SGMII card is used, we do it slot by slot. 333 * if a SGMII PHY address is valid on a slot, then we mark 334 * all ports on the slot, then fix the PHY address for the 335 * marked port when doing dtb fixup. 336 */ 337 if (miiphy_read(mdio_names[i], 338 SGMII_CARD_PORT1_PHY_ADDR, MII_PHYSID2, ®) != 0) { 339 debug("Slot%d PHY ID register 2 read failed\n", i); 340 continue; 341 } 342 343 debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg); 344 345 if (reg == 0xFFFF) { 346 /* No physical device present at this address */ 347 continue; 348 } 349 350 switch (i) { 351 case 1: 352 qsgmiiphy_fix[FM1_DTSEC5] = 1; 353 qsgmiiphy_fix[FM1_DTSEC6] = 1; 354 qsgmiiphy_fix[FM1_DTSEC9] = 1; 355 qsgmiiphy_fix[FM1_DTSEC10] = 1; 356 slot_qsgmii_phyaddr[1][0] = SGMII_CARD_PORT1_PHY_ADDR; 357 slot_qsgmii_phyaddr[1][1] = SGMII_CARD_PORT2_PHY_ADDR; 358 slot_qsgmii_phyaddr[1][2] = SGMII_CARD_PORT3_PHY_ADDR; 359 slot_qsgmii_phyaddr[1][3] = SGMII_CARD_PORT4_PHY_ADDR; 360 break; 361 case 2: 362 qsgmiiphy_fix[FM1_DTSEC1] = 1; 363 qsgmiiphy_fix[FM1_DTSEC2] = 1; 364 qsgmiiphy_fix[FM1_DTSEC3] = 1; 365 qsgmiiphy_fix[FM1_DTSEC4] = 1; 366 slot_qsgmii_phyaddr[2][0] = SGMII_CARD_PORT1_PHY_ADDR; 367 slot_qsgmii_phyaddr[2][1] = SGMII_CARD_PORT2_PHY_ADDR; 368 slot_qsgmii_phyaddr[2][2] = SGMII_CARD_PORT3_PHY_ADDR; 369 slot_qsgmii_phyaddr[2][3] = SGMII_CARD_PORT4_PHY_ADDR; 370 break; 371 case 3: 372 qsgmiiphy_fix[FM2_DTSEC5] = 1; 373 qsgmiiphy_fix[FM2_DTSEC6] = 1; 374 qsgmiiphy_fix[FM2_DTSEC9] = 1; 375 qsgmiiphy_fix[FM2_DTSEC10] = 1; 376 slot_qsgmii_phyaddr[3][0] = SGMII_CARD_PORT1_PHY_ADDR; 377 slot_qsgmii_phyaddr[3][1] = SGMII_CARD_PORT2_PHY_ADDR; 378 slot_qsgmii_phyaddr[3][2] = SGMII_CARD_PORT3_PHY_ADDR; 379 slot_qsgmii_phyaddr[3][3] = SGMII_CARD_PORT4_PHY_ADDR; 380 break; 381 case 4: 382 qsgmiiphy_fix[FM2_DTSEC1] = 1; 383 qsgmiiphy_fix[FM2_DTSEC2] = 1; 384 qsgmiiphy_fix[FM2_DTSEC3] = 1; 385 qsgmiiphy_fix[FM2_DTSEC4] = 1; 386 slot_qsgmii_phyaddr[4][0] = SGMII_CARD_PORT1_PHY_ADDR; 387 slot_qsgmii_phyaddr[4][1] = SGMII_CARD_PORT2_PHY_ADDR; 388 slot_qsgmii_phyaddr[4][2] = SGMII_CARD_PORT3_PHY_ADDR; 389 slot_qsgmii_phyaddr[4][3] = SGMII_CARD_PORT4_PHY_ADDR; 390 break; 391 default: 392 break; 393 } 394 } 395 } 396 397 int board_eth_init(bd_t *bis) 398 { 399 #if defined(CONFIG_FMAN_ENET) 400 int i, idx, lane, slot, interface; 401 struct memac_mdio_info dtsec_mdio_info; 402 struct memac_mdio_info tgec_mdio_info; 403 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 404 u32 srds_prtcl_s1, srds_prtcl_s2; 405 406 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 407 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 408 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 409 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & 410 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 411 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 412 413 /* Initialize the mdio_mux array so we can recognize empty elements */ 414 for (i = 0; i < NUM_FM_PORTS; i++) 415 mdio_mux[i] = EMI_NONE; 416 417 dtsec_mdio_info.regs = 418 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; 419 420 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 421 422 /* Register the 1G MDIO bus */ 423 fm_memac_mdio_init(bis, &dtsec_mdio_info); 424 425 tgec_mdio_info.regs = 426 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; 427 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 428 429 /* Register the 10G MDIO bus */ 430 fm_memac_mdio_init(bis, &tgec_mdio_info); 431 432 /* Register the muxing front-ends to the MDIO buses */ 433 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); 434 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); 435 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); 436 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); 437 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); 438 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); 439 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); 440 t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); 441 442 initialize_qsgmiiphy_fix(); 443 444 switch (srds_prtcl_s1) { 445 case 1: 446 case 2: 447 case 4: 448 /* XAUI/HiGig in Slot1 and Slot2 */ 449 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); 450 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); 451 break; 452 case 28: 453 case 36: 454 /* SGMII in Slot1 and Slot2 */ 455 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); 456 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); 457 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); 458 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); 459 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); 460 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); 461 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { 462 fm_info_set_phy_address(FM1_DTSEC9, 463 slot_qsgmii_phyaddr[1][3]); 464 fm_info_set_phy_address(FM1_DTSEC10, 465 slot_qsgmii_phyaddr[1][2]); 466 } 467 break; 468 case 38: 469 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); 470 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); 471 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); 472 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); 473 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); 474 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); 475 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { 476 fm_info_set_phy_address(FM1_DTSEC9, 477 slot_qsgmii_phyaddr[1][2]); 478 fm_info_set_phy_address(FM1_DTSEC10, 479 slot_qsgmii_phyaddr[1][3]); 480 } 481 break; 482 case 40: 483 case 46: 484 case 48: 485 fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]); 486 fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]); 487 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { 488 fm_info_set_phy_address(FM1_DTSEC10, 489 slot_qsgmii_phyaddr[1][2]); 490 fm_info_set_phy_address(FM1_DTSEC9, 491 slot_qsgmii_phyaddr[1][3]); 492 } 493 fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]); 494 fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]); 495 fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]); 496 fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]); 497 break; 498 default: 499 puts("Invalid SerDes1 protocol for T4240QDS\n"); 500 break; 501 } 502 503 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 504 idx = i - FM1_DTSEC1; 505 interface = fm_info_get_enet_if(i); 506 switch (interface) { 507 case PHY_INTERFACE_MODE_SGMII: 508 case PHY_INTERFACE_MODE_QSGMII: 509 if (interface == PHY_INTERFACE_MODE_QSGMII) { 510 if (idx <= 3) 511 lane = serdes_get_first_lane(FSL_SRDS_1, 512 QSGMII_FM1_A); 513 else 514 lane = serdes_get_first_lane(FSL_SRDS_1, 515 QSGMII_FM1_B); 516 if (lane < 0) 517 break; 518 slot = lane_to_slot_fsm1[lane]; 519 debug("FM1@DTSEC%u expects QSGMII in slot %u\n", 520 idx + 1, slot); 521 } else { 522 lane = serdes_get_first_lane(FSL_SRDS_1, 523 SGMII_FM1_DTSEC1 + idx); 524 if (lane < 0) 525 break; 526 slot = lane_to_slot_fsm1[lane]; 527 debug("FM1@DTSEC%u expects SGMII in slot %u\n", 528 idx + 1, slot); 529 } 530 if (QIXIS_READ(present2) & (1 << (slot - 1))) 531 fm_disable_port(i); 532 switch (slot) { 533 case 1: 534 mdio_mux[i] = EMI1_SLOT1; 535 fm_info_set_mdio(i, 536 mii_dev_for_muxval(mdio_mux[i])); 537 break; 538 case 2: 539 mdio_mux[i] = EMI1_SLOT2; 540 fm_info_set_mdio(i, 541 mii_dev_for_muxval(mdio_mux[i])); 542 break; 543 }; 544 break; 545 case PHY_INTERFACE_MODE_RGMII: 546 /* FM1 DTSEC5 routes to RGMII with EC2 */ 547 debug("FM1@DTSEC%u is RGMII at address %u\n", 548 idx + 1, 2); 549 if (i == FM1_DTSEC5) 550 fm_info_set_phy_address(i, 2); 551 mdio_mux[i] = EMI1_RGMII; 552 fm_info_set_mdio(i, 553 mii_dev_for_muxval(mdio_mux[i])); 554 break; 555 default: 556 break; 557 } 558 } 559 560 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { 561 idx = i - FM1_10GEC1; 562 switch (fm_info_get_enet_if(i)) { 563 case PHY_INTERFACE_MODE_XGMII: 564 lane = serdes_get_first_lane(FSL_SRDS_1, 565 XAUI_FM1_MAC9 + idx); 566 if (lane < 0) 567 break; 568 slot = lane_to_slot_fsm1[lane]; 569 if (QIXIS_READ(present2) & (1 << (slot - 1))) 570 fm_disable_port(i); 571 mdio_mux[i] = EMI2; 572 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 573 break; 574 default: 575 break; 576 } 577 } 578 579 #if (CONFIG_SYS_NUM_FMAN == 2) 580 switch (srds_prtcl_s2) { 581 case 1: 582 case 2: 583 case 4: 584 /* XAUI/HiGig in Slot3 and Slot4 */ 585 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); 586 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); 587 break; 588 case 7: 589 case 13: 590 case 14: 591 case 16: 592 case 22: 593 case 23: 594 case 25: 595 case 26: 596 /* XAUI/HiGig in Slot3, SGMII in Slot4 */ 597 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); 598 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 599 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 600 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 601 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 602 break; 603 case 28: 604 case 36: 605 /* SGMII in Slot3 and Slot4 */ 606 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 607 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 608 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 609 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 610 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); 611 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); 612 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); 613 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); 614 break; 615 case 38: 616 /* QSGMII in Slot3 and Slot4 */ 617 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 618 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 619 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 620 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 621 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); 622 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); 623 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]); 624 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]); 625 break; 626 case 40: 627 case 46: 628 case 48: 629 /* SGMII in Slot3 */ 630 fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]); 631 fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]); 632 fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]); 633 fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]); 634 /* QSGMII in Slot4 */ 635 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 636 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 637 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 638 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 639 break; 640 case 50: 641 case 52: 642 case 54: 643 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); 644 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 645 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 646 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 647 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 648 break; 649 case 56: 650 case 57: 651 /* XFI in Slot3, SGMII in Slot4 */ 652 fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]); 653 fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]); 654 fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]); 655 fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]); 656 break; 657 default: 658 puts("Invalid SerDes2 protocol for T4240QDS\n"); 659 break; 660 } 661 662 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { 663 idx = i - FM2_DTSEC1; 664 interface = fm_info_get_enet_if(i); 665 switch (interface) { 666 case PHY_INTERFACE_MODE_SGMII: 667 case PHY_INTERFACE_MODE_QSGMII: 668 if (interface == PHY_INTERFACE_MODE_QSGMII) { 669 if (idx <= 3) 670 lane = serdes_get_first_lane(FSL_SRDS_2, 671 QSGMII_FM2_A); 672 else 673 lane = serdes_get_first_lane(FSL_SRDS_2, 674 QSGMII_FM2_B); 675 if (lane < 0) 676 break; 677 slot = lane_to_slot_fsm2[lane]; 678 debug("FM2@DTSEC%u expects QSGMII in slot %u\n", 679 idx + 1, slot); 680 } else { 681 lane = serdes_get_first_lane(FSL_SRDS_2, 682 SGMII_FM2_DTSEC1 + idx); 683 if (lane < 0) 684 break; 685 slot = lane_to_slot_fsm2[lane]; 686 debug("FM2@DTSEC%u expects SGMII in slot %u\n", 687 idx + 1, slot); 688 } 689 if (QIXIS_READ(present2) & (1 << (slot - 1))) 690 fm_disable_port(i); 691 switch (slot) { 692 case 3: 693 mdio_mux[i] = EMI1_SLOT3; 694 fm_info_set_mdio(i, 695 mii_dev_for_muxval(mdio_mux[i])); 696 break; 697 case 4: 698 mdio_mux[i] = EMI1_SLOT4; 699 fm_info_set_mdio(i, 700 mii_dev_for_muxval(mdio_mux[i])); 701 break; 702 }; 703 break; 704 case PHY_INTERFACE_MODE_RGMII: 705 /* 706 * If DTSEC5 is RGMII, then it's routed via via EC1 to 707 * the first on-board RGMII port. If DTSEC6 is RGMII, 708 * then it's routed via via EC2 to the second on-board 709 * RGMII port. 710 */ 711 debug("FM2@DTSEC%u is RGMII at address %u\n", 712 idx + 1, i == FM2_DTSEC5 ? 1 : 2); 713 fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2); 714 mdio_mux[i] = EMI1_RGMII; 715 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 716 break; 717 default: 718 break; 719 } 720 } 721 722 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { 723 idx = i - FM2_10GEC1; 724 switch (fm_info_get_enet_if(i)) { 725 case PHY_INTERFACE_MODE_XGMII: 726 lane = serdes_get_first_lane(FSL_SRDS_2, 727 XAUI_FM2_MAC9 + idx); 728 if (lane < 0) 729 break; 730 slot = lane_to_slot_fsm2[lane]; 731 if (QIXIS_READ(present2) & (1 << (slot - 1))) 732 fm_disable_port(i); 733 mdio_mux[i] = EMI2; 734 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 735 break; 736 default: 737 break; 738 } 739 } 740 #endif /* CONFIG_SYS_NUM_FMAN */ 741 742 cpu_eth_init(bis); 743 #endif /* CONFIG_FMAN_ENET */ 744 745 return pci_eth_init(bis); 746 } 747