1 /* 2 * Copyright 2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #include <common.h> 24 #include <command.h> 25 #include <netdev.h> 26 #include <asm/mmu.h> 27 #include <asm/processor.h> 28 #include <asm/cache.h> 29 #include <asm/immap_85xx.h> 30 #include <asm/fsl_law.h> 31 #include <asm/fsl_ddr_sdram.h> 32 #include <asm/fsl_serdes.h> 33 #include <asm/fsl_portals.h> 34 #include <asm/fsl_liodn.h> 35 #include <malloc.h> 36 #include <fm_eth.h> 37 #include <fsl_mdio.h> 38 #include <miiphy.h> 39 #include <phy.h> 40 #include <asm/fsl_dtsec.h> 41 #include <asm/fsl_serdes.h> 42 #include "../common/qixis.h" 43 #include "../common/fman.h" 44 45 #include "t4240qds_qixis.h" 46 47 #define EMI_NONE 0xFFFFFFFF 48 #define EMI1_RGMII 0 49 #define EMI1_SLOT1 1 50 #define EMI1_SLOT2 2 51 #define EMI1_SLOT3 3 52 #define EMI1_SLOT4 4 53 #define EMI1_SLOT5 5 54 #define EMI1_SLOT7 7 55 #define EMI2 8 /* tmp, FIXME */ 56 /* Slot6 and Slot8 do not have EMI connections */ 57 58 static int mdio_mux[NUM_FM_PORTS]; 59 60 static const char *mdio_names[] = { 61 "T4240QDS_MDIO0", 62 "T4240QDS_MDIO1", 63 "T4240QDS_MDIO2", 64 "T4240QDS_MDIO3", 65 "T4240QDS_MDIO4", 66 "T4240QDS_MDIO5", 67 "NULL", 68 "T4240QDS_MDIO7", 69 "T4240QDS_10GC", 70 }; 71 72 static u8 lane_to_slot_fsm1[] = {1, 1, 1, 1, 2, 2, 2, 2}; 73 static u8 lane_to_slot_fsm2[] = {3, 3, 3, 3, 4, 4, 4, 4}; 74 75 static const char *t4240qds_mdio_name_for_muxval(u8 muxval) 76 { 77 return mdio_names[muxval]; 78 } 79 80 struct mii_dev *mii_dev_for_muxval(u8 muxval) 81 { 82 struct mii_dev *bus; 83 const char *name = t4240qds_mdio_name_for_muxval(muxval); 84 85 if (!name) { 86 printf("No bus for muxval %x\n", muxval); 87 return NULL; 88 } 89 90 bus = miiphy_get_dev_by_name(name); 91 92 if (!bus) { 93 printf("No bus by name %s\n", name); 94 return NULL; 95 } 96 97 return bus; 98 } 99 100 struct t4240qds_mdio { 101 u8 muxval; 102 struct mii_dev *realbus; 103 }; 104 105 static void t4240qds_mux_mdio(u8 muxval) 106 { 107 u8 brdcfg4; 108 if ((muxval < 6) || (muxval == 7)) { 109 brdcfg4 = QIXIS_READ(brdcfg[4]); 110 brdcfg4 &= ~BRDCFG4_EMISEL_MASK; 111 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); 112 QIXIS_WRITE(brdcfg[4], brdcfg4); 113 } 114 } 115 116 static int t4240qds_mdio_read(struct mii_dev *bus, int addr, int devad, 117 int regnum) 118 { 119 struct t4240qds_mdio *priv = bus->priv; 120 121 t4240qds_mux_mdio(priv->muxval); 122 123 return priv->realbus->read(priv->realbus, addr, devad, regnum); 124 } 125 126 static int t4240qds_mdio_write(struct mii_dev *bus, int addr, int devad, 127 int regnum, u16 value) 128 { 129 struct t4240qds_mdio *priv = bus->priv; 130 131 t4240qds_mux_mdio(priv->muxval); 132 133 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 134 } 135 136 static int t4240qds_mdio_reset(struct mii_dev *bus) 137 { 138 struct t4240qds_mdio *priv = bus->priv; 139 140 return priv->realbus->reset(priv->realbus); 141 } 142 143 static int t4240qds_mdio_init(char *realbusname, u8 muxval) 144 { 145 struct t4240qds_mdio *pmdio; 146 struct mii_dev *bus = mdio_alloc(); 147 148 if (!bus) { 149 printf("Failed to allocate T4240QDS MDIO bus\n"); 150 return -1; 151 } 152 153 pmdio = malloc(sizeof(*pmdio)); 154 if (!pmdio) { 155 printf("Failed to allocate T4240QDS private data\n"); 156 free(bus); 157 return -1; 158 } 159 160 bus->read = t4240qds_mdio_read; 161 bus->write = t4240qds_mdio_write; 162 bus->reset = t4240qds_mdio_reset; 163 sprintf(bus->name, t4240qds_mdio_name_for_muxval(muxval)); 164 165 pmdio->realbus = miiphy_get_dev_by_name(realbusname); 166 167 if (!pmdio->realbus) { 168 printf("No bus with name %s\n", realbusname); 169 free(bus); 170 free(pmdio); 171 return -1; 172 } 173 174 pmdio->muxval = muxval; 175 bus->priv = pmdio; 176 177 return mdio_register(bus); 178 } 179 180 void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, 181 enum fm_port port, int offset) 182 { 183 if (mdio_mux[port] == EMI1_RGMII) 184 fdt_set_phy_handle(blob, prop, pa, "phy_rgmii"); 185 186 /* TODO: will do with dts */ 187 } 188 189 void fdt_fixup_board_enet(void *fdt) 190 { 191 /* TODO: will do with dts */ 192 } 193 194 int board_eth_init(bd_t *bis) 195 { 196 #if defined(CONFIG_FMAN_ENET) 197 int i; 198 struct memac_mdio_info dtsec_mdio_info; 199 struct memac_mdio_info tgec_mdio_info; 200 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 201 u32 srds_prtcl_s1, srds_prtcl_s2; 202 203 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & 204 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 205 srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 206 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & 207 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 208 srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 209 210 /* Initialize the mdio_mux array so we can recognize empty elements */ 211 for (i = 0; i < NUM_FM_PORTS; i++) 212 mdio_mux[i] = EMI_NONE; 213 214 dtsec_mdio_info.regs = 215 (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; 216 217 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 218 219 /* Register the 1G MDIO bus */ 220 fm_memac_mdio_init(bis, &dtsec_mdio_info); 221 222 tgec_mdio_info.regs = 223 (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; 224 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 225 226 /* Register the 10G MDIO bus */ 227 fm_memac_mdio_init(bis, &tgec_mdio_info); 228 229 /* Register the muxing front-ends to the MDIO buses */ 230 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII); 231 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); 232 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); 233 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); 234 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); 235 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); 236 t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); 237 t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); 238 239 240 switch (srds_prtcl_s1) { 241 case 1: 242 case 2: 243 case 4: 244 /* XAUI/HiGig in Slot1 and Slot2 */ 245 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); 246 fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); 247 break; 248 case 28: 249 case 36: 250 /* SGMII in Slot1 and Slot2 */ 251 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); 252 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); 253 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); 254 fm_info_set_phy_address(FM1_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); 255 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); 256 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 257 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { 258 fm_info_set_phy_address(FM1_DTSEC9, 259 SGMII_CARD_PORT4_PHY_ADDR); 260 fm_info_set_phy_address(FM1_DTSEC10, 261 SGMII_CARD_PORT3_PHY_ADDR); 262 } 263 break; 264 case 38: 265 fm_info_set_phy_address(FM1_DTSEC5, QSGMII_CARD_PHY_ADDR); 266 fm_info_set_phy_address(FM1_DTSEC6, QSGMII_CARD_PHY_ADDR); 267 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { 268 fm_info_set_phy_address(FM1_DTSEC9, 269 QSGMII_CARD_PHY_ADDR); 270 fm_info_set_phy_address(FM1_DTSEC10, 271 QSGMII_CARD_PHY_ADDR); 272 } 273 break; 274 case 40: 275 case 46: 276 case 48: 277 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); 278 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 279 if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) { 280 fm_info_set_phy_address(FM1_DTSEC10, 281 SGMII_CARD_PORT3_PHY_ADDR); 282 fm_info_set_phy_address(FM1_DTSEC9, 283 SGMII_CARD_PORT4_PHY_ADDR); 284 } 285 fm_info_set_phy_address(FM1_DTSEC1, QSGMII_CARD_PHY_ADDR); 286 fm_info_set_phy_address(FM1_DTSEC2, QSGMII_CARD_PHY_ADDR); 287 fm_info_set_phy_address(FM1_DTSEC3, QSGMII_CARD_PHY_ADDR); 288 fm_info_set_phy_address(FM1_DTSEC4, QSGMII_CARD_PHY_ADDR); 289 break; 290 default: 291 puts("Invalid SerDes1 protocol for T4240QDS\n"); 292 break; 293 } 294 295 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 296 int idx = i - FM1_DTSEC1, lane, slot; 297 switch (fm_info_get_enet_if(i)) { 298 case PHY_INTERFACE_MODE_SGMII: 299 lane = serdes_get_first_lane(FSL_SRDS_1, 300 SGMII_FM1_DTSEC1 + idx); 301 if (lane < 0) 302 break; 303 slot = lane_to_slot_fsm1[lane]; 304 debug("FM1@DTSEC%u expects SGMII in slot %u\n", 305 idx + 1, slot); 306 if (QIXIS_READ(present2) & (1 << (slot - 1))) 307 fm_disable_port(i); 308 switch (slot) { 309 case 1: 310 mdio_mux[i] = EMI1_SLOT1; 311 fm_info_set_mdio(i, 312 mii_dev_for_muxval(mdio_mux[i])); 313 break; 314 case 2: 315 mdio_mux[i] = EMI1_SLOT2; 316 fm_info_set_mdio(i, 317 mii_dev_for_muxval(mdio_mux[i])); 318 break; 319 }; 320 break; 321 case PHY_INTERFACE_MODE_RGMII: 322 /* FM1 DTSEC5 routes to RGMII with EC2 */ 323 debug("FM1@DTSEC%u is RGMII at address %u\n", 324 idx + 1, 2); 325 if (i == FM1_DTSEC5) 326 fm_info_set_phy_address(i, 2); 327 mdio_mux[i] = EMI1_RGMII; 328 fm_info_set_mdio(i, 329 mii_dev_for_muxval(mdio_mux[i])); 330 break; 331 default: 332 break; 333 } 334 } 335 336 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { 337 switch (fm_info_get_enet_if(i)) { 338 case PHY_INTERFACE_MODE_XGMII: 339 mdio_mux[i] = EMI2; 340 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 341 break; 342 default: 343 break; 344 } 345 } 346 347 348 #if (CONFIG_SYS_NUM_FMAN == 2) 349 switch (srds_prtcl_s2) { 350 case 1: 351 case 2: 352 case 4: 353 /* XAUI/HiGig in Slot3 and Slot4 */ 354 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); 355 fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR); 356 break; 357 case 7: 358 case 13: 359 case 14: 360 case 16: 361 case 22: 362 case 23: 363 case 25: 364 case 26: 365 /* XAUI/HiGig in Slot3, SGMII in Slot4 */ 366 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); 367 fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); 368 fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); 369 fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); 370 fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); 371 break; 372 case 28: 373 case 36: 374 /* SGMII in Slot3 and Slot4 */ 375 fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); 376 fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); 377 fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); 378 fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); 379 fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); 380 fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 381 fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR); 382 fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); 383 break; 384 case 38: 385 /* QSGMII in Slot3 and Slot4 */ 386 fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); 387 fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); 388 fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); 389 fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); 390 fm_info_set_phy_address(FM2_DTSEC5, QSGMII_CARD_PHY_ADDR); 391 fm_info_set_phy_address(FM2_DTSEC6, QSGMII_CARD_PHY_ADDR); 392 fm_info_set_phy_address(FM2_DTSEC9, QSGMII_CARD_PHY_ADDR); 393 fm_info_set_phy_address(FM2_DTSEC10, QSGMII_CARD_PHY_ADDR); 394 break; 395 case 40: 396 case 46: 397 case 48: 398 /* SGMII in Slot3 */ 399 fm_info_set_phy_address(FM2_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); 400 fm_info_set_phy_address(FM2_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 401 fm_info_set_phy_address(FM2_DTSEC9, SGMII_CARD_PORT4_PHY_ADDR); 402 fm_info_set_phy_address(FM2_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); 403 /* QSGMII in Slot4 */ 404 fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); 405 fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); 406 fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); 407 fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); 408 break; 409 case 50: 410 case 52: 411 case 54: 412 fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR); 413 fm_info_set_phy_address(FM2_DTSEC1, QSGMII_CARD_PHY_ADDR); 414 fm_info_set_phy_address(FM2_DTSEC2, QSGMII_CARD_PHY_ADDR); 415 fm_info_set_phy_address(FM2_DTSEC3, QSGMII_CARD_PHY_ADDR); 416 fm_info_set_phy_address(FM2_DTSEC4, QSGMII_CARD_PHY_ADDR); 417 break; 418 case 56: 419 case 57: 420 /* XFI in Slot3, SGMII in Slot4 */ 421 fm_info_set_phy_address(FM1_10GEC1, XFI_CARD_PORT1_PHY_ADDR); 422 fm_info_set_phy_address(FM1_10GEC2, XFI_CARD_PORT2_PHY_ADDR); 423 fm_info_set_phy_address(FM2_10GEC2, XFI_CARD_PORT3_PHY_ADDR); 424 fm_info_set_phy_address(FM2_10GEC1, XFI_CARD_PORT4_PHY_ADDR); 425 fm_info_set_phy_address(FM2_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); 426 fm_info_set_phy_address(FM2_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); 427 fm_info_set_phy_address(FM2_DTSEC3, SGMII_CARD_PORT3_PHY_ADDR); 428 fm_info_set_phy_address(FM2_DTSEC4, SGMII_CARD_PORT4_PHY_ADDR); 429 break; 430 default: 431 puts("Invalid SerDes2 protocol for T4240QDS\n"); 432 break; 433 } 434 435 for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { 436 int idx = i - FM2_DTSEC1, lane, slot; 437 switch (fm_info_get_enet_if(i)) { 438 case PHY_INTERFACE_MODE_SGMII: 439 lane = serdes_get_first_lane(FSL_SRDS_2, 440 SGMII_FM2_DTSEC1 + idx); 441 if (lane < 0) 442 break; 443 slot = lane_to_slot_fsm2[lane]; 444 debug("FM2@DTSEC%u expects SGMII in slot %u\n", 445 idx + 1, slot); 446 if (QIXIS_READ(present2) & (1 << (slot - 1))) 447 fm_disable_port(i); 448 switch (slot) { 449 case 3: 450 mdio_mux[i] = EMI1_SLOT3; 451 fm_info_set_mdio(i, 452 mii_dev_for_muxval(mdio_mux[i])); 453 break; 454 case 4: 455 mdio_mux[i] = EMI1_SLOT4; 456 fm_info_set_mdio(i, 457 mii_dev_for_muxval(mdio_mux[i])); 458 break; 459 }; 460 break; 461 case PHY_INTERFACE_MODE_RGMII: 462 /* 463 * If DTSEC5 is RGMII, then it's routed via via EC1 to 464 * the first on-board RGMII port. If DTSEC6 is RGMII, 465 * then it's routed via via EC2 to the second on-board 466 * RGMII port. 467 */ 468 debug("FM2@DTSEC%u is RGMII at address %u\n", 469 idx + 1, i == FM2_DTSEC5 ? 1 : 2); 470 fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2); 471 mdio_mux[i] = EMI1_RGMII; 472 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 473 break; 474 default: 475 break; 476 } 477 } 478 479 for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { 480 switch (fm_info_get_enet_if(i)) { 481 case PHY_INTERFACE_MODE_XGMII: 482 mdio_mux[i] = EMI2; 483 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 484 break; 485 default: 486 break; 487 } 488 } 489 #endif /* CONFIG_SYS_NUM_FMAN */ 490 491 cpu_eth_init(bis); 492 #endif /* CONFIG_FMAN_ENET */ 493 494 return pci_eth_init(bis); 495 } 496