1 /* 2 * (C) Copyright 2015, Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/io.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/siul.h> 10 #include <asm/arch/lpddr2.h> 11 #include <asm/arch/mmdc.h> 12 13 volatile int mscr_offset_ck0; 14 15 void lpddr2_config_iomux(uint8_t module) 16 { 17 int i; 18 19 switch (module) { 20 case DDR0: 21 mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0); 22 writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0)); 23 24 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0)); 25 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1)); 26 27 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0)); 28 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1)); 29 30 for (i = _DDR0_DM0; i <= _DDR0_DM3; i++) 31 writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); 32 33 for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++) 34 writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); 35 36 for (i = _DDR0_A0; i <= _DDR0_A9; i++) 37 writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); 38 39 for (i = _DDR0_D0; i <= _DDR0_D31; i++) 40 writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); 41 break; 42 case DDR1: 43 writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0)); 44 45 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0)); 46 writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1)); 47 48 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0)); 49 writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1)); 50 51 for (i = _DDR1_DM0; i <= _DDR1_DM3; i++) 52 writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i)); 53 54 for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++) 55 writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i)); 56 57 for (i = _DDR1_A0; i <= _DDR1_A9; i++) 58 writel(LPDDR2_An_PAD, SIUL2_MSCRn(i)); 59 60 for (i = _DDR1_D0; i <= _DDR1_D31; i++) 61 writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i)); 62 break; 63 } 64 } 65 66 void config_mmdc(uint8_t module) 67 { 68 unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR; 69 70 writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR); 71 72 writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0); 73 writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1); 74 writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2); 75 writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP); 76 writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC); 77 writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC); 78 writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR); 79 writel(_MDCTL, mmdc_addr + MMDC_MDCTL); 80 81 writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0); 82 83 while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) { 84 } 85 86 writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR); 87 88 /* Perform ZQ calibration */ 89 writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL); 90 writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL); 91 while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) { 92 } 93 94 /* Enable MMDC with CS0 */ 95 writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL); 96 97 /* Complete the initialization sequence as defined by JEDEC */ 98 writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR); 99 writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR); 100 writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR); 101 writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR); 102 103 /* Set the amount of DRAM */ 104 /* Set DQS settings based on board type */ 105 106 switch (module) { 107 case MMDC0: 108 writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP); 109 writel(MMDC_MPRDDLCTL_MODULE0_VALUE, 110 mmdc_addr + MMDC_MPRDDLCTL); 111 writel(MMDC_MPWRDLCTL_MODULE0_VALUE, 112 mmdc_addr + MMDC_MPWRDLCTL); 113 writel(MMDC_MPDGCTRL0_MODULE0_VALUE, 114 mmdc_addr + MMDC_MPDGCTRL0); 115 writel(MMDC_MPDGCTRL1_MODULE0_VALUE, 116 mmdc_addr + MMDC_MPDGCTRL1); 117 break; 118 case MMDC1: 119 writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP); 120 writel(MMDC_MPRDDLCTL_MODULE1_VALUE, 121 mmdc_addr + MMDC_MPRDDLCTL); 122 writel(MMDC_MPWRDLCTL_MODULE1_VALUE, 123 mmdc_addr + MMDC_MPWRDLCTL); 124 writel(MMDC_MPDGCTRL0_MODULE1_VALUE, 125 mmdc_addr + MMDC_MPDGCTRL0); 126 writel(MMDC_MPDGCTRL1_MODULE1_VALUE, 127 mmdc_addr + MMDC_MPDGCTRL1); 128 break; 129 } 130 131 writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD); 132 writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC); 133 writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF); 134 writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL); 135 writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR); 136 137 } 138