1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2015, Freescale Semiconductor, Inc.
4  */
5 
6 #include <asm/io.h>
7 #include <asm/arch/imx-regs.h>
8 #include <asm/arch/siul.h>
9 #include <asm/arch/lpddr2.h>
10 #include <asm/arch/mmdc.h>
11 
12 volatile int mscr_offset_ck0;
13 
lpddr2_config_iomux(uint8_t module)14 void lpddr2_config_iomux(uint8_t module)
15 {
16 	int i;
17 
18 	switch (module) {
19 	case DDR0:
20 		mscr_offset_ck0 = SIUL2_MSCRn(_DDR0_CKE0);
21 		writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR0_CLK0));
22 
23 		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE0));
24 		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR0_CKE1));
25 
26 		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B0));
27 		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR0_CS_B1));
28 
29 		for (i = _DDR0_DM0; i <= _DDR0_DM3; i++)
30 			writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
31 
32 		for (i = _DDR0_DQS0; i <= _DDR0_DQS3; i++)
33 			writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
34 
35 		for (i = _DDR0_A0; i <= _DDR0_A9; i++)
36 			writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
37 
38 		for (i = _DDR0_D0; i <= _DDR0_D31; i++)
39 			writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
40 		break;
41 	case DDR1:
42 		writel(LPDDR2_CLK0_PAD, SIUL2_MSCRn(_DDR1_CLK0));
43 
44 		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE0));
45 		writel(LPDDR2_CKEn_PAD, SIUL2_MSCRn(_DDR1_CKE1));
46 
47 		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B0));
48 		writel(LPDDR2_CS_Bn_PAD, SIUL2_MSCRn(_DDR1_CS_B1));
49 
50 		for (i = _DDR1_DM0; i <= _DDR1_DM3; i++)
51 			writel(LPDDR2_DMn_PAD, SIUL2_MSCRn(i));
52 
53 		for (i = _DDR1_DQS0; i <= _DDR1_DQS3; i++)
54 			writel(LPDDR2_DQSn_PAD, SIUL2_MSCRn(i));
55 
56 		for (i = _DDR1_A0; i <= _DDR1_A9; i++)
57 			writel(LPDDR2_An_PAD, SIUL2_MSCRn(i));
58 
59 		for (i = _DDR1_D0; i <= _DDR1_D31; i++)
60 			writel(LPDDR2_Dn_PAD, SIUL2_MSCRn(i));
61 		break;
62 	}
63 }
64 
config_mmdc(uint8_t module)65 void config_mmdc(uint8_t module)
66 {
67 	unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR;
68 
69 	writel(MMDC_MDSCR_CFG_VALUE, mmdc_addr + MMDC_MDSCR);
70 
71 	writel(MMDC_MDCFG0_VALUE, mmdc_addr + MMDC_MDCFG0);
72 	writel(MMDC_MDCFG1_VALUE, mmdc_addr + MMDC_MDCFG1);
73 	writel(MMDC_MDCFG2_VALUE, mmdc_addr + MMDC_MDCFG2);
74 	writel(MMDC_MDCFG3LP_VALUE, mmdc_addr + MMDC_MDCFG3LP);
75 	writel(MMDC_MDOTC_VALUE, mmdc_addr + MMDC_MDOTC);
76 	writel(MMDC_MDMISC_VALUE, mmdc_addr + MMDC_MDMISC);
77 	writel(MMDC_MDOR_VALUE, mmdc_addr + MMDC_MDOR);
78 	writel(_MDCTL, mmdc_addr + MMDC_MDCTL);
79 
80 	writel(MMDC_MPMUR0_VALUE, mmdc_addr + MMDC_MPMUR0);
81 
82 	while (readl(mmdc_addr + MMDC_MPMUR0) & MMDC_MPMUR0_FRC_MSR) {
83 	}
84 
85 	writel(MMDC_MDSCR_RST_VALUE, mmdc_addr + MMDC_MDSCR);
86 
87 	/* Perform ZQ calibration */
88 	writel(MMDC_MPZQLP2CTL_VALUE, mmdc_addr + MMDC_MPZQLP2CTL);
89 	writel(MMDC_MPZQHWCTRL_VALUE, mmdc_addr + MMDC_MPZQHWCTRL);
90 	while (readl(mmdc_addr + MMDC_MPZQHWCTRL) & MMDC_MPZQHWCTRL_ZQ_HW_FOR) {
91 	}
92 
93 	/* Enable MMDC with CS0 */
94 	writel(_MDCTL + 0x80000000, mmdc_addr + MMDC_MDCTL);
95 
96 	/* Complete the initialization sequence as defined by JEDEC */
97 	writel(MMDC_MDSCR_MR1_VALUE, mmdc_addr + MMDC_MDSCR);
98 	writel(MMDC_MDSCR_MR2_VALUE, mmdc_addr + MMDC_MDSCR);
99 	writel(MMDC_MDSCR_MR3_VALUE, mmdc_addr + MMDC_MDSCR);
100 	writel(MMDC_MDSCR_MR10_VALUE, mmdc_addr + MMDC_MDSCR);
101 
102 	/* Set the amount of DRAM */
103 	/* Set DQS settings based on board type */
104 
105 	switch (module) {
106 	case MMDC0:
107 		writel(MMDC_MDASP_MODULE0_VALUE, mmdc_addr + MMDC_MDASP);
108 		writel(MMDC_MPRDDLCTL_MODULE0_VALUE,
109 		       mmdc_addr + MMDC_MPRDDLCTL);
110 		writel(MMDC_MPWRDLCTL_MODULE0_VALUE,
111 		       mmdc_addr + MMDC_MPWRDLCTL);
112 		writel(MMDC_MPDGCTRL0_MODULE0_VALUE,
113 		       mmdc_addr + MMDC_MPDGCTRL0);
114 		writel(MMDC_MPDGCTRL1_MODULE0_VALUE,
115 		       mmdc_addr + MMDC_MPDGCTRL1);
116 		break;
117 	case MMDC1:
118 		writel(MMDC_MDASP_MODULE1_VALUE, mmdc_addr + MMDC_MDASP);
119 		writel(MMDC_MPRDDLCTL_MODULE1_VALUE,
120 		       mmdc_addr + MMDC_MPRDDLCTL);
121 		writel(MMDC_MPWRDLCTL_MODULE1_VALUE,
122 		       mmdc_addr + MMDC_MPWRDLCTL);
123 		writel(MMDC_MPDGCTRL0_MODULE1_VALUE,
124 		       mmdc_addr + MMDC_MPDGCTRL0);
125 		writel(MMDC_MPDGCTRL1_MODULE1_VALUE,
126 		       mmdc_addr + MMDC_MPDGCTRL1);
127 		break;
128 	}
129 
130 	writel(MMDC_MDRWD_VALUE, mmdc_addr + MMDC_MDRWD);
131 	writel(MMDC_MDPDC_VALUE, mmdc_addr + MMDC_MDPDC);
132 	writel(MMDC_MDREF_VALUE, mmdc_addr + MMDC_MDREF);
133 	writel(MMDC_MPODTCTRL_VALUE, mmdc_addr + MMDC_MPODTCTRL);
134 	writel(MMDC_MDSCR_DEASSERT_VALUE, mmdc_addr + MMDC_MDSCR);
135 
136 }
137