1 /*
2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
3  *
4  * See file CREDITS for list of people who contributed to this
5  * project.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License as
9  * published by the Free Software Foundation; either version 2 of
10  * the License, or (at your option) any later version.
11  */
12 
13 #include <common.h>
14 #include <mpc83xx.h>
15 #include <pci.h>
16 #include <asm/io.h>
17 
18 #if defined(CONFIG_PCI)
19 static struct pci_region pci_regions[] = {
20 	{
21 		bus_start: CONFIG_SYS_PCI_MEM_BASE,
22 		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
23 		size: CONFIG_SYS_PCI_MEM_SIZE,
24 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
25 	},
26 	{
27 		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
28 		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
29 		size: CONFIG_SYS_PCI_MMIO_SIZE,
30 		flags: PCI_REGION_MEM
31 	},
32 	{
33 		bus_start: CONFIG_SYS_PCI_IO_BASE,
34 		phys_start: CONFIG_SYS_PCI_IO_PHYS,
35 		size: CONFIG_SYS_PCI_IO_SIZE,
36 		flags: PCI_REGION_IO
37 	}
38 };
39 
40 static struct pci_region pcie_regions_0[] = {
41 	{
42 		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
43 		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
44 		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
45 		.flags = PCI_REGION_MEM,
46 	},
47 	{
48 		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
49 		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
50 		.size = CONFIG_SYS_PCIE1_IO_SIZE,
51 		.flags = PCI_REGION_IO,
52 	},
53 };
54 
55 static struct pci_region pcie_regions_1[] = {
56 	{
57 		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
58 		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
59 		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
60 		.flags = PCI_REGION_MEM,
61 	},
62 	{
63 		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
64 		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
65 		.size = CONFIG_SYS_PCIE2_IO_SIZE,
66 		.flags = PCI_REGION_IO,
67 	},
68 };
69 
70 void pci_init_board(void)
71 {
72 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
73 	volatile sysconf83xx_t *sysconf = &immr->sysconf;
74 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
75 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
76 	volatile law83xx_t *pcie_law = sysconf->pcielaw;
77 	struct pci_region *reg[] = { pci_regions };
78 	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
79 	u32 spridr = in_be32(&immr->sysconf.spridr);
80 
81 	/* Enable all 5 PCI_CLK_OUTPUTS */
82 	clk->occr |= 0xf8000000;
83 	udelay(2000);
84 
85 	/* Configure PCI Local Access Windows */
86 	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
87 	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
88 
89 	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
90 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
91 
92 	mpc83xx_pci_init(1, reg, 0);
93 
94 	/* There is no PEX in MPC8379 parts. */
95 	if (PARTID_NO_E(spridr) == SPR_8379)
96 		return;
97 
98 	/* Configure the clock for PCIE controller */
99 	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
100 				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
101 
102 	/* Deassert the resets in the control register */
103 	out_be32(&sysconf->pecr1, 0xE0008000);
104 	out_be32(&sysconf->pecr2, 0xE0008000);
105 	udelay(2000);
106 
107 	/* Configure PCI Express Local Access Windows */
108 	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
109 	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
110 
111 	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
112 	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
113 
114 	mpc83xx_pcie_init(2, pcie_reg, 0);
115 }
116 #endif	/* CONFIG_PCI */
117