1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7
8 #include <asm/mmu.h>
9 #include <asm/io.h>
10 #include <mpc83xx.h>
11 #include <pci.h>
12 #include <i2c.h>
13 #include <asm/fsl_i2c.h>
14
15 static struct pci_region pci1_regions[] = {
16 {
17 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
18 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
19 size: CONFIG_SYS_PCI1_MEM_SIZE,
20 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
21 },
22 {
23 bus_start: CONFIG_SYS_PCI1_IO_BASE,
24 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
25 size: CONFIG_SYS_PCI1_IO_SIZE,
26 flags: PCI_REGION_IO
27 },
28 {
29 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
30 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
31 size: CONFIG_SYS_PCI1_MMIO_SIZE,
32 flags: PCI_REGION_MEM
33 },
34 };
35
36 #ifdef CONFIG_MPC83XX_PCI2
37 static struct pci_region pci2_regions[] = {
38 {
39 bus_start: CONFIG_SYS_PCI2_MEM_BASE,
40 phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
41 size: CONFIG_SYS_PCI2_MEM_SIZE,
42 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
43 },
44 {
45 bus_start: CONFIG_SYS_PCI2_IO_BASE,
46 phys_start: CONFIG_SYS_PCI2_IO_PHYS,
47 size: CONFIG_SYS_PCI2_IO_SIZE,
48 flags: PCI_REGION_IO
49 },
50 {
51 bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
52 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
53 size: CONFIG_SYS_PCI2_MMIO_SIZE,
54 flags: PCI_REGION_MEM
55 },
56 };
57 #endif
58
pci_init_board(void)59 void pci_init_board(void)
60 {
61 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
62 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
63 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
64 #ifndef CONFIG_MPC83XX_PCI2
65 struct pci_region *reg[] = { pci1_regions };
66 #else
67 struct pci_region *reg[] = { pci1_regions, pci2_regions };
68 #endif
69 u8 reg8;
70
71 #if defined(CONFIG_SYS_I2C)
72 i2c_set_bus_num(1);
73 /* Read the PCI_M66EN jumper setting */
74 if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0) ||
75 (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, ®8, sizeof(reg8)) == 0)) {
76 if (reg8 & I2C_8574_PCI66)
77 clk->occr = 0xff000000; /* 66 MHz PCI */
78 else
79 clk->occr = 0xff600001; /* 33 MHz PCI */
80 } else {
81 clk->occr = 0xff600001; /* 33 MHz PCI */
82 }
83 #else
84 clk->occr = 0xff000000; /* 66 MHz PCI */
85 #endif
86 udelay(2000);
87
88 /* Configure PCI Local Access Windows */
89 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
90 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
91
92 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
93 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
94
95 udelay(2000);
96
97 #ifndef CONFIG_MPC83XX_PCI2
98 mpc83xx_pci_init(1, reg);
99 #else
100 mpc83xx_pci_init(2, reg);
101 #endif
102 }
103