1 /*
2  * (C) Copyright 2004
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 #include <common.h>
25 #include <command.h>
26 #include <malloc.h>
27 #include <asm/immap.h>
28 
29 
30 /* Prototypes */
31 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
32 
33 int checkboard (void) {
34 	ulong val;
35 	uchar val8;
36 
37 	puts ("Board: ");
38 	puts("Freescale M5249EVB");
39 	val8 = ((uchar)~((uchar)mbar2_readLong(MCFSIM_GPIO1_READ) >> 4)) & 0xf;
40 	printf(" (Switch=%1X)\n", val8);
41 
42 	/*
43 	 * Set LED on
44 	 */
45 	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
46 	mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
47 
48 	return 0;
49 };
50 
51 
52 phys_size_t initdram (int board_type) {
53 	unsigned long	junk = 0xa5a59696;
54 
55 	/*
56 	 *  Note:
57 	 *	RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
58 	 */
59 
60 #ifdef CONFIG_SYS_FAST_CLK
61 	/*
62 	 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
63 	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
64 	 */
65 	mbar_writeShort(MCFSIM_DCR, 0x8239);
66 #elif CONFIG_SYS_PLL_BYPASS
67 	/*
68 	 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
69 	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
70 	 */
71 	mbar_writeShort(MCFSIM_DCR, 0x8202);
72 #else
73 	/*
74 	 * Busclk=36MHz, RefreshTime=64ms, #rows=4096 (4K)
75 	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=22 (562 bus clock cycles)
76 	 */
77 	mbar_writeShort(MCFSIM_DCR, 0x8222);
78 #endif
79 
80 	/*
81 	 * SDRAM starts at 0x0000_0000, CASL=10, CBM=010, PS=10 (16bit port),
82 	 * PM=1 (continuous page mode)
83 	 */
84 
85 	/* RE=0 (keep auto-refresh disabled while setting up registers) */
86 	mbar_writeLong(MCFSIM_DACR0, 0x00003324);
87 
88 	/* BAM=007c (bits 22,21 are bank selects; 256kB blocks) */
89 	mbar_writeLong(MCFSIM_DMR0, 0x01fc0001);
90 
91 	/** Precharge sequence **/
92 	mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */
93 	*((volatile unsigned long *) 0x00) = junk; /* write to a memory location to init. precharge */
94 	udelay(0x10); /* Allow several Precharge cycles */
95 
96 	/** Refresh Sequence **/
97 	mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */
98 	udelay(0x7d0); /* Allow gobs of refresh cycles */
99 
100 	/** Mode Register initialization **/
101 	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
102 	*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
103 
104 	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
105 };
106 
107 
108 int testdram (void) {
109 	/* TODO: XXX XXX XXX */
110 	printf ("DRAM test not implemented!\n");
111 
112 	return (0);
113 }
114