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Kconfig | H A D | 12-Jun-2018 | 727 | 34 | 25 | |
MAINTAINERS | H A D | 10-Dec-2018 | 580 | 19 | 17 | |
Makefile | H A D | 09-May-2017 | 177 | 12 | 5 | |
README | H A D | 26-Sep-2016 | 2.5 KiB | 71 | 66 | |
ddr.c | H A D | 10-Dec-2018 | 2.9 KiB | 130 | 92 | |
ddr.h | H A D | 06-May-2018 | 1,012 | 44 | 23 | |
eth.c | H A D | 18-Jan-2019 | 10.6 KiB | 431 | 349 | |
ls1046aqds.c | H A D | 10-Dec-2018 | 9.1 KiB | 491 | 400 | |
ls1046aqds_pbi.cfg | H A D | 26-Sep-2016 | 329 | 18 | 17 | |
ls1046aqds_qixis.h | H A D | 06-May-2018 | 900 | 39 | 22 | |
ls1046aqds_rcw_nand.cfg | H A D | 26-Sep-2016 | 209 | 8 | 7 | |
ls1046aqds_rcw_sd_ifc.cfg | H A D | 26-Sep-2016 | 224 | 9 | 8 | |
ls1046aqds_rcw_sd_qspi.cfg | H A D | 26-Sep-2016 | 224 | 9 | 8 |
README
1Overview 2-------- 3The LS1046A Development System (QDS) is a high-performance computing, 4evaluation, and development platform that supports the QorIQ LS1046A 5LayerScape Architecture processor. The LS1046AQDS provides SW development 6platform for the Freescale LS1046A processor series, with a complete 7debugging environment. 8 9LS1046A SoC Overview 10-------------------- 11Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A 12SoC overview. 13 14 LS1046AQDS board Overview 15 ----------------------- 16 - SERDES Connections, 8 lanes supporting: 17 - PCI Express - 3.0 18 - SGMII, SGMII 2.5 19 - QSGMII 20 - SATA 3.0 21 - XFI 22 - DDR Controller 23 - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s 24 -IFC/Local Bus 25 - One in-socket 128 MB NOR flash 16-bit data bus 26 - One 512 MB NAND flash with ECC support 27 - PromJet Port 28 - FPGA connection 29 - USB 3.0 30 - Three high speed USB 3.0 ports 31 - First USB 3.0 port configured as Host with Type-A connector 32 - The other two USB 3.0 ports configured as OTG with micro-AB connector 33 - SDHC port connects directly to an adapter card slot, featuring: 34 - Optional clock feedback paths, and optional high-speed voltage translation assistance 35 - SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC 36 - eMMC memory devices 37 - DSPI: Onboard support for three SPI flash memory devices 38 - 4 I2C controllers 39 - One SATA onboard connectors 40 - UART 41 - Two 4-pin serial ports at up to 115.2 Kbit/s 42 - Two DB9 D-Type connectors supporting one Serial port each 43 - ARM JTAG support 44 45Memory map from core's view 46---------------------------- 47Start Address End Address Description Size 480x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB 490x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB 500x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB 510x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB 520x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB 530x00_6000_0000 - 0x00_67FF_FFFF IFC - NOR Flash 128MB 540x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB 550x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - FPGA 4KB 560x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB 570x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M 580x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M 590x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB 600x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G 610x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G 620x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G 63 64Booting Options 65--------------- 66a) Promjet Boot 67b) NOR boot 68c) NAND boot 69d) SD boot 70e) QSPI boot 71