1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <i2c.h> 9 #include <hwconfig.h> 10 #include <fsl_ddr.h> 11 #include <asm/mmu.h> 12 #include <fsl_ddr_sdram.h> 13 #include <fsl_ddr_dimm_params.h> 14 #include <asm/fsl_law.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 dimm_params_t ddr_raw_timing = { 19 .n_ranks = 2, 20 .rank_density = 2147483648u, 21 .capacity = 4294967296u, 22 .primary_sdram_width = 64, 23 .ec_sdram_width = 8, 24 .registered_dimm = 0, 25 .mirrored_dimm = 1, 26 .n_row_addr = 15, 27 .n_col_addr = 10, 28 .n_banks_per_sdram_device = 8, 29 .edc_config = 2, /* ECC */ 30 .burst_lengths_bitmask = 0x0c, 31 32 .tckmin_x_ps = 1071, 33 .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ 34 .taa_ps = 13910, 35 .twr_ps = 15000, 36 .trcd_ps = 13910, 37 .trrd_ps = 6000, 38 .trp_ps = 13910, 39 .tras_ps = 34000, 40 .trc_ps = 48910, 41 .trfc_ps = 260000, 42 .twtr_ps = 7500, 43 .trtp_ps = 7500, 44 .refresh_rate_ps = 7800000, 45 .tfaw_ps = 35000, 46 }; 47 48 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 49 unsigned int controller_number, 50 unsigned int dimm_number) 51 { 52 const char dimm_model[] = "RAW timing DDR"; 53 54 if ((controller_number == 0) && (dimm_number == 0)) { 55 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 56 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 57 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 58 } 59 60 return 0; 61 } 62 63 struct board_specific_parameters { 64 u32 n_ranks; 65 u32 datarate_mhz_high; 66 u32 clk_adjust; 67 u32 wrlvl_start; 68 u32 wrlvl_ctl_2; 69 u32 wrlvl_ctl_3; 70 u32 cpo; 71 u32 write_data_delay; 72 u32 force_2t; 73 }; 74 75 /* 76 * This table contains all valid speeds we want to override with board 77 * specific parameters. datarate_mhz_high values need to be in ascending order 78 * for each n_ranks group. 79 */ 80 static const struct board_specific_parameters udimm0[] = { 81 /* 82 * memory controller 0 83 * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 84 * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | 85 */ 86 {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, 87 {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, 88 {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, 89 {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, 90 {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, 91 {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, 92 {} 93 }; 94 95 static const struct board_specific_parameters *udimms[] = { 96 udimm0, 97 }; 98 99 void fsl_ddr_board_options(memctl_options_t *popts, 100 dimm_params_t *pdimm, 101 unsigned int ctrl_num) 102 { 103 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 104 ulong ddr_freq; 105 106 if (ctrl_num > 2) { 107 printf("Not supported controller number %d\n", ctrl_num); 108 return; 109 } 110 if (!pdimm->n_ranks) 111 return; 112 113 pbsp = udimms[0]; 114 115 116 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 117 * freqency and n_banks specified in board_specific_parameters table. 118 */ 119 ddr_freq = get_ddr_freq(0) / 1000000; 120 while (pbsp->datarate_mhz_high) { 121 if (pbsp->n_ranks == pdimm->n_ranks) { 122 if (ddr_freq <= pbsp->datarate_mhz_high) { 123 popts->cpo_override = pbsp->cpo; 124 popts->write_data_delay = 125 pbsp->write_data_delay; 126 popts->clk_adjust = pbsp->clk_adjust; 127 popts->wrlvl_start = pbsp->wrlvl_start; 128 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 129 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 130 popts->twot_en = pbsp->force_2t; 131 goto found; 132 } 133 pbsp_highest = pbsp; 134 } 135 pbsp++; 136 } 137 138 if (pbsp_highest) { 139 printf("Error: board specific timing not found " 140 "for data rate %lu MT/s\n" 141 "Trying to use the highest speed (%u) parameters\n", 142 ddr_freq, pbsp_highest->datarate_mhz_high); 143 popts->cpo_override = pbsp_highest->cpo; 144 popts->write_data_delay = pbsp_highest->write_data_delay; 145 popts->clk_adjust = pbsp_highest->clk_adjust; 146 popts->wrlvl_start = pbsp_highest->wrlvl_start; 147 popts->twot_en = pbsp_highest->force_2t; 148 } else { 149 panic("DIMM is not supported by this board"); 150 } 151 found: 152 /* 153 * Factors to consider for half-strength driver enable: 154 * - number of DIMMs installed 155 */ 156 popts->half_strength_driver_enable = 0; 157 /* 158 * Write leveling override 159 */ 160 popts->wrlvl_override = 1; 161 popts->wrlvl_sample = 0xf; 162 163 /* 164 * Rtt and Rtt_WR override 165 */ 166 popts->rtt_override = 0; 167 168 /* Enable ZQ calibration */ 169 popts->zq_en = 1; 170 171 /* DHC_EN =1, ODT = 75 Ohm */ 172 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 173 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 174 } 175 176 phys_size_t initdram(int board_type) 177 { 178 phys_size_t dram_size; 179 180 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) 181 puts("Initializing....using SPD\n"); 182 183 dram_size = fsl_ddr_sdram(); 184 185 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 186 dram_size *= 0x100000; 187 188 #else 189 dram_size = fsl_ddr_sdram_size(); 190 #endif 191 return dram_size; 192 } 193 194 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, 195 unsigned int dbw_cap_adj[]) 196 { 197 int i, j; 198 unsigned long long total_mem, current_mem_base, total_ctlr_mem; 199 unsigned long long rank_density, ctlr_density = 0; 200 201 current_mem_base = 0ull; 202 total_mem = 0; 203 /* 204 * This board has soldered DDR chips. DDRC1 has two rank. 205 * DDRC2 has only one rank. 206 * Assigning DDRC2 to lower address and DDRC1 to higher address. 207 */ 208 if (pinfo->memctl_opts[0].memctl_interleaving) { 209 rank_density = pinfo->dimm_params[0][0].rank_density >> 210 dbw_cap_adj[0]; 211 ctlr_density = rank_density; 212 213 debug("rank density is 0x%llx, ctlr density is 0x%llx\n", 214 rank_density, ctlr_density); 215 for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { 216 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { 217 case FSL_DDR_CACHE_LINE_INTERLEAVING: 218 case FSL_DDR_PAGE_INTERLEAVING: 219 case FSL_DDR_BANK_INTERLEAVING: 220 case FSL_DDR_SUPERBANK_INTERLEAVING: 221 total_ctlr_mem = 2 * ctlr_density; 222 break; 223 default: 224 panic("Unknown interleaving mode"); 225 } 226 pinfo->common_timing_params[i].base_address = 227 current_mem_base; 228 pinfo->common_timing_params[i].total_mem = 229 total_ctlr_mem; 230 total_mem = current_mem_base + total_ctlr_mem; 231 debug("ctrl %d base 0x%llx\n", i, current_mem_base); 232 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 233 } 234 } else { 235 /* 236 * Simple linear assignment if memory 237 * controllers are not interleaved. 238 */ 239 for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { 240 total_ctlr_mem = 0; 241 pinfo->common_timing_params[i].base_address = 242 current_mem_base; 243 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 244 /* Compute DIMM base addresses. */ 245 unsigned long long cap = 246 pinfo->dimm_params[i][j].capacity; 247 pinfo->dimm_params[i][j].base_address = 248 current_mem_base; 249 debug("ctrl %d dimm %d base 0x%llx\n", 250 i, j, current_mem_base); 251 current_mem_base += cap; 252 total_ctlr_mem += cap; 253 } 254 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 255 pinfo->common_timing_params[i].total_mem = 256 total_ctlr_mem; 257 total_mem += total_ctlr_mem; 258 } 259 } 260 debug("Total mem by %s is 0x%llx\n", __func__, total_mem); 261 262 return total_mem; 263 } 264