1*b5b06fb7SYork Sun /* 2*b5b06fb7SYork Sun * Copyright 2011-2012 Freescale Semiconductor, Inc. 3*b5b06fb7SYork Sun * 4*b5b06fb7SYork Sun * This program is free software; you can redistribute it and/or 5*b5b06fb7SYork Sun * modify it under the terms of the GNU General Public License 6*b5b06fb7SYork Sun * Version 2 or later as published by the Free Software Foundation. 7*b5b06fb7SYork Sun */ 8*b5b06fb7SYork Sun 9*b5b06fb7SYork Sun #include <common.h> 10*b5b06fb7SYork Sun #include <i2c.h> 11*b5b06fb7SYork Sun #include <hwconfig.h> 12*b5b06fb7SYork Sun #include <asm/mmu.h> 13*b5b06fb7SYork Sun #include <asm/fsl_ddr_sdram.h> 14*b5b06fb7SYork Sun #include <asm/fsl_ddr_dimm_params.h> 15*b5b06fb7SYork Sun #include <asm/fsl_law.h> 16*b5b06fb7SYork Sun 17*b5b06fb7SYork Sun DECLARE_GLOBAL_DATA_PTR; 18*b5b06fb7SYork Sun 19*b5b06fb7SYork Sun dimm_params_t ddr_raw_timing = { 20*b5b06fb7SYork Sun .n_ranks = 2, 21*b5b06fb7SYork Sun .rank_density = 2147483648u, 22*b5b06fb7SYork Sun .capacity = 4294967296u, 23*b5b06fb7SYork Sun .primary_sdram_width = 64, 24*b5b06fb7SYork Sun .ec_sdram_width = 8, 25*b5b06fb7SYork Sun .registered_dimm = 0, 26*b5b06fb7SYork Sun .mirrored_dimm = 1, 27*b5b06fb7SYork Sun .n_row_addr = 15, 28*b5b06fb7SYork Sun .n_col_addr = 10, 29*b5b06fb7SYork Sun .n_banks_per_sdram_device = 8, 30*b5b06fb7SYork Sun .edc_config = 2, /* ECC */ 31*b5b06fb7SYork Sun .burst_lengths_bitmask = 0x0c, 32*b5b06fb7SYork Sun 33*b5b06fb7SYork Sun .tCKmin_X_ps = 1071, 34*b5b06fb7SYork Sun .caslat_X = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ 35*b5b06fb7SYork Sun .tAA_ps = 13910, 36*b5b06fb7SYork Sun .tWR_ps = 15000, 37*b5b06fb7SYork Sun .tRCD_ps = 13910, 38*b5b06fb7SYork Sun .tRRD_ps = 6000, 39*b5b06fb7SYork Sun .tRP_ps = 13910, 40*b5b06fb7SYork Sun .tRAS_ps = 34000, 41*b5b06fb7SYork Sun .tRC_ps = 48910, 42*b5b06fb7SYork Sun .tRFC_ps = 260000, 43*b5b06fb7SYork Sun .tWTR_ps = 7500, 44*b5b06fb7SYork Sun .tRTP_ps = 7500, 45*b5b06fb7SYork Sun .refresh_rate_ps = 7800000, 46*b5b06fb7SYork Sun .tFAW_ps = 35000, 47*b5b06fb7SYork Sun }; 48*b5b06fb7SYork Sun 49*b5b06fb7SYork Sun int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 50*b5b06fb7SYork Sun unsigned int controller_number, 51*b5b06fb7SYork Sun unsigned int dimm_number) 52*b5b06fb7SYork Sun { 53*b5b06fb7SYork Sun const char dimm_model[] = "RAW timing DDR"; 54*b5b06fb7SYork Sun 55*b5b06fb7SYork Sun if ((controller_number == 0) && (dimm_number == 0)) { 56*b5b06fb7SYork Sun memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 57*b5b06fb7SYork Sun memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 58*b5b06fb7SYork Sun memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 59*b5b06fb7SYork Sun } 60*b5b06fb7SYork Sun 61*b5b06fb7SYork Sun return 0; 62*b5b06fb7SYork Sun } 63*b5b06fb7SYork Sun 64*b5b06fb7SYork Sun struct board_specific_parameters { 65*b5b06fb7SYork Sun u32 n_ranks; 66*b5b06fb7SYork Sun u32 datarate_mhz_high; 67*b5b06fb7SYork Sun u32 clk_adjust; 68*b5b06fb7SYork Sun u32 wrlvl_start; 69*b5b06fb7SYork Sun u32 wrlvl_ctl_2; 70*b5b06fb7SYork Sun u32 wrlvl_ctl_3; 71*b5b06fb7SYork Sun u32 cpo; 72*b5b06fb7SYork Sun u32 write_data_delay; 73*b5b06fb7SYork Sun u32 force_2T; 74*b5b06fb7SYork Sun }; 75*b5b06fb7SYork Sun 76*b5b06fb7SYork Sun /* 77*b5b06fb7SYork Sun * This table contains all valid speeds we want to override with board 78*b5b06fb7SYork Sun * specific parameters. datarate_mhz_high values need to be in ascending order 79*b5b06fb7SYork Sun * for each n_ranks group. 80*b5b06fb7SYork Sun */ 81*b5b06fb7SYork Sun static const struct board_specific_parameters udimm0[] = { 82*b5b06fb7SYork Sun /* 83*b5b06fb7SYork Sun * memory controller 0 84*b5b06fb7SYork Sun * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 85*b5b06fb7SYork Sun * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | 86*b5b06fb7SYork Sun */ 87*b5b06fb7SYork Sun {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, 88*b5b06fb7SYork Sun {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, 89*b5b06fb7SYork Sun {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, 90*b5b06fb7SYork Sun {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, 91*b5b06fb7SYork Sun {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, 92*b5b06fb7SYork Sun {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, 93*b5b06fb7SYork Sun {} 94*b5b06fb7SYork Sun }; 95*b5b06fb7SYork Sun 96*b5b06fb7SYork Sun static const struct board_specific_parameters *udimms[] = { 97*b5b06fb7SYork Sun udimm0, 98*b5b06fb7SYork Sun }; 99*b5b06fb7SYork Sun 100*b5b06fb7SYork Sun void fsl_ddr_board_options(memctl_options_t *popts, 101*b5b06fb7SYork Sun dimm_params_t *pdimm, 102*b5b06fb7SYork Sun unsigned int ctrl_num) 103*b5b06fb7SYork Sun { 104*b5b06fb7SYork Sun const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 105*b5b06fb7SYork Sun ulong ddr_freq; 106*b5b06fb7SYork Sun 107*b5b06fb7SYork Sun if (ctrl_num > 2) { 108*b5b06fb7SYork Sun printf("Not supported controller number %d\n", ctrl_num); 109*b5b06fb7SYork Sun return; 110*b5b06fb7SYork Sun } 111*b5b06fb7SYork Sun if (!pdimm->n_ranks) 112*b5b06fb7SYork Sun return; 113*b5b06fb7SYork Sun 114*b5b06fb7SYork Sun pbsp = udimms[0]; 115*b5b06fb7SYork Sun 116*b5b06fb7SYork Sun 117*b5b06fb7SYork Sun /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 118*b5b06fb7SYork Sun * freqency and n_banks specified in board_specific_parameters table. 119*b5b06fb7SYork Sun */ 120*b5b06fb7SYork Sun ddr_freq = get_ddr_freq(0) / 1000000; 121*b5b06fb7SYork Sun while (pbsp->datarate_mhz_high) { 122*b5b06fb7SYork Sun if (pbsp->n_ranks == pdimm->n_ranks) { 123*b5b06fb7SYork Sun if (ddr_freq <= pbsp->datarate_mhz_high) { 124*b5b06fb7SYork Sun popts->cpo_override = pbsp->cpo; 125*b5b06fb7SYork Sun popts->write_data_delay = 126*b5b06fb7SYork Sun pbsp->write_data_delay; 127*b5b06fb7SYork Sun popts->clk_adjust = pbsp->clk_adjust; 128*b5b06fb7SYork Sun popts->wrlvl_start = pbsp->wrlvl_start; 129*b5b06fb7SYork Sun popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 130*b5b06fb7SYork Sun popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 131*b5b06fb7SYork Sun popts->twoT_en = pbsp->force_2T; 132*b5b06fb7SYork Sun goto found; 133*b5b06fb7SYork Sun } 134*b5b06fb7SYork Sun pbsp_highest = pbsp; 135*b5b06fb7SYork Sun } 136*b5b06fb7SYork Sun pbsp++; 137*b5b06fb7SYork Sun } 138*b5b06fb7SYork Sun 139*b5b06fb7SYork Sun if (pbsp_highest) { 140*b5b06fb7SYork Sun printf("Error: board specific timing not found " 141*b5b06fb7SYork Sun "for data rate %lu MT/s\n" 142*b5b06fb7SYork Sun "Trying to use the highest speed (%u) parameters\n", 143*b5b06fb7SYork Sun ddr_freq, pbsp_highest->datarate_mhz_high); 144*b5b06fb7SYork Sun popts->cpo_override = pbsp_highest->cpo; 145*b5b06fb7SYork Sun popts->write_data_delay = pbsp_highest->write_data_delay; 146*b5b06fb7SYork Sun popts->clk_adjust = pbsp_highest->clk_adjust; 147*b5b06fb7SYork Sun popts->wrlvl_start = pbsp_highest->wrlvl_start; 148*b5b06fb7SYork Sun popts->twoT_en = pbsp_highest->force_2T; 149*b5b06fb7SYork Sun } else { 150*b5b06fb7SYork Sun panic("DIMM is not supported by this board"); 151*b5b06fb7SYork Sun } 152*b5b06fb7SYork Sun found: 153*b5b06fb7SYork Sun /* 154*b5b06fb7SYork Sun * Factors to consider for half-strength driver enable: 155*b5b06fb7SYork Sun * - number of DIMMs installed 156*b5b06fb7SYork Sun */ 157*b5b06fb7SYork Sun popts->half_strength_driver_enable = 0; 158*b5b06fb7SYork Sun /* 159*b5b06fb7SYork Sun * Write leveling override 160*b5b06fb7SYork Sun */ 161*b5b06fb7SYork Sun popts->wrlvl_override = 1; 162*b5b06fb7SYork Sun popts->wrlvl_sample = 0xf; 163*b5b06fb7SYork Sun 164*b5b06fb7SYork Sun /* 165*b5b06fb7SYork Sun * Rtt and Rtt_WR override 166*b5b06fb7SYork Sun */ 167*b5b06fb7SYork Sun popts->rtt_override = 0; 168*b5b06fb7SYork Sun 169*b5b06fb7SYork Sun /* Enable ZQ calibration */ 170*b5b06fb7SYork Sun popts->zq_en = 1; 171*b5b06fb7SYork Sun 172*b5b06fb7SYork Sun /* DHC_EN =1, ODT = 75 Ohm */ 173*b5b06fb7SYork Sun popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 174*b5b06fb7SYork Sun popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 175*b5b06fb7SYork Sun } 176*b5b06fb7SYork Sun 177*b5b06fb7SYork Sun phys_size_t initdram(int board_type) 178*b5b06fb7SYork Sun { 179*b5b06fb7SYork Sun phys_size_t dram_size; 180*b5b06fb7SYork Sun 181*b5b06fb7SYork Sun puts("Initializing....using SPD\n"); 182*b5b06fb7SYork Sun 183*b5b06fb7SYork Sun dram_size = fsl_ddr_sdram(); 184*b5b06fb7SYork Sun 185*b5b06fb7SYork Sun dram_size = setup_ddr_tlbs(dram_size / 0x100000); 186*b5b06fb7SYork Sun dram_size *= 0x100000; 187*b5b06fb7SYork Sun 188*b5b06fb7SYork Sun puts(" DDR: "); 189*b5b06fb7SYork Sun return dram_size; 190*b5b06fb7SYork Sun } 191