1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0 2b5b06fb7SYork Sun /* 3b5b06fb7SYork Sun * Copyright 2011-2012 Freescale Semiconductor, Inc. 4b5b06fb7SYork Sun */ 5b5b06fb7SYork Sun 6b5b06fb7SYork Sun #include <common.h> 7b5b06fb7SYork Sun #include <i2c.h> 8b5b06fb7SYork Sun #include <hwconfig.h> 95614e71bSYork Sun #include <fsl_ddr.h> 10b5b06fb7SYork Sun #include <asm/mmu.h> 115614e71bSYork Sun #include <fsl_ddr_sdram.h> 125614e71bSYork Sun #include <fsl_ddr_dimm_params.h> 13b5b06fb7SYork Sun #include <asm/fsl_law.h> 14b5b06fb7SYork Sun 15b5b06fb7SYork Sun DECLARE_GLOBAL_DATA_PTR; 16b5b06fb7SYork Sun 17b5b06fb7SYork Sun dimm_params_t ddr_raw_timing = { 18b5b06fb7SYork Sun .n_ranks = 2, 19b5b06fb7SYork Sun .rank_density = 2147483648u, 20b5b06fb7SYork Sun .capacity = 4294967296u, 21b5b06fb7SYork Sun .primary_sdram_width = 64, 22b5b06fb7SYork Sun .ec_sdram_width = 8, 23b5b06fb7SYork Sun .registered_dimm = 0, 24b5b06fb7SYork Sun .mirrored_dimm = 1, 25b5b06fb7SYork Sun .n_row_addr = 15, 26b5b06fb7SYork Sun .n_col_addr = 10, 27b5b06fb7SYork Sun .n_banks_per_sdram_device = 8, 28b5b06fb7SYork Sun .edc_config = 2, /* ECC */ 29b5b06fb7SYork Sun .burst_lengths_bitmask = 0x0c, 30b5b06fb7SYork Sun 310dd38a35SPriyanka Jain .tckmin_x_ps = 1071, 320dd38a35SPriyanka Jain .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ 330dd38a35SPriyanka Jain .taa_ps = 13910, 340dd38a35SPriyanka Jain .twr_ps = 15000, 350dd38a35SPriyanka Jain .trcd_ps = 13910, 360dd38a35SPriyanka Jain .trrd_ps = 6000, 370dd38a35SPriyanka Jain .trp_ps = 13910, 380dd38a35SPriyanka Jain .tras_ps = 34000, 390dd38a35SPriyanka Jain .trc_ps = 48910, 400dd38a35SPriyanka Jain .trfc_ps = 260000, 410dd38a35SPriyanka Jain .twtr_ps = 7500, 420dd38a35SPriyanka Jain .trtp_ps = 7500, 43b5b06fb7SYork Sun .refresh_rate_ps = 7800000, 440dd38a35SPriyanka Jain .tfaw_ps = 35000, 45b5b06fb7SYork Sun }; 46b5b06fb7SYork Sun 47b5b06fb7SYork Sun int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 48b5b06fb7SYork Sun unsigned int controller_number, 49b5b06fb7SYork Sun unsigned int dimm_number) 50b5b06fb7SYork Sun { 51b5b06fb7SYork Sun const char dimm_model[] = "RAW timing DDR"; 52b5b06fb7SYork Sun 53b5b06fb7SYork Sun if ((controller_number == 0) && (dimm_number == 0)) { 54b5b06fb7SYork Sun memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 55b5b06fb7SYork Sun memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 56b5b06fb7SYork Sun memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 57b5b06fb7SYork Sun } 58b5b06fb7SYork Sun 59b5b06fb7SYork Sun return 0; 60b5b06fb7SYork Sun } 61b5b06fb7SYork Sun 62b5b06fb7SYork Sun struct board_specific_parameters { 63b5b06fb7SYork Sun u32 n_ranks; 64b5b06fb7SYork Sun u32 datarate_mhz_high; 65b5b06fb7SYork Sun u32 clk_adjust; 66b5b06fb7SYork Sun u32 wrlvl_start; 67b5b06fb7SYork Sun u32 wrlvl_ctl_2; 68b5b06fb7SYork Sun u32 wrlvl_ctl_3; 69b5b06fb7SYork Sun u32 cpo; 70b5b06fb7SYork Sun u32 write_data_delay; 710dd38a35SPriyanka Jain u32 force_2t; 72b5b06fb7SYork Sun }; 73b5b06fb7SYork Sun 74b5b06fb7SYork Sun /* 75b5b06fb7SYork Sun * This table contains all valid speeds we want to override with board 76b5b06fb7SYork Sun * specific parameters. datarate_mhz_high values need to be in ascending order 77b5b06fb7SYork Sun * for each n_ranks group. 78b5b06fb7SYork Sun */ 79b5b06fb7SYork Sun static const struct board_specific_parameters udimm0[] = { 80b5b06fb7SYork Sun /* 81b5b06fb7SYork Sun * memory controller 0 82b5b06fb7SYork Sun * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 83b5b06fb7SYork Sun * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | 84b5b06fb7SYork Sun */ 85b5b06fb7SYork Sun {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, 86b5b06fb7SYork Sun {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, 87b5b06fb7SYork Sun {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, 88b5b06fb7SYork Sun {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, 89b5b06fb7SYork Sun {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, 90b5b06fb7SYork Sun {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, 91b5b06fb7SYork Sun {} 92b5b06fb7SYork Sun }; 93b5b06fb7SYork Sun 94b5b06fb7SYork Sun static const struct board_specific_parameters *udimms[] = { 95b5b06fb7SYork Sun udimm0, 96b5b06fb7SYork Sun }; 97b5b06fb7SYork Sun 98b5b06fb7SYork Sun void fsl_ddr_board_options(memctl_options_t *popts, 99b5b06fb7SYork Sun dimm_params_t *pdimm, 100b5b06fb7SYork Sun unsigned int ctrl_num) 101b5b06fb7SYork Sun { 102b5b06fb7SYork Sun const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 103b5b06fb7SYork Sun ulong ddr_freq; 104b5b06fb7SYork Sun 105b5b06fb7SYork Sun if (ctrl_num > 2) { 106b5b06fb7SYork Sun printf("Not supported controller number %d\n", ctrl_num); 107b5b06fb7SYork Sun return; 108b5b06fb7SYork Sun } 109b5b06fb7SYork Sun if (!pdimm->n_ranks) 110b5b06fb7SYork Sun return; 111b5b06fb7SYork Sun 112b5b06fb7SYork Sun pbsp = udimms[0]; 113b5b06fb7SYork Sun 114b5b06fb7SYork Sun 115b5b06fb7SYork Sun /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 116b5b06fb7SYork Sun * freqency and n_banks specified in board_specific_parameters table. 117b5b06fb7SYork Sun */ 118b5b06fb7SYork Sun ddr_freq = get_ddr_freq(0) / 1000000; 119b5b06fb7SYork Sun while (pbsp->datarate_mhz_high) { 120b5b06fb7SYork Sun if (pbsp->n_ranks == pdimm->n_ranks) { 121b5b06fb7SYork Sun if (ddr_freq <= pbsp->datarate_mhz_high) { 122b5b06fb7SYork Sun popts->cpo_override = pbsp->cpo; 123b5b06fb7SYork Sun popts->write_data_delay = 124b5b06fb7SYork Sun pbsp->write_data_delay; 125b5b06fb7SYork Sun popts->clk_adjust = pbsp->clk_adjust; 126b5b06fb7SYork Sun popts->wrlvl_start = pbsp->wrlvl_start; 127b5b06fb7SYork Sun popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 128b5b06fb7SYork Sun popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 1290dd38a35SPriyanka Jain popts->twot_en = pbsp->force_2t; 130b5b06fb7SYork Sun goto found; 131b5b06fb7SYork Sun } 132b5b06fb7SYork Sun pbsp_highest = pbsp; 133b5b06fb7SYork Sun } 134b5b06fb7SYork Sun pbsp++; 135b5b06fb7SYork Sun } 136b5b06fb7SYork Sun 137b5b06fb7SYork Sun if (pbsp_highest) { 138b5b06fb7SYork Sun printf("Error: board specific timing not found " 139b5b06fb7SYork Sun "for data rate %lu MT/s\n" 140b5b06fb7SYork Sun "Trying to use the highest speed (%u) parameters\n", 141b5b06fb7SYork Sun ddr_freq, pbsp_highest->datarate_mhz_high); 142b5b06fb7SYork Sun popts->cpo_override = pbsp_highest->cpo; 143b5b06fb7SYork Sun popts->write_data_delay = pbsp_highest->write_data_delay; 144b5b06fb7SYork Sun popts->clk_adjust = pbsp_highest->clk_adjust; 145b5b06fb7SYork Sun popts->wrlvl_start = pbsp_highest->wrlvl_start; 1460dd38a35SPriyanka Jain popts->twot_en = pbsp_highest->force_2t; 147b5b06fb7SYork Sun } else { 148b5b06fb7SYork Sun panic("DIMM is not supported by this board"); 149b5b06fb7SYork Sun } 150b5b06fb7SYork Sun found: 151b5b06fb7SYork Sun /* 152b5b06fb7SYork Sun * Factors to consider for half-strength driver enable: 153b5b06fb7SYork Sun * - number of DIMMs installed 154b5b06fb7SYork Sun */ 155b5b06fb7SYork Sun popts->half_strength_driver_enable = 0; 156b5b06fb7SYork Sun /* 157b5b06fb7SYork Sun * Write leveling override 158b5b06fb7SYork Sun */ 159b5b06fb7SYork Sun popts->wrlvl_override = 1; 160b5b06fb7SYork Sun popts->wrlvl_sample = 0xf; 161b5b06fb7SYork Sun 162b5b06fb7SYork Sun /* 163b5b06fb7SYork Sun * Rtt and Rtt_WR override 164b5b06fb7SYork Sun */ 165b5b06fb7SYork Sun popts->rtt_override = 0; 166b5b06fb7SYork Sun 167b5b06fb7SYork Sun /* Enable ZQ calibration */ 168b5b06fb7SYork Sun popts->zq_en = 1; 169b5b06fb7SYork Sun 170b5b06fb7SYork Sun /* DHC_EN =1, ODT = 75 Ohm */ 171b5b06fb7SYork Sun popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 172b5b06fb7SYork Sun popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 17390101386SShengzhou Liu 17490101386SShengzhou Liu /* optimize cpo for erratum A-009942 */ 17590101386SShengzhou Liu popts->cpo_sample = 0x3e; 176b5b06fb7SYork Sun } 177b5b06fb7SYork Sun 178f1683aa7SSimon Glass int dram_init(void) 179b5b06fb7SYork Sun { 180b5b06fb7SYork Sun phys_size_t dram_size; 181b5b06fb7SYork Sun 182c5dfe6ecSPrabhakar Kushwaha #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) 183b5b06fb7SYork Sun puts("Initializing....using SPD\n"); 184b5b06fb7SYork Sun dram_size = fsl_ddr_sdram(); 185c5dfe6ecSPrabhakar Kushwaha #else 186c5dfe6ecSPrabhakar Kushwaha dram_size = fsl_ddr_sdram_size(); 187c5dfe6ecSPrabhakar Kushwaha #endif 18853499282SShengzhou Liu dram_size = setup_ddr_tlbs(dram_size / 0x100000); 18953499282SShengzhou Liu dram_size *= 0x100000; 19053499282SShengzhou Liu 191088454cdSSimon Glass gd->ram_size = dram_size; 192088454cdSSimon Glass 193088454cdSSimon Glass return 0; 194b5b06fb7SYork Sun } 19543104795SYork Sun 19643104795SYork Sun unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, 19743104795SYork Sun unsigned int dbw_cap_adj[]) 19843104795SYork Sun { 19943104795SYork Sun int i, j; 20043104795SYork Sun unsigned long long total_mem, current_mem_base, total_ctlr_mem; 20143104795SYork Sun unsigned long long rank_density, ctlr_density = 0; 20243104795SYork Sun 20343104795SYork Sun current_mem_base = 0ull; 20443104795SYork Sun total_mem = 0; 20543104795SYork Sun /* 20643104795SYork Sun * This board has soldered DDR chips. DDRC1 has two rank. 20743104795SYork Sun * DDRC2 has only one rank. 20843104795SYork Sun * Assigning DDRC2 to lower address and DDRC1 to higher address. 20943104795SYork Sun */ 21043104795SYork Sun if (pinfo->memctl_opts[0].memctl_interleaving) { 21143104795SYork Sun rank_density = pinfo->dimm_params[0][0].rank_density >> 21243104795SYork Sun dbw_cap_adj[0]; 21343104795SYork Sun ctlr_density = rank_density; 21443104795SYork Sun 21543104795SYork Sun debug("rank density is 0x%llx, ctlr density is 0x%llx\n", 21643104795SYork Sun rank_density, ctlr_density); 21751370d56SYork Sun for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) { 21843104795SYork Sun switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { 21943104795SYork Sun case FSL_DDR_CACHE_LINE_INTERLEAVING: 22043104795SYork Sun case FSL_DDR_PAGE_INTERLEAVING: 22143104795SYork Sun case FSL_DDR_BANK_INTERLEAVING: 22243104795SYork Sun case FSL_DDR_SUPERBANK_INTERLEAVING: 22343104795SYork Sun total_ctlr_mem = 2 * ctlr_density; 22443104795SYork Sun break; 22543104795SYork Sun default: 22643104795SYork Sun panic("Unknown interleaving mode"); 22743104795SYork Sun } 22843104795SYork Sun pinfo->common_timing_params[i].base_address = 22943104795SYork Sun current_mem_base; 23043104795SYork Sun pinfo->common_timing_params[i].total_mem = 23143104795SYork Sun total_ctlr_mem; 23243104795SYork Sun total_mem = current_mem_base + total_ctlr_mem; 23343104795SYork Sun debug("ctrl %d base 0x%llx\n", i, current_mem_base); 23443104795SYork Sun debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 23543104795SYork Sun } 23643104795SYork Sun } else { 23743104795SYork Sun /* 23843104795SYork Sun * Simple linear assignment if memory 23943104795SYork Sun * controllers are not interleaved. 24043104795SYork Sun */ 24151370d56SYork Sun for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) { 24243104795SYork Sun total_ctlr_mem = 0; 24343104795SYork Sun pinfo->common_timing_params[i].base_address = 24443104795SYork Sun current_mem_base; 24543104795SYork Sun for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 24643104795SYork Sun /* Compute DIMM base addresses. */ 24743104795SYork Sun unsigned long long cap = 24843104795SYork Sun pinfo->dimm_params[i][j].capacity; 24943104795SYork Sun pinfo->dimm_params[i][j].base_address = 25043104795SYork Sun current_mem_base; 25143104795SYork Sun debug("ctrl %d dimm %d base 0x%llx\n", 25243104795SYork Sun i, j, current_mem_base); 25343104795SYork Sun current_mem_base += cap; 25443104795SYork Sun total_ctlr_mem += cap; 25543104795SYork Sun } 25643104795SYork Sun debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 25743104795SYork Sun pinfo->common_timing_params[i].total_mem = 25843104795SYork Sun total_ctlr_mem; 25943104795SYork Sun total_mem += total_ctlr_mem; 26043104795SYork Sun } 26143104795SYork Sun } 26243104795SYork Sun debug("Total mem by %s is 0x%llx\n", __func__, total_mem); 26343104795SYork Sun 26443104795SYork Sun return total_mem; 26543104795SYork Sun } 266