1b5b06fb7SYork Sun /* 2b5b06fb7SYork Sun * Copyright 2011-2012 Freescale Semiconductor, Inc. 3b5b06fb7SYork Sun * 4b5b06fb7SYork Sun * This program is free software; you can redistribute it and/or 5b5b06fb7SYork Sun * modify it under the terms of the GNU General Public License 6b5b06fb7SYork Sun * Version 2 or later as published by the Free Software Foundation. 7b5b06fb7SYork Sun */ 8b5b06fb7SYork Sun 9b5b06fb7SYork Sun #include <common.h> 10b5b06fb7SYork Sun #include <i2c.h> 11b5b06fb7SYork Sun #include <hwconfig.h> 12b5b06fb7SYork Sun #include <asm/mmu.h> 13b5b06fb7SYork Sun #include <asm/fsl_ddr_sdram.h> 14b5b06fb7SYork Sun #include <asm/fsl_ddr_dimm_params.h> 15b5b06fb7SYork Sun #include <asm/fsl_law.h> 16*43104795SYork Sun #include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h> 17b5b06fb7SYork Sun 18b5b06fb7SYork Sun DECLARE_GLOBAL_DATA_PTR; 19b5b06fb7SYork Sun 20b5b06fb7SYork Sun dimm_params_t ddr_raw_timing = { 21b5b06fb7SYork Sun .n_ranks = 2, 22b5b06fb7SYork Sun .rank_density = 2147483648u, 23b5b06fb7SYork Sun .capacity = 4294967296u, 24b5b06fb7SYork Sun .primary_sdram_width = 64, 25b5b06fb7SYork Sun .ec_sdram_width = 8, 26b5b06fb7SYork Sun .registered_dimm = 0, 27b5b06fb7SYork Sun .mirrored_dimm = 1, 28b5b06fb7SYork Sun .n_row_addr = 15, 29b5b06fb7SYork Sun .n_col_addr = 10, 30b5b06fb7SYork Sun .n_banks_per_sdram_device = 8, 31b5b06fb7SYork Sun .edc_config = 2, /* ECC */ 32b5b06fb7SYork Sun .burst_lengths_bitmask = 0x0c, 33b5b06fb7SYork Sun 34b5b06fb7SYork Sun .tCKmin_X_ps = 1071, 35b5b06fb7SYork Sun .caslat_X = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ 36b5b06fb7SYork Sun .tAA_ps = 13910, 37b5b06fb7SYork Sun .tWR_ps = 15000, 38b5b06fb7SYork Sun .tRCD_ps = 13910, 39b5b06fb7SYork Sun .tRRD_ps = 6000, 40b5b06fb7SYork Sun .tRP_ps = 13910, 41b5b06fb7SYork Sun .tRAS_ps = 34000, 42b5b06fb7SYork Sun .tRC_ps = 48910, 43b5b06fb7SYork Sun .tRFC_ps = 260000, 44b5b06fb7SYork Sun .tWTR_ps = 7500, 45b5b06fb7SYork Sun .tRTP_ps = 7500, 46b5b06fb7SYork Sun .refresh_rate_ps = 7800000, 47b5b06fb7SYork Sun .tFAW_ps = 35000, 48b5b06fb7SYork Sun }; 49b5b06fb7SYork Sun 50b5b06fb7SYork Sun int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 51b5b06fb7SYork Sun unsigned int controller_number, 52b5b06fb7SYork Sun unsigned int dimm_number) 53b5b06fb7SYork Sun { 54b5b06fb7SYork Sun const char dimm_model[] = "RAW timing DDR"; 55b5b06fb7SYork Sun 56b5b06fb7SYork Sun if ((controller_number == 0) && (dimm_number == 0)) { 57b5b06fb7SYork Sun memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 58b5b06fb7SYork Sun memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 59b5b06fb7SYork Sun memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 60b5b06fb7SYork Sun } 61b5b06fb7SYork Sun 62b5b06fb7SYork Sun return 0; 63b5b06fb7SYork Sun } 64b5b06fb7SYork Sun 65b5b06fb7SYork Sun struct board_specific_parameters { 66b5b06fb7SYork Sun u32 n_ranks; 67b5b06fb7SYork Sun u32 datarate_mhz_high; 68b5b06fb7SYork Sun u32 clk_adjust; 69b5b06fb7SYork Sun u32 wrlvl_start; 70b5b06fb7SYork Sun u32 wrlvl_ctl_2; 71b5b06fb7SYork Sun u32 wrlvl_ctl_3; 72b5b06fb7SYork Sun u32 cpo; 73b5b06fb7SYork Sun u32 write_data_delay; 74b5b06fb7SYork Sun u32 force_2T; 75b5b06fb7SYork Sun }; 76b5b06fb7SYork Sun 77b5b06fb7SYork Sun /* 78b5b06fb7SYork Sun * This table contains all valid speeds we want to override with board 79b5b06fb7SYork Sun * specific parameters. datarate_mhz_high values need to be in ascending order 80b5b06fb7SYork Sun * for each n_ranks group. 81b5b06fb7SYork Sun */ 82b5b06fb7SYork Sun static const struct board_specific_parameters udimm0[] = { 83b5b06fb7SYork Sun /* 84b5b06fb7SYork Sun * memory controller 0 85b5b06fb7SYork Sun * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 86b5b06fb7SYork Sun * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | 87b5b06fb7SYork Sun */ 88b5b06fb7SYork Sun {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, 89b5b06fb7SYork Sun {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, 90b5b06fb7SYork Sun {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, 91b5b06fb7SYork Sun {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, 92b5b06fb7SYork Sun {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, 93b5b06fb7SYork Sun {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, 94b5b06fb7SYork Sun {} 95b5b06fb7SYork Sun }; 96b5b06fb7SYork Sun 97b5b06fb7SYork Sun static const struct board_specific_parameters *udimms[] = { 98b5b06fb7SYork Sun udimm0, 99b5b06fb7SYork Sun }; 100b5b06fb7SYork Sun 101b5b06fb7SYork Sun void fsl_ddr_board_options(memctl_options_t *popts, 102b5b06fb7SYork Sun dimm_params_t *pdimm, 103b5b06fb7SYork Sun unsigned int ctrl_num) 104b5b06fb7SYork Sun { 105b5b06fb7SYork Sun const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 106b5b06fb7SYork Sun ulong ddr_freq; 107b5b06fb7SYork Sun 108b5b06fb7SYork Sun if (ctrl_num > 2) { 109b5b06fb7SYork Sun printf("Not supported controller number %d\n", ctrl_num); 110b5b06fb7SYork Sun return; 111b5b06fb7SYork Sun } 112b5b06fb7SYork Sun if (!pdimm->n_ranks) 113b5b06fb7SYork Sun return; 114b5b06fb7SYork Sun 115b5b06fb7SYork Sun pbsp = udimms[0]; 116b5b06fb7SYork Sun 117b5b06fb7SYork Sun 118b5b06fb7SYork Sun /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr 119b5b06fb7SYork Sun * freqency and n_banks specified in board_specific_parameters table. 120b5b06fb7SYork Sun */ 121b5b06fb7SYork Sun ddr_freq = get_ddr_freq(0) / 1000000; 122b5b06fb7SYork Sun while (pbsp->datarate_mhz_high) { 123b5b06fb7SYork Sun if (pbsp->n_ranks == pdimm->n_ranks) { 124b5b06fb7SYork Sun if (ddr_freq <= pbsp->datarate_mhz_high) { 125b5b06fb7SYork Sun popts->cpo_override = pbsp->cpo; 126b5b06fb7SYork Sun popts->write_data_delay = 127b5b06fb7SYork Sun pbsp->write_data_delay; 128b5b06fb7SYork Sun popts->clk_adjust = pbsp->clk_adjust; 129b5b06fb7SYork Sun popts->wrlvl_start = pbsp->wrlvl_start; 130b5b06fb7SYork Sun popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 131b5b06fb7SYork Sun popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 132b5b06fb7SYork Sun popts->twoT_en = pbsp->force_2T; 133b5b06fb7SYork Sun goto found; 134b5b06fb7SYork Sun } 135b5b06fb7SYork Sun pbsp_highest = pbsp; 136b5b06fb7SYork Sun } 137b5b06fb7SYork Sun pbsp++; 138b5b06fb7SYork Sun } 139b5b06fb7SYork Sun 140b5b06fb7SYork Sun if (pbsp_highest) { 141b5b06fb7SYork Sun printf("Error: board specific timing not found " 142b5b06fb7SYork Sun "for data rate %lu MT/s\n" 143b5b06fb7SYork Sun "Trying to use the highest speed (%u) parameters\n", 144b5b06fb7SYork Sun ddr_freq, pbsp_highest->datarate_mhz_high); 145b5b06fb7SYork Sun popts->cpo_override = pbsp_highest->cpo; 146b5b06fb7SYork Sun popts->write_data_delay = pbsp_highest->write_data_delay; 147b5b06fb7SYork Sun popts->clk_adjust = pbsp_highest->clk_adjust; 148b5b06fb7SYork Sun popts->wrlvl_start = pbsp_highest->wrlvl_start; 149b5b06fb7SYork Sun popts->twoT_en = pbsp_highest->force_2T; 150b5b06fb7SYork Sun } else { 151b5b06fb7SYork Sun panic("DIMM is not supported by this board"); 152b5b06fb7SYork Sun } 153b5b06fb7SYork Sun found: 154b5b06fb7SYork Sun /* 155b5b06fb7SYork Sun * Factors to consider for half-strength driver enable: 156b5b06fb7SYork Sun * - number of DIMMs installed 157b5b06fb7SYork Sun */ 158b5b06fb7SYork Sun popts->half_strength_driver_enable = 0; 159b5b06fb7SYork Sun /* 160b5b06fb7SYork Sun * Write leveling override 161b5b06fb7SYork Sun */ 162b5b06fb7SYork Sun popts->wrlvl_override = 1; 163b5b06fb7SYork Sun popts->wrlvl_sample = 0xf; 164b5b06fb7SYork Sun 165b5b06fb7SYork Sun /* 166b5b06fb7SYork Sun * Rtt and Rtt_WR override 167b5b06fb7SYork Sun */ 168b5b06fb7SYork Sun popts->rtt_override = 0; 169b5b06fb7SYork Sun 170b5b06fb7SYork Sun /* Enable ZQ calibration */ 171b5b06fb7SYork Sun popts->zq_en = 1; 172b5b06fb7SYork Sun 173b5b06fb7SYork Sun /* DHC_EN =1, ODT = 75 Ohm */ 174b5b06fb7SYork Sun popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 175b5b06fb7SYork Sun popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 176b5b06fb7SYork Sun } 177b5b06fb7SYork Sun 178b5b06fb7SYork Sun phys_size_t initdram(int board_type) 179b5b06fb7SYork Sun { 180b5b06fb7SYork Sun phys_size_t dram_size; 181b5b06fb7SYork Sun 182b5b06fb7SYork Sun puts("Initializing....using SPD\n"); 183b5b06fb7SYork Sun 184b5b06fb7SYork Sun dram_size = fsl_ddr_sdram(); 185b5b06fb7SYork Sun 186b5b06fb7SYork Sun dram_size = setup_ddr_tlbs(dram_size / 0x100000); 187b5b06fb7SYork Sun dram_size *= 0x100000; 188b5b06fb7SYork Sun 189b5b06fb7SYork Sun puts(" DDR: "); 190b5b06fb7SYork Sun return dram_size; 191b5b06fb7SYork Sun } 192*43104795SYork Sun 193*43104795SYork Sun unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo, 194*43104795SYork Sun unsigned int dbw_cap_adj[]) 195*43104795SYork Sun { 196*43104795SYork Sun int i, j; 197*43104795SYork Sun unsigned long long total_mem, current_mem_base, total_ctlr_mem; 198*43104795SYork Sun unsigned long long rank_density, ctlr_density = 0; 199*43104795SYork Sun 200*43104795SYork Sun current_mem_base = 0ull; 201*43104795SYork Sun total_mem = 0; 202*43104795SYork Sun /* 203*43104795SYork Sun * This board has soldered DDR chips. DDRC1 has two rank. 204*43104795SYork Sun * DDRC2 has only one rank. 205*43104795SYork Sun * Assigning DDRC2 to lower address and DDRC1 to higher address. 206*43104795SYork Sun */ 207*43104795SYork Sun if (pinfo->memctl_opts[0].memctl_interleaving) { 208*43104795SYork Sun rank_density = pinfo->dimm_params[0][0].rank_density >> 209*43104795SYork Sun dbw_cap_adj[0]; 210*43104795SYork Sun ctlr_density = rank_density; 211*43104795SYork Sun 212*43104795SYork Sun debug("rank density is 0x%llx, ctlr density is 0x%llx\n", 213*43104795SYork Sun rank_density, ctlr_density); 214*43104795SYork Sun for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { 215*43104795SYork Sun switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { 216*43104795SYork Sun case FSL_DDR_CACHE_LINE_INTERLEAVING: 217*43104795SYork Sun case FSL_DDR_PAGE_INTERLEAVING: 218*43104795SYork Sun case FSL_DDR_BANK_INTERLEAVING: 219*43104795SYork Sun case FSL_DDR_SUPERBANK_INTERLEAVING: 220*43104795SYork Sun total_ctlr_mem = 2 * ctlr_density; 221*43104795SYork Sun break; 222*43104795SYork Sun default: 223*43104795SYork Sun panic("Unknown interleaving mode"); 224*43104795SYork Sun } 225*43104795SYork Sun pinfo->common_timing_params[i].base_address = 226*43104795SYork Sun current_mem_base; 227*43104795SYork Sun pinfo->common_timing_params[i].total_mem = 228*43104795SYork Sun total_ctlr_mem; 229*43104795SYork Sun total_mem = current_mem_base + total_ctlr_mem; 230*43104795SYork Sun debug("ctrl %d base 0x%llx\n", i, current_mem_base); 231*43104795SYork Sun debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 232*43104795SYork Sun } 233*43104795SYork Sun } else { 234*43104795SYork Sun /* 235*43104795SYork Sun * Simple linear assignment if memory 236*43104795SYork Sun * controllers are not interleaved. 237*43104795SYork Sun */ 238*43104795SYork Sun for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) { 239*43104795SYork Sun total_ctlr_mem = 0; 240*43104795SYork Sun pinfo->common_timing_params[i].base_address = 241*43104795SYork Sun current_mem_base; 242*43104795SYork Sun for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { 243*43104795SYork Sun /* Compute DIMM base addresses. */ 244*43104795SYork Sun unsigned long long cap = 245*43104795SYork Sun pinfo->dimm_params[i][j].capacity; 246*43104795SYork Sun pinfo->dimm_params[i][j].base_address = 247*43104795SYork Sun current_mem_base; 248*43104795SYork Sun debug("ctrl %d dimm %d base 0x%llx\n", 249*43104795SYork Sun i, j, current_mem_base); 250*43104795SYork Sun current_mem_base += cap; 251*43104795SYork Sun total_ctlr_mem += cap; 252*43104795SYork Sun } 253*43104795SYork Sun debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem); 254*43104795SYork Sun pinfo->common_timing_params[i].total_mem = 255*43104795SYork Sun total_ctlr_mem; 256*43104795SYork Sun total_mem += total_ctlr_mem; 257*43104795SYork Sun } 258*43104795SYork Sun } 259*43104795SYork Sun debug("Total mem by %s is 0x%llx\n", __func__, total_mem); 260*43104795SYork Sun 261*43104795SYork Sun return total_mem; 262*43104795SYork Sun } 263