1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (c) 2017 Tuomas Tynkkynen
4  */
5 #include <common.h>
6 #include <fdtdec.h>
7 
8 #ifdef CONFIG_ARM64
9 #include <asm/armv8/mmu.h>
10 
11 static struct mm_region qemu_arm64_mem_map[] = {
12 	{
13 		/* Flash */
14 		.virt = 0x00000000UL,
15 		.phys = 0x00000000UL,
16 		.size = 0x08000000UL,
17 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
18 			 PTE_BLOCK_INNER_SHARE
19 	}, {
20 		/* Lowmem peripherals */
21 		.virt = 0x08000000UL,
22 		.phys = 0x08000000UL,
23 		.size = 0x38000000,
24 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
25 			 PTE_BLOCK_NON_SHARE |
26 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
27 	}, {
28 		/* RAM */
29 		.virt = 0x40000000UL,
30 		.phys = 0x40000000UL,
31 		.size = 255UL * SZ_1G,
32 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
33 			 PTE_BLOCK_INNER_SHARE
34 	}, {
35 		/* Highmem PCI-E ECAM memory area */
36 		.virt = 0x4010000000ULL,
37 		.phys = 0x4010000000ULL,
38 		.size = 0x10000000,
39 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
40 			 PTE_BLOCK_NON_SHARE |
41 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
42 	}, {
43 		/* Highmem PCI-E MMIO memory area */
44 		.virt = 0x8000000000ULL,
45 		.phys = 0x8000000000ULL,
46 		.size = 0x8000000000ULL,
47 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
48 			 PTE_BLOCK_NON_SHARE |
49 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
50 	}, {
51 		/* List terminator */
52 		0,
53 	}
54 };
55 
56 struct mm_region *mem_map = qemu_arm64_mem_map;
57 #endif
58 
59 int board_init(void)
60 {
61 	return 0;
62 }
63 
64 int dram_init(void)
65 {
66 	if (fdtdec_setup_mem_size_base() != 0)
67 		return -EINVAL;
68 
69 	return 0;
70 }
71 
72 int dram_init_banksize(void)
73 {
74 	fdtdec_setup_memory_banksize();
75 
76 	return 0;
77 }
78 
79 void *board_fdt_blob_setup(void)
80 {
81 	/* QEMU loads a generated DTB for us at the start of RAM. */
82 	return (void *)CONFIG_SYS_SDRAM_BASE;
83 }
84