1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2017 Tuomas Tynkkynen
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <fdtdec.h>
9 #include <virtio_types.h>
10 #include <virtio.h>
11
12 #ifdef CONFIG_ARM64
13 #include <asm/armv8/mmu.h>
14
15 static struct mm_region qemu_arm64_mem_map[] = {
16 {
17 /* Flash */
18 .virt = 0x00000000UL,
19 .phys = 0x00000000UL,
20 .size = 0x08000000UL,
21 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
22 PTE_BLOCK_INNER_SHARE
23 }, {
24 /* Lowmem peripherals */
25 .virt = 0x08000000UL,
26 .phys = 0x08000000UL,
27 .size = 0x38000000,
28 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
29 PTE_BLOCK_NON_SHARE |
30 PTE_BLOCK_PXN | PTE_BLOCK_UXN
31 }, {
32 /* RAM */
33 .virt = 0x40000000UL,
34 .phys = 0x40000000UL,
35 .size = 255UL * SZ_1G,
36 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
37 PTE_BLOCK_INNER_SHARE
38 }, {
39 /* Highmem PCI-E ECAM memory area */
40 .virt = 0x4010000000ULL,
41 .phys = 0x4010000000ULL,
42 .size = 0x10000000,
43 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
44 PTE_BLOCK_NON_SHARE |
45 PTE_BLOCK_PXN | PTE_BLOCK_UXN
46 }, {
47 /* Highmem PCI-E MMIO memory area */
48 .virt = 0x8000000000ULL,
49 .phys = 0x8000000000ULL,
50 .size = 0x8000000000ULL,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
52 PTE_BLOCK_NON_SHARE |
53 PTE_BLOCK_PXN | PTE_BLOCK_UXN
54 }, {
55 /* List terminator */
56 0,
57 }
58 };
59
60 struct mm_region *mem_map = qemu_arm64_mem_map;
61 #endif
62
board_init(void)63 int board_init(void)
64 {
65 /*
66 * Make sure virtio bus is enumerated so that peripherals
67 * on the virtio bus can be discovered by their drivers
68 */
69 virtio_init();
70
71 return 0;
72 }
73
dram_init(void)74 int dram_init(void)
75 {
76 if (fdtdec_setup_mem_size_base() != 0)
77 return -EINVAL;
78
79 return 0;
80 }
81
dram_init_banksize(void)82 int dram_init_banksize(void)
83 {
84 fdtdec_setup_memory_banksize();
85
86 return 0;
87 }
88
board_fdt_blob_setup(void)89 void *board_fdt_blob_setup(void)
90 {
91 /* QEMU loads a generated DTB for us at the start of RAM. */
92 return (void *)CONFIG_SYS_SDRAM_BASE;
93 }
94