1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * board.c 4 * 5 * (C) Copyright 2016 6 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 7 * 8 * Based on: 9 * Board functions for TI AM335X based boards 10 * 11 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 12 */ 13 14 #include <common.h> 15 #include <errno.h> 16 #include <spl.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/omap.h> 20 #include <asm/arch/ddr_defs.h> 21 #include <asm/arch/clock.h> 22 #include <asm/arch/gpio.h> 23 #include <asm/arch/mmc_host_def.h> 24 #include <asm/arch/sys_proto.h> 25 #include <asm/arch/mem.h> 26 #include <asm/io.h> 27 #include <asm/emif.h> 28 #include <asm/gpio.h> 29 #include <i2c.h> 30 #include <miiphy.h> 31 #include <cpsw.h> 32 #include <power/tps65217.h> 33 #include <environment.h> 34 #include <watchdog.h> 35 #include <environment.h> 36 #include "mmc.h" 37 #include "board.h" 38 39 DECLARE_GLOBAL_DATA_PTR; 40 41 static struct shc_eeprom __attribute__((section(".data"))) header; 42 static int shc_eeprom_valid; 43 44 /* 45 * Read header information from EEPROM into global structure. 46 */ 47 static int read_eeprom(void) 48 { 49 /* Check if baseboard eeprom is available */ 50 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 51 puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); 52 return -ENODEV; 53 } 54 55 /* read the eeprom using i2c */ 56 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header, 57 sizeof(header))) { 58 puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); 59 return -EIO; 60 } 61 62 if (header.magic != HDR_MAGIC) { 63 printf("Incorrect magic number (0x%x) in EEPROM\n", 64 header.magic); 65 return -EIO; 66 } 67 68 shc_eeprom_valid = 1; 69 70 return 0; 71 } 72 73 static void shc_request_gpio(void) 74 { 75 gpio_request(LED_PWR_BL_GPIO, "LED PWR BL"); 76 gpio_request(LED_PWR_RD_GPIO, "LED PWR RD"); 77 gpio_request(RESET_GPIO, "reset"); 78 gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN"); 79 gpio_request(WIFI_RST_GPIO, "WIFI rst"); 80 gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst"); 81 gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst"); 82 gpio_request(ENOC_RST_GPIO, "ENOC rst"); 83 #if defined CONFIG_B_SAMPLE 84 gpio_request(LED_PWR_GN_GPIO, "LED PWR GN"); 85 gpio_request(LED_CONN_BL_GPIO, "LED CONN BL"); 86 gpio_request(LED_CONN_RD_GPIO, "LED CONN RD"); 87 gpio_request(LED_CONN_GN_GPIO, "LED CONN GN"); 88 #else 89 gpio_request(LED_LAN_BL_GPIO, "LED LAN BL"); 90 gpio_request(LED_LAN_RD_GPIO, "LED LAN RD"); 91 gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL"); 92 gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD"); 93 gpio_request(LED_PWM_GPIO, "LED PWM"); 94 gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst"); 95 #endif 96 gpio_request(BACK_BUTTON_GPIO, "Back button"); 97 gpio_request(FRONT_BUTTON_GPIO, "Front button"); 98 } 99 100 /* 101 * Function which forces all installed modules into running state for ICT 102 * testing. Called by SPL. 103 */ 104 static void __maybe_unused force_modules_running(void) 105 { 106 /* Wi-Fi power regulator enable - high = enabled */ 107 gpio_direction_output(WIFI_REGEN_GPIO, 1); 108 /* 109 * Wait for Wi-Fi power regulator to reach a stable voltage 110 * (soft-start time, max. 350 µs) 111 */ 112 __udelay(350); 113 114 /* Wi-Fi module reset - high = running */ 115 gpio_direction_output(WIFI_RST_GPIO, 1); 116 117 /* ZigBee reset - high = running */ 118 gpio_direction_output(ZIGBEE_RST_GPIO, 1); 119 120 /* BidCos reset - high = running */ 121 gpio_direction_output(BIDCOS_RST_GPIO, 1); 122 123 #if !defined(CONFIG_B_SAMPLE) 124 /* Z-Wave reset - high = running */ 125 gpio_direction_output(Z_WAVE_RST_GPIO, 1); 126 #endif 127 128 /* EnOcean reset - low = running */ 129 gpio_direction_output(ENOC_RST_GPIO, 0); 130 } 131 132 /* 133 * Function which forces all installed modules into reset - to be released by 134 * the OS, called by SPL 135 */ 136 static void __maybe_unused force_modules_reset(void) 137 { 138 /* Wi-Fi module reset - low = reset */ 139 gpio_direction_output(WIFI_RST_GPIO, 0); 140 141 /* Wi-Fi power regulator enable - low = disabled */ 142 gpio_direction_output(WIFI_REGEN_GPIO, 0); 143 144 /* ZigBee reset - low = reset */ 145 gpio_direction_output(ZIGBEE_RST_GPIO, 0); 146 147 /* BidCos reset - low = reset */ 148 /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/ 149 150 #if !defined(CONFIG_B_SAMPLE) 151 /* Z-Wave reset - low = reset */ 152 gpio_direction_output(Z_WAVE_RST_GPIO, 0); 153 #endif 154 155 /* EnOcean reset - high = reset*/ 156 gpio_direction_output(ENOC_RST_GPIO, 1); 157 } 158 159 /* 160 * Function to set the LEDs in the state "Bootloader booting" 161 */ 162 static void __maybe_unused leds_set_booting(void) 163 { 164 #if defined(CONFIG_B_SAMPLE) 165 166 /* Turn all red LEDs on */ 167 gpio_direction_output(LED_PWR_RD_GPIO, 1); 168 gpio_direction_output(LED_CONN_RD_GPIO, 1); 169 170 #else /* All other SHCs starting with B2-Sample */ 171 /* Set the PWM GPIO */ 172 gpio_direction_output(LED_PWM_GPIO, 1); 173 /* Turn all red LEDs on */ 174 gpio_direction_output(LED_PWR_RD_GPIO, 1); 175 gpio_direction_output(LED_LAN_RD_GPIO, 1); 176 gpio_direction_output(LED_CLOUD_RD_GPIO, 1); 177 178 #endif 179 } 180 181 /* 182 * Function to set the LEDs in the state "Bootloader error" 183 */ 184 static void leds_set_failure(int state) 185 { 186 #if defined(CONFIG_B_SAMPLE) 187 /* Turn all blue and green LEDs off */ 188 gpio_set_value(LED_PWR_BL_GPIO, 0); 189 gpio_set_value(LED_PWR_GN_GPIO, 0); 190 gpio_set_value(LED_CONN_BL_GPIO, 0); 191 gpio_set_value(LED_CONN_GN_GPIO, 0); 192 193 /* Turn all red LEDs to 'state' */ 194 gpio_set_value(LED_PWR_RD_GPIO, state); 195 gpio_set_value(LED_CONN_RD_GPIO, state); 196 197 #else /* All other SHCs starting with B2-Sample */ 198 /* Set the PWM GPIO */ 199 gpio_direction_output(LED_PWM_GPIO, 1); 200 201 /* Turn all blue LEDs off */ 202 gpio_set_value(LED_PWR_BL_GPIO, 0); 203 gpio_set_value(LED_LAN_BL_GPIO, 0); 204 gpio_set_value(LED_CLOUD_BL_GPIO, 0); 205 206 /* Turn all red LEDs to 'state' */ 207 gpio_set_value(LED_PWR_RD_GPIO, state); 208 gpio_set_value(LED_LAN_RD_GPIO, state); 209 gpio_set_value(LED_CLOUD_RD_GPIO, state); 210 #endif 211 } 212 213 /* 214 * Function to set the LEDs in the state "Bootloader finished" 215 */ 216 static void leds_set_finish(void) 217 { 218 #if defined(CONFIG_B_SAMPLE) 219 /* Turn all LEDs off */ 220 gpio_set_value(LED_PWR_BL_GPIO, 0); 221 gpio_set_value(LED_PWR_RD_GPIO, 0); 222 gpio_set_value(LED_PWR_GN_GPIO, 0); 223 gpio_set_value(LED_CONN_BL_GPIO, 0); 224 gpio_set_value(LED_CONN_RD_GPIO, 0); 225 gpio_set_value(LED_CONN_GN_GPIO, 0); 226 #else /* All other SHCs starting with B2-Sample */ 227 /* Turn all LEDs off */ 228 gpio_set_value(LED_PWR_BL_GPIO, 0); 229 gpio_set_value(LED_PWR_RD_GPIO, 0); 230 gpio_set_value(LED_LAN_BL_GPIO, 0); 231 gpio_set_value(LED_LAN_RD_GPIO, 0); 232 gpio_set_value(LED_CLOUD_BL_GPIO, 0); 233 gpio_set_value(LED_CLOUD_RD_GPIO, 0); 234 235 /* Turn off the PWM GPIO and mux it to EHRPWM */ 236 gpio_set_value(LED_PWM_GPIO, 0); 237 enable_shc_board_pwm_pin_mux(); 238 #endif 239 } 240 241 static void check_button_status(void) 242 { 243 ulong value; 244 gpio_direction_input(FRONT_BUTTON_GPIO); 245 value = gpio_get_value(FRONT_BUTTON_GPIO); 246 247 if (value == 0) { 248 printf("front button activated !\n"); 249 env_set("harakiri", "1"); 250 } 251 } 252 253 #if defined(CONFIG_SPL_BUILD) 254 #ifdef CONFIG_SPL_OS_BOOT 255 int spl_start_uboot(void) 256 { 257 return 1; 258 } 259 #endif 260 261 static void shc_board_early_init(void) 262 { 263 shc_request_gpio(); 264 # ifdef CONFIG_SHC_ICT 265 /* Force all modules into enabled state for ICT testing */ 266 force_modules_running(); 267 # else 268 /* Force all modules to enter Reset state until released by the OS */ 269 force_modules_reset(); 270 # endif 271 leds_set_booting(); 272 } 273 274 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 275 276 #define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */ 277 #define OSC (V_OSCK/1000000) 278 /* Bosch: Predivider must be fixed to 4, so N = 4-1 */ 279 #define MPUPLL_N (4-1) 280 /* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */ 281 #define MPUPLL_FREF (OSC / (MPUPLL_N + 1)) 282 283 const struct dpll_params dpll_ddr_shc = { 284 400, OSC-1, 1, -1, -1, -1, -1}; 285 286 const struct dpll_params *get_dpll_ddr_params(void) 287 { 288 return &dpll_ddr_shc; 289 } 290 291 /* 292 * As we enabled downspread SSC with 1.8%, the values needed to be corrected 293 * such that the 20% overshoot will not lead to too high frequencies. 294 * In all cases, this is achieved by subtracting one from M (6 MHz less). 295 * Example: 600 MHz CPU 296 * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz 297 * 600 MHz - 6 MHz (1x Fref) = 594 MHz 298 * SSC: 594 MHz * 1.8% = 10.7 MHz SSC 299 * Overshoot: 10.7 MHz * 20 % = 2.2 MHz 300 * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK! 301 */ 302 const struct dpll_params dpll_mpu_shc_opp100 = { 303 99, MPUPLL_N, 1, -1, -1, -1, -1}; 304 305 void am33xx_spl_board_init(void) 306 { 307 int sil_rev; 308 int mpu_vdd; 309 310 puts(BOARD_ID_STR); 311 312 /* 313 * Set CORE Frequency to OPP100 314 * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100) 315 */ 316 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 317 318 sil_rev = readl(&cdev->deviceid) >> 28; 319 if (sil_rev < 2) { 320 puts("We do not support Silicon Revisions below 2.0!\n"); 321 return; 322 } 323 324 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 325 if (i2c_probe(TPS65217_CHIP_PM)) 326 return; 327 328 /* 329 * Retrieve the CPU max frequency by reading the efuse 330 * SHC-Default: 600 MHz 331 */ 332 switch (dpll_mpu_opp100.m) { 333 case MPUPLL_M_1000: 334 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 335 break; 336 case MPUPLL_M_800: 337 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 338 break; 339 case MPUPLL_M_720: 340 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV; 341 break; 342 case MPUPLL_M_600: 343 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV; 344 break; 345 case MPUPLL_M_300: 346 mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV; 347 break; 348 default: 349 puts("Cannot determine the frequency, failing!\n"); 350 return; 351 } 352 353 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 354 puts("tps65217_voltage_update failure\n"); 355 return; 356 } 357 358 /* Set MPU Frequency to what we detected */ 359 printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF); 360 printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF * 361 dpll_mpu_shc_opp100.m); 362 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100); 363 364 /* Enable Spread Spectrum for this freq to be clean on EMI side */ 365 set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE); 366 367 /* 368 * Using the default voltages for the PMIC (TPS65217D) 369 * LS1 = 1.8V (VDD_1V8) 370 * LS2 = 3.3V (VDD_3V3A) 371 * LDO1 = 1.8V (VIO and VRTC) 372 * LDO2 = 3.3V (VDD_3V3AUX) 373 */ 374 shc_board_early_init(); 375 } 376 377 void set_uart_mux_conf(void) 378 { 379 enable_uart0_pin_mux(); 380 } 381 382 void set_mux_conf_regs(void) 383 { 384 enable_shc_board_pin_mux(); 385 } 386 387 const struct ctrl_ioregs ioregs_evmsk = { 388 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 389 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 390 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 391 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 392 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 393 }; 394 395 static const struct ddr_data ddr3_shc_data = { 396 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 397 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 398 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 399 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 400 }; 401 402 static const struct cmd_control ddr3_shc_cmd_ctrl_data = { 403 .cmd0csratio = MT41K256M16HA125E_RATIO, 404 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 405 406 .cmd1csratio = MT41K256M16HA125E_RATIO, 407 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 408 409 .cmd2csratio = MT41K256M16HA125E_RATIO, 410 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 411 }; 412 413 static struct emif_regs ddr3_shc_emif_reg_data = { 414 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 415 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 416 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 417 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 418 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 419 .zq_config = MT41K256M16HA125E_ZQ_CFG, 420 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | 421 PHY_EN_DYN_PWRDN, 422 }; 423 424 void sdram_init(void) 425 { 426 /* Configure the DDR3 RAM */ 427 config_ddr(400, &ioregs_evmsk, &ddr3_shc_data, 428 &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0); 429 } 430 #endif 431 432 /* 433 * Basic board specific setup. Pinmux has been handled already. 434 */ 435 int board_init(void) 436 { 437 #if defined(CONFIG_HW_WATCHDOG) 438 hw_watchdog_init(); 439 #endif 440 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 441 if (read_eeprom() < 0) 442 puts("EEPROM Content Invalid.\n"); 443 444 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 445 #if defined(CONFIG_NOR) || defined(CONFIG_NAND) 446 gpmc_init(); 447 #endif 448 shc_request_gpio(); 449 450 return 0; 451 } 452 453 #ifdef CONFIG_BOARD_LATE_INIT 454 int board_late_init(void) 455 { 456 check_button_status(); 457 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 458 if (shc_eeprom_valid) 459 if (is_valid_ethaddr(header.mac_addr)) 460 eth_env_set_enetaddr("ethaddr", header.mac_addr); 461 #endif 462 463 return 0; 464 } 465 #endif 466 467 #if defined(CONFIG_USB_ETHER) && \ 468 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) 469 int board_eth_init(bd_t *bis) 470 { 471 return usb_eth_initialize(bis); 472 } 473 #endif 474 475 #ifdef CONFIG_SHOW_BOOT_PROGRESS 476 static void bosch_check_reset_pin(void) 477 { 478 if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) { 479 printf("Resetting ...\n"); 480 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0); 481 disable_interrupts(); 482 reset_cpu(0); 483 /*NOTREACHED*/ 484 } 485 } 486 487 static void hang_bosch(const char *cause, int code) 488 { 489 int lv; 490 491 gpio_direction_input(RESET_GPIO); 492 493 /* Enable reset pin interrupt on falling edge */ 494 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0); 495 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT); 496 enable_interrupts(); 497 498 puts(cause); 499 for (;;) { 500 for (lv = 0; lv < code; lv++) { 501 bosch_check_reset_pin(); 502 leds_set_failure(1); 503 __udelay(150 * 1000); 504 leds_set_failure(0); 505 __udelay(150 * 1000); 506 } 507 #if defined(BLINK_CODE) 508 __udelay(300 * 1000); 509 #endif 510 } 511 } 512 513 void show_boot_progress(int val) 514 { 515 switch (val) { 516 case BOOTSTAGE_ID_NEED_RESET: 517 hang_bosch("need reset", 4); 518 break; 519 } 520 } 521 522 void arch_preboot_os(void) 523 { 524 leds_set_finish(); 525 } 526 #endif 527