1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 */
5
6 #include <common.h>
7 #include <miiphy.h>
8 #include <netdev.h>
9 #include <asm/io.h>
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/soc.h>
12
13 DECLARE_GLOBAL_DATA_PTR;
14
15 /*
16 * Those values and defines are taken from the Marvell U-Boot version
17 * "u-boot-2013.01-2014_T2.0" for the board Armada 375 DB-88F6720
18 */
19 #define DB_88F6720_MPP0_7 0x00020020 /* SPI */
20 #define DB_88F6720_MPP8_15 0x22000022 /* SPI , I2C */
21 #define DB_88F6720_MPP16_23 0x22222222 /* UART, TDM*/
22 #define DB_88F6720_MPP24_31 0x33333333 /* SDIO, SPI1*/
23 #define DB_88F6720_MPP32_39 0x04403330 /* SPI1, External SMI */
24 #define DB_88F6720_MPP40_47 0x22002044 /* UART1, GE0, SATA0 LED */
25 #define DB_88F6720_MPP48_55 0x22222222 /* GE0 */
26 #define DB_88F6720_MPP56_63 0x04444422 /* GE0 , LED_MATRIX, GPIO */
27 #define DB_88F6720_MPP64_67 0x014 /* LED_MATRIX, SATA1 LED*/
28
29 #define DB_88F6720_GPP_OUT_ENA_LOW 0xFFFFFFFF
30 #define DB_88F6720_GPP_OUT_ENA_MID 0x7FFFFFFF
31 #define DB_88F6720_GPP_OUT_ENA_HIGH 0xFFFFFFFF
32 #define DB_88F6720_GPP_OUT_VAL_LOW 0x0
33 #define DB_88F6720_GPP_OUT_VAL_MID BIT(31) /* SATA Power output enable */
34 #define DB_88F6720_GPP_OUT_VAL_HIGH 0x0
35 #define DB_88F6720_GPP_POL_LOW 0x0
36 #define DB_88F6720_GPP_POL_MID 0x0
37 #define DB_88F6720_GPP_POL_HIGH 0x0
38
board_early_init_f(void)39 int board_early_init_f(void)
40 {
41 /* Configure MPP */
42 writel(DB_88F6720_MPP0_7, MVEBU_MPP_BASE + 0x00);
43 writel(DB_88F6720_MPP8_15, MVEBU_MPP_BASE + 0x04);
44 writel(DB_88F6720_MPP16_23, MVEBU_MPP_BASE + 0x08);
45 writel(DB_88F6720_MPP24_31, MVEBU_MPP_BASE + 0x0c);
46 writel(DB_88F6720_MPP32_39, MVEBU_MPP_BASE + 0x10);
47 writel(DB_88F6720_MPP40_47, MVEBU_MPP_BASE + 0x14);
48 writel(DB_88F6720_MPP48_55, MVEBU_MPP_BASE + 0x18);
49 writel(DB_88F6720_MPP56_63, MVEBU_MPP_BASE + 0x1c);
50 writel(DB_88F6720_MPP64_67, MVEBU_MPP_BASE + 0x20);
51
52 /* Configure GPIO */
53 /* Set GPP Out value */
54 writel(DB_88F6720_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
55 writel(DB_88F6720_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
56 writel(DB_88F6720_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
57
58 /* Set GPP Polarity */
59 writel(DB_88F6720_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
60 writel(DB_88F6720_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
61 writel(DB_88F6720_GPP_POL_HIGH, MVEBU_GPIO2_BASE + 0x0c);
62
63 /* Set GPP Out Enable */
64 writel(DB_88F6720_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
65 writel(DB_88F6720_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
66 writel(DB_88F6720_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
67
68 return 0;
69 }
70
board_init(void)71 int board_init(void)
72 {
73 /* adress of boot parameters */
74 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
75
76 return 0;
77 }
78
checkboard(void)79 int checkboard(void)
80 {
81 puts("Board: Marvell DB-88F6720\n");
82
83 return 0;
84 }
85
board_eth_init(bd_t * bis)86 int board_eth_init(bd_t *bis)
87 {
88 cpu_eth_init(bis); /* Built in controller(s) come first */
89 return pci_eth_init(bis);
90 }
91