1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2008 - 2013 Tensilica Inc.
4 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
5 */
6
7 #include <common.h>
8 #include <asm/cache.h>
9
10 /*
11 * We currently run always with caches enabled when running from memory.
12 * Xtensa version D or later will support changing cache behavior, so
13 * we could implement it if necessary.
14 */
15
dcache_status(void)16 int dcache_status(void)
17 {
18 return 1;
19 }
20
dcache_enable(void)21 void dcache_enable(void)
22 {
23 }
24
dcache_disable(void)25 void dcache_disable(void)
26 {
27 }
28
flush_cache(ulong start_addr,ulong size)29 void flush_cache(ulong start_addr, ulong size)
30 {
31 __flush_invalidate_dcache_range(start_addr, size);
32 __invalidate_icache_range(start_addr, size);
33 }
34
flush_dcache_all(void)35 void flush_dcache_all(void)
36 {
37 __flush_dcache_all();
38 __invalidate_icache_all();
39 }
40
flush_dcache_range(ulong start_addr,ulong end_addr)41 void flush_dcache_range(ulong start_addr, ulong end_addr)
42 {
43 __flush_invalidate_dcache_range(start_addr, end_addr - start_addr);
44 }
45
invalidate_dcache_range(ulong start,ulong stop)46 void invalidate_dcache_range(ulong start, ulong stop)
47 {
48 __invalidate_dcache_range(start, stop - start);
49 }
50
invalidate_dcache_all(void)51 void invalidate_dcache_all(void)
52 {
53 __invalidate_dcache_all();
54 }
55
invalidate_icache_all(void)56 void invalidate_icache_all(void)
57 {
58 __invalidate_icache_all();
59 }
60