1*fea25720SGraeme Russ /* 2*fea25720SGraeme Russ * (C) Copyright 2002 3*fea25720SGraeme Russ * Daniel Engstr�m, Omicron Ceti AB, daniel@omicron.se. 4*fea25720SGraeme Russ * 5*fea25720SGraeme Russ * See file CREDITS for list of people who contributed to this 6*fea25720SGraeme Russ * project. 7*fea25720SGraeme Russ * 8*fea25720SGraeme Russ * This program is free software; you can redistribute it and/or 9*fea25720SGraeme Russ * modify it under the terms of the GNU General Public License as 10*fea25720SGraeme Russ * published by the Free Software Foundation; either version 2 of 11*fea25720SGraeme Russ * the License, or (at your option) any later version. 12*fea25720SGraeme Russ * 13*fea25720SGraeme Russ * This program is distributed in the hope that it will be useful, 14*fea25720SGraeme Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*fea25720SGraeme Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*fea25720SGraeme Russ * GNU General Public License for more details. 17*fea25720SGraeme Russ * 18*fea25720SGraeme Russ * You should have received a copy of the GNU General Public License 19*fea25720SGraeme Russ * along with this program; if not, write to the Free Software 20*fea25720SGraeme Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*fea25720SGraeme Russ * MA 02111-1307 USA 22*fea25720SGraeme Russ */ 23*fea25720SGraeme Russ 24*fea25720SGraeme Russ /* i8259.h i8259 PIC Registers */ 25*fea25720SGraeme Russ 26*fea25720SGraeme Russ #ifndef _ASMI386_I8259_H_ 27*fea25720SGraeme Russ #define _ASMI386_I8959_H_ 1 28*fea25720SGraeme Russ 29*fea25720SGraeme Russ 30*fea25720SGraeme Russ /* PIC I/O mapped registers */ 31*fea25720SGraeme Russ 32*fea25720SGraeme Russ #define IRR 0x0 /* Interrupt Request Register */ 33*fea25720SGraeme Russ #define ISR 0x0 /* In-Service Register */ 34*fea25720SGraeme Russ #define ICW1 0x0 /* Initialization Control Word 1 */ 35*fea25720SGraeme Russ #define OCW2 0x0 /* Operation Control Word 2 */ 36*fea25720SGraeme Russ #define OCW3 0x0 /* Operation Control Word 3 */ 37*fea25720SGraeme Russ #define ICW2 0x1 /* Initialization Control Word 2 */ 38*fea25720SGraeme Russ #define ICW3 0x1 /* Initialization Control Word 3 */ 39*fea25720SGraeme Russ #define ICW4 0x1 /* Initialization Control Word 4 */ 40*fea25720SGraeme Russ #define IMR 0x1 /* Interrupt Mask Register */ 41*fea25720SGraeme Russ 42*fea25720SGraeme Russ /* bits for IRR, IMR, ISR and ICW3 */ 43*fea25720SGraeme Russ #define IR7 0x80 /* IR7 */ 44*fea25720SGraeme Russ #define IR6 0x40 /* IR6 */ 45*fea25720SGraeme Russ #define IR5 0x20 /* IR5 */ 46*fea25720SGraeme Russ #define IR4 0x10 /* IR4 */ 47*fea25720SGraeme Russ #define IR3 0x08 /* IR3 */ 48*fea25720SGraeme Russ #define IR2 0x04 /* IR2 */ 49*fea25720SGraeme Russ #define IR1 0x02 /* IR1 */ 50*fea25720SGraeme Russ #define IR0 0x01 /* IR0 */ 51*fea25720SGraeme Russ 52*fea25720SGraeme Russ /* bits for SEOI */ 53*fea25720SGraeme Russ #define SEOI_IR7 0x07 /* IR7 */ 54*fea25720SGraeme Russ #define SEOI_IR6 0x06 /* IR6 */ 55*fea25720SGraeme Russ #define SEOI_IR5 0x05 /* IR5 */ 56*fea25720SGraeme Russ #define SEOI_IR4 0x04 /* IR4 */ 57*fea25720SGraeme Russ #define SEOI_IR3 0x03 /* IR3 */ 58*fea25720SGraeme Russ #define SEOI_IR2 0x02 /* IR2 */ 59*fea25720SGraeme Russ #define SEOI_IR1 0x01 /* IR1 */ 60*fea25720SGraeme Russ #define SEOI_IR0 0x00 /* IR0 */ 61*fea25720SGraeme Russ 62*fea25720SGraeme Russ /* OCW2 bits */ 63*fea25720SGraeme Russ #define OCW2_RCLR 0x00 /* Rotate/clear */ 64*fea25720SGraeme Russ #define OCW2_NEOI 0x20 /* Non specific EOI */ 65*fea25720SGraeme Russ #define OCW2_NOP 0x40 /* NOP */ 66*fea25720SGraeme Russ #define OCW2_SEOI 0x60 /* Specific EOI */ 67*fea25720SGraeme Russ #define OCW2_RSET 0x80 /* Rotate/set */ 68*fea25720SGraeme Russ #define OCW2_REOI 0xA0 /* Rotate on non specific EOI */ 69*fea25720SGraeme Russ #define OCW2_PSET 0xC0 /* Priority Set Command */ 70*fea25720SGraeme Russ #define OCW2_RSEOI 0xE0 /* Rotate on specific EOI */ 71*fea25720SGraeme Russ 72*fea25720SGraeme Russ /* ICW1 bits */ 73*fea25720SGraeme Russ #define ICW1_SEL 0x10 /* Select ICW1 */ 74*fea25720SGraeme Russ #define ICW1_LTIM 0x08 /* Level-Triggered Interrupt Mode */ 75*fea25720SGraeme Russ #define ICW1_ADI 0x04 /* Address Interval */ 76*fea25720SGraeme Russ #define ICW1_SNGL 0x02 /* Single PIC */ 77*fea25720SGraeme Russ #define ICW1_EICW4 0x01 /* Expect initilization ICW4 */ 78*fea25720SGraeme Russ 79*fea25720SGraeme Russ /* ICW2 is the starting vector number */ 80*fea25720SGraeme Russ 81*fea25720SGraeme Russ /* ICW2 is bit-mask of present slaves for a master device, 82*fea25720SGraeme Russ * or the slave ID for a slave device */ 83*fea25720SGraeme Russ 84*fea25720SGraeme Russ /* ICW4 bits */ 85*fea25720SGraeme Russ #define ICW4_AEOI 0x02 /* Automatic EOI Mode */ 86*fea25720SGraeme Russ #define ICW4_PM 0x01 /* Microprocessor Mode */ 87*fea25720SGraeme Russ 88*fea25720SGraeme Russ #endif 89