1fea25720SGraeme Russ /* 2fea25720SGraeme Russ * (C) Copyright 2002 3fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. 4fea25720SGraeme Russ * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6fea25720SGraeme Russ */ 7fea25720SGraeme Russ 8fea25720SGraeme Russ /* i8259.h i8259 PIC Registers */ 9fea25720SGraeme Russ 10fea25720SGraeme Russ #ifndef _ASMI386_I8259_H_ 11*0a2ea020SBin Meng #define _ASMI386_I8959_H_ 12fea25720SGraeme Russ 13fea25720SGraeme Russ /* PIC I/O mapped registers */ 14fea25720SGraeme Russ #define IRR 0x0 /* Interrupt Request Register */ 15fea25720SGraeme Russ #define ISR 0x0 /* In-Service Register */ 16fea25720SGraeme Russ #define ICW1 0x0 /* Initialization Control Word 1 */ 17fea25720SGraeme Russ #define OCW2 0x0 /* Operation Control Word 2 */ 18fea25720SGraeme Russ #define OCW3 0x0 /* Operation Control Word 3 */ 19fea25720SGraeme Russ #define ICW2 0x1 /* Initialization Control Word 2 */ 20fea25720SGraeme Russ #define ICW3 0x1 /* Initialization Control Word 3 */ 21fea25720SGraeme Russ #define ICW4 0x1 /* Initialization Control Word 4 */ 22fea25720SGraeme Russ #define IMR 0x1 /* Interrupt Mask Register */ 23fea25720SGraeme Russ 24*0a2ea020SBin Meng /* IRR, IMR, ISR and ICW3 bits */ 25fea25720SGraeme Russ #define IR7 0x80 /* IR7 */ 26fea25720SGraeme Russ #define IR6 0x40 /* IR6 */ 27fea25720SGraeme Russ #define IR5 0x20 /* IR5 */ 28fea25720SGraeme Russ #define IR4 0x10 /* IR4 */ 29fea25720SGraeme Russ #define IR3 0x08 /* IR3 */ 30fea25720SGraeme Russ #define IR2 0x04 /* IR2 */ 31fea25720SGraeme Russ #define IR1 0x02 /* IR1 */ 32fea25720SGraeme Russ #define IR0 0x01 /* IR0 */ 33fea25720SGraeme Russ 34*0a2ea020SBin Meng /* SEOI bits */ 35fea25720SGraeme Russ #define SEOI_IR7 0x07 /* IR7 */ 36fea25720SGraeme Russ #define SEOI_IR6 0x06 /* IR6 */ 37fea25720SGraeme Russ #define SEOI_IR5 0x05 /* IR5 */ 38fea25720SGraeme Russ #define SEOI_IR4 0x04 /* IR4 */ 39fea25720SGraeme Russ #define SEOI_IR3 0x03 /* IR3 */ 40fea25720SGraeme Russ #define SEOI_IR2 0x02 /* IR2 */ 41fea25720SGraeme Russ #define SEOI_IR1 0x01 /* IR1 */ 42fea25720SGraeme Russ #define SEOI_IR0 0x00 /* IR0 */ 43fea25720SGraeme Russ 44fea25720SGraeme Russ /* OCW2 bits */ 45fea25720SGraeme Russ #define OCW2_RCLR 0x00 /* Rotate/clear */ 46fea25720SGraeme Russ #define OCW2_NEOI 0x20 /* Non specific EOI */ 47fea25720SGraeme Russ #define OCW2_NOP 0x40 /* NOP */ 48fea25720SGraeme Russ #define OCW2_SEOI 0x60 /* Specific EOI */ 49fea25720SGraeme Russ #define OCW2_RSET 0x80 /* Rotate/set */ 50*0a2ea020SBin Meng #define OCW2_REOI 0xa0 /* Rotate on non specific EOI */ 51*0a2ea020SBin Meng #define OCW2_PSET 0xc0 /* Priority Set Command */ 52*0a2ea020SBin Meng #define OCW2_RSEOI 0xe0 /* Rotate on specific EOI */ 53fea25720SGraeme Russ 54fea25720SGraeme Russ /* ICW1 bits */ 55fea25720SGraeme Russ #define ICW1_SEL 0x10 /* Select ICW1 */ 56fea25720SGraeme Russ #define ICW1_LTIM 0x08 /* Level-Triggered Interrupt Mode */ 57fea25720SGraeme Russ #define ICW1_ADI 0x04 /* Address Interval */ 58fea25720SGraeme Russ #define ICW1_SNGL 0x02 /* Single PIC */ 59fea25720SGraeme Russ #define ICW1_EICW4 0x01 /* Expect initilization ICW4 */ 60fea25720SGraeme Russ 61*0a2ea020SBin Meng /* 62*0a2ea020SBin Meng * ICW2 is the starting vector number 63*0a2ea020SBin Meng * 64*0a2ea020SBin Meng * ICW2 is bit-mask of present slaves for a master device, 65*0a2ea020SBin Meng * or the slave ID for a slave device 66*0a2ea020SBin Meng */ 67fea25720SGraeme Russ 68fea25720SGraeme Russ /* ICW4 bits */ 69fea25720SGraeme Russ #define ICW4_AEOI 0x02 /* Automatic EOI Mode */ 70fea25720SGraeme Russ #define ICW4_PM 0x01 /* Microprocessor Mode */ 71fea25720SGraeme Russ 72*0a2ea020SBin Meng #define ELCR1 0x4d0 73*0a2ea020SBin Meng #define ELCR2 0x4d1 74*0a2ea020SBin Meng 751dae2e0eSBin Meng int i8259_init(void); 761dae2e0eSBin Meng 77*0a2ea020SBin Meng #endif /* _ASMI386_I8959_H_ */ 78