xref: /openbmc/u-boot/arch/x86/include/asm/i8254.h (revision f4ef6668)
1 /*
2  * (C) Copyright 2002
3  * Daniel Engstr�m, Omicron Ceti AB, daniel@omicron.se.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 
25 /* i8254.h Intel 8254 PIT registers */
26 
27 
28 #ifndef _ASMI386_I8254_H_
29 #define _ASMI386_I8954_H_       1
30 
31 
32 #define PIT_T0		0x00		/* PIT channel 0 count/status */
33 #define PIT_T1		0x01		/* PIT channel 1 count/status */
34 #define PIT_T2		0x02		/* PIT channel 2 count/status */
35 #define PIT_COMMAND	0x03		/* PIT mode control, latch and read back */
36 
37 /* PIT Command Register Bit Definitions */
38 
39 #define PIT_CMD_CTR0	0x00		/* Select PIT counter 0 */
40 #define PIT_CMD_CTR1	0x40		/* Select PIT counter 1 */
41 #define PIT_CMD_CTR2	0x80		/* Select PIT counter 2 */
42 
43 #define PIT_CMD_LATCH	0x00		/* Counter Latch Command */
44 #define PIT_CMD_LOW	0x10		/* Access counter bits 7-0 */
45 #define PIT_CMD_HIGH	0x20		/* Access counter bits 15-8 */
46 #define PIT_CMD_BOTH	0x30		/* Access counter bits 15-0 in two accesses */
47 
48 #define PIT_CMD_MODE0	0x00		/* Select mode 0 */
49 #define PIT_CMD_MODE1	0x02		/* Select mode 1 */
50 #define PIT_CMD_MODE2	0x04		/* Select mode 2 */
51 #define PIT_CMD_MODE3	0x06		/* Select mode 3 */
52 #define PIT_CMD_MODE4	0x08		/* Select mode 4 */
53 #define PIT_CMD_MODE5	0x0A		/* Select mode 5 */
54 
55 #endif
56