1 /* 2 * (C) Copyright 2002 3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 9 /* i8254.h Intel 8254 PIT registers */ 10 11 12 #ifndef _ASMI386_I8254_H_ 13 #define _ASMI386_I8954_H_ 1 14 15 16 #define PIT_T0 0x00 /* PIT channel 0 count/status */ 17 #define PIT_T1 0x01 /* PIT channel 1 count/status */ 18 #define PIT_T2 0x02 /* PIT channel 2 count/status */ 19 #define PIT_COMMAND 0x03 /* PIT mode control, latch and read back */ 20 21 /* PIT Command Register Bit Definitions */ 22 23 #define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */ 24 #define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */ 25 #define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */ 26 27 #define PIT_CMD_LATCH 0x00 /* Counter Latch Command */ 28 #define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */ 29 #define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */ 30 #define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */ 31 32 #define PIT_CMD_MODE0 0x00 /* Select mode 0 */ 33 #define PIT_CMD_MODE1 0x02 /* Select mode 1 */ 34 #define PIT_CMD_MODE2 0x04 /* Select mode 2 */ 35 #define PIT_CMD_MODE3 0x06 /* Select mode 3 */ 36 #define PIT_CMD_MODE4 0x08 /* Select mode 4 */ 37 #define PIT_CMD_MODE5 0x0A /* Select mode 5 */ 38 39 /* The clock frequency of the i8253/i8254 PIT */ 40 #define PIT_TICK_RATE 1193182ul 41 42 #endif 43