1fea25720SGraeme Russ /* 2fea25720SGraeme Russ * (C) Copyright 2002 3*fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. 4fea25720SGraeme Russ * 5fea25720SGraeme Russ * See file CREDITS for list of people who contributed to this 6fea25720SGraeme Russ * project. 7fea25720SGraeme Russ * 8fea25720SGraeme Russ * This program is free software; you can redistribute it and/or 9fea25720SGraeme Russ * modify it under the terms of the GNU General Public License as 10fea25720SGraeme Russ * published by the Free Software Foundation; either version 2 of 11fea25720SGraeme Russ * the License, or (at your option) any later version. 12fea25720SGraeme Russ * 13fea25720SGraeme Russ * This program is distributed in the hope that it will be useful, 14fea25720SGraeme Russ * but WITHOUT ANY WARRANTY; without even the implied warranty of 15fea25720SGraeme Russ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16fea25720SGraeme Russ * GNU General Public License for more details. 17fea25720SGraeme Russ * 18fea25720SGraeme Russ * You should have received a copy of the GNU General Public License 19fea25720SGraeme Russ * along with this program; if not, write to the Free Software 20fea25720SGraeme Russ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21fea25720SGraeme Russ * MA 02111-1307 USA 22fea25720SGraeme Russ */ 23fea25720SGraeme Russ 24fea25720SGraeme Russ 25fea25720SGraeme Russ /* i8254.h Intel 8254 PIT registers */ 26fea25720SGraeme Russ 27fea25720SGraeme Russ 28fea25720SGraeme Russ #ifndef _ASMI386_I8254_H_ 29fea25720SGraeme Russ #define _ASMI386_I8954_H_ 1 30fea25720SGraeme Russ 31fea25720SGraeme Russ 32fea25720SGraeme Russ #define PIT_T0 0x00 /* PIT channel 0 count/status */ 33fea25720SGraeme Russ #define PIT_T1 0x01 /* PIT channel 1 count/status */ 34fea25720SGraeme Russ #define PIT_T2 0x02 /* PIT channel 2 count/status */ 35fea25720SGraeme Russ #define PIT_COMMAND 0x03 /* PIT mode control, latch and read back */ 36fea25720SGraeme Russ 37fea25720SGraeme Russ /* PIT Command Register Bit Definitions */ 38fea25720SGraeme Russ 39fea25720SGraeme Russ #define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */ 40fea25720SGraeme Russ #define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */ 41fea25720SGraeme Russ #define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */ 42fea25720SGraeme Russ 43fea25720SGraeme Russ #define PIT_CMD_LATCH 0x00 /* Counter Latch Command */ 44fea25720SGraeme Russ #define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */ 45fea25720SGraeme Russ #define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */ 46fea25720SGraeme Russ #define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */ 47fea25720SGraeme Russ 48fea25720SGraeme Russ #define PIT_CMD_MODE0 0x00 /* Select mode 0 */ 49fea25720SGraeme Russ #define PIT_CMD_MODE1 0x02 /* Select mode 1 */ 50fea25720SGraeme Russ #define PIT_CMD_MODE2 0x04 /* Select mode 2 */ 51fea25720SGraeme Russ #define PIT_CMD_MODE3 0x06 /* Select mode 3 */ 52fea25720SGraeme Russ #define PIT_CMD_MODE4 0x08 /* Select mode 4 */ 53fea25720SGraeme Russ #define PIT_CMD_MODE5 0x0A /* Select mode 5 */ 54fea25720SGraeme Russ 55fea25720SGraeme Russ #endif 56