1fea25720SGraeme Russ /* 2fea25720SGraeme Russ * (C) Copyright 2002 3fa82f871SAlbert ARIBAUD * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. 4fea25720SGraeme Russ * 51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6fea25720SGraeme Russ */ 7fea25720SGraeme Russ 8fea25720SGraeme Russ 9fea25720SGraeme Russ /* i8254.h Intel 8254 PIT registers */ 10fea25720SGraeme Russ 11fea25720SGraeme Russ 12fea25720SGraeme Russ #ifndef _ASMI386_I8254_H_ 13fea25720SGraeme Russ #define _ASMI386_I8954_H_ 1 14fea25720SGraeme Russ 15fea25720SGraeme Russ 16fea25720SGraeme Russ #define PIT_T0 0x00 /* PIT channel 0 count/status */ 17fea25720SGraeme Russ #define PIT_T1 0x01 /* PIT channel 1 count/status */ 18fea25720SGraeme Russ #define PIT_T2 0x02 /* PIT channel 2 count/status */ 19fea25720SGraeme Russ #define PIT_COMMAND 0x03 /* PIT mode control, latch and read back */ 20fea25720SGraeme Russ 21fea25720SGraeme Russ /* PIT Command Register Bit Definitions */ 22fea25720SGraeme Russ 23fea25720SGraeme Russ #define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */ 24fea25720SGraeme Russ #define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */ 25fea25720SGraeme Russ #define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */ 26fea25720SGraeme Russ 27fea25720SGraeme Russ #define PIT_CMD_LATCH 0x00 /* Counter Latch Command */ 28fea25720SGraeme Russ #define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */ 29fea25720SGraeme Russ #define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */ 30fea25720SGraeme Russ #define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */ 31fea25720SGraeme Russ 32fea25720SGraeme Russ #define PIT_CMD_MODE0 0x00 /* Select mode 0 */ 33fea25720SGraeme Russ #define PIT_CMD_MODE1 0x02 /* Select mode 1 */ 34fea25720SGraeme Russ #define PIT_CMD_MODE2 0x04 /* Select mode 2 */ 35fea25720SGraeme Russ #define PIT_CMD_MODE3 0x06 /* Select mode 3 */ 36fea25720SGraeme Russ #define PIT_CMD_MODE4 0x08 /* Select mode 4 */ 37fea25720SGraeme Russ #define PIT_CMD_MODE5 0x0A /* Select mode 5 */ 38fea25720SGraeme Russ 39*80de0495SBin Meng /* The clock frequency of the i8253/i8254 PIT */ 40*80de0495SBin Meng #define PIT_TICK_RATE 1193182ul 41*80de0495SBin Meng 42fea25720SGraeme Russ #endif 43