1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Google Inc. 4 */ 5 6 /* Core Clocks */ 7 #define PLL_DPLL 2 8 #define PLL_D2PLL 3 9 #define PLL_MPLL 4 10 11 12 /* Bus Clocks, derived from core clocks */ 13 #define BCLK_PCLK 101 14 #define BCLK_LHCLK 102 15 #define BCLK_MACCLK 103 16 #define BCLK_SDCLK 104 17 #define BCLK_ARMCLK 105 18 19 #define MCLK_DDR 201 20 21 /* Special clocks */ 22 #define PCLK_UART1 501 23 #define PCLK_UART2 502 24 #define PCLK_UART3 503 25 #define PCLK_UART4 504 26 #define PCLK_UART5 505 27 #define PCLK_MAC1 506 28 #define PCLK_MAC2 507 29 30 /* come from linux kernel */ 31 32 #define ASPEED_CLK_GATE_ECLK 0 33 #define ASPEED_CLK_GATE_GCLK 1 34 #define ASPEED_CLK_GATE_MCLK 2 35 #define ASPEED_CLK_GATE_VCLK 3 36 #define ASPEED_CLK_GATE_BCLK 4 37 #define ASPEED_CLK_GATE_DCLK 5 38 #define ASPEED_CLK_GATE_REFCLK 6 39 #define ASPEED_CLK_GATE_USBPORT2CLK 7 40 #define ASPEED_CLK_GATE_LCLK 8 41 #define ASPEED_CLK_GATE_USBUHCICLK 9 42 #define ASPEED_CLK_GATE_D1CLK 10 43 #define ASPEED_CLK_GATE_YCLK 11 44 #define ASPEED_CLK_GATE_USBPORT1CLK 12 45 #define ASPEED_CLK_GATE_UART1CLK 13 46 #define ASPEED_CLK_GATE_UART2CLK 14 47 #define ASPEED_CLK_GATE_UART5CLK 15 48 #define ASPEED_CLK_GATE_ESPICLK 16 49 #define ASPEED_CLK_GATE_MAC1CLK 17 50 #define ASPEED_CLK_GATE_MAC2CLK 18 51 #define ASPEED_CLK_GATE_RSACLK 19 52 #define ASPEED_CLK_GATE_UART3CLK 20 53 #define ASPEED_CLK_GATE_UART4CLK 21 54 #define ASPEED_CLK_GATE_SDCLK 22 55 #define ASPEED_CLK_GATE_LHCCLK 23 56 #define ASPEED_CLK_GATE_SDEXTCLK 24 57 #define ASPEED_CLK_HPLL 25 58 #define ASPEED_CLK_AHB 26 59 #define ASPEED_CLK_APB 27 60 #define ASPEED_CLK_UART 28 61 #define ASPEED_CLK_SDIO 29 62 #define ASPEED_CLK_ECLK 30 63 #define ASPEED_CLK_ECLK_MUX 31 64 #define ASPEED_CLK_LHCLK 32 65 #define ASPEED_CLK_MAC 33 66 #define ASPEED_CLK_BCLK 34 67 #define ASPEED_CLK_MPLL 35 68 #define ASPEED_CLK_24M 36 69 70