19604e92eSryan_chen /* SPDX-License-Identifier: GPL-2.0+ */ 29604e92eSryan_chen /* 39604e92eSryan_chen * Copyright 2016 Google Inc. 49604e92eSryan_chen */ 59604e92eSryan_chen 69604e92eSryan_chen /* Core Clocks */ 79604e92eSryan_chen #define PLL_DPLL 2 89604e92eSryan_chen #define PLL_D2PLL 3 99604e92eSryan_chen #define PLL_MPLL 4 109604e92eSryan_chen 119604e92eSryan_chen 129604e92eSryan_chen /* Bus Clocks, derived from core clocks */ 139604e92eSryan_chen #define BCLK_PCLK 101 149604e92eSryan_chen #define BCLK_LHCLK 102 159604e92eSryan_chen #define BCLK_MACCLK 103 169604e92eSryan_chen #define BCLK_SDCLK 104 179604e92eSryan_chen #define BCLK_ARMCLK 105 189604e92eSryan_chen 199604e92eSryan_chen #define MCLK_DDR 201 209604e92eSryan_chen 219604e92eSryan_chen /* Special clocks */ 229604e92eSryan_chen #define PCLK_UART1 501 239604e92eSryan_chen #define PCLK_UART2 502 249604e92eSryan_chen #define PCLK_UART3 503 259604e92eSryan_chen #define PCLK_UART4 504 269604e92eSryan_chen #define PCLK_UART5 505 279604e92eSryan_chen #define PCLK_MAC1 506 289604e92eSryan_chen #define PCLK_MAC2 507 29*d1e64dd1Sryan_chen 30*d1e64dd1Sryan_chen /* come from linux kernel */ 31*d1e64dd1Sryan_chen 32*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_ECLK 0 33*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_GCLK 1 34*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_MCLK 2 35*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_VCLK 3 36*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_BCLK 4 37*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_DCLK 5 38*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_REFCLK 6 39*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_USBPORT2CLK 7 40*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_LCLK 8 41*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_USBUHCICLK 9 42*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_D1CLK 10 43*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_YCLK 11 44*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_USBPORT1CLK 12 45*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART1CLK 13 46*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART2CLK 14 47*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART5CLK 15 48*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_ESPICLK 16 49*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_MAC1CLK 17 50*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_MAC2CLK 18 51*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_RSACLK 19 52*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART3CLK 20 53*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_UART4CLK 21 54*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_SDCLK 22 55*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_LHCCLK 23 56*d1e64dd1Sryan_chen #define ASPEED_CLK_GATE_SDEXTCLK 24 57*d1e64dd1Sryan_chen #define ASPEED_CLK_HPLL 25 58*d1e64dd1Sryan_chen #define ASPEED_CLK_AHB 26 59*d1e64dd1Sryan_chen #define ASPEED_CLK_APB 27 60*d1e64dd1Sryan_chen #define ASPEED_CLK_UART 28 61*d1e64dd1Sryan_chen #define ASPEED_CLK_SDIO 29 62*d1e64dd1Sryan_chen #define ASPEED_CLK_ECLK 30 63*d1e64dd1Sryan_chen #define ASPEED_CLK_ECLK_MUX 31 64*d1e64dd1Sryan_chen #define ASPEED_CLK_LHCLK 32 65*d1e64dd1Sryan_chen #define ASPEED_CLK_MAC 33 66*d1e64dd1Sryan_chen #define ASPEED_CLK_BCLK 34 67*d1e64dd1Sryan_chen #define ASPEED_CLK_MPLL 35 68*d1e64dd1Sryan_chen #define ASPEED_CLK_24M 36 69*d1e64dd1Sryan_chen 70