1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7config USE_PRIVATE_LIBGCC 8 default y 9 10choice 11 prompt "Target select" 12 13config TARGET_COREBOOT 14 bool "Support coreboot" 15 help 16 This target is used for running U-Boot on top of Coreboot. In 17 this case Coreboot does the early inititalisation, and U-Boot 18 takes over once the RAM, video and CPU are fully running. 19 U-Boot is loaded as a fallback payload from Coreboot, in 20 Coreboot terminology. This method was used for the Chromebook 21 Pixel when launched. 22 23config TARGET_CHROMEBOOK_LINK 24 bool "Support Chromebook link" 25 help 26 This is the Chromebook Pixel released in 2013. It uses an Intel 27 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of 28 SDRAM. It has a Panther Point platform controller hub, PCIe 29 WiFi and Bluetooth. It also includes a 720p webcam, USB SD 30 reader, microphone and speakers, display port and 32GB SATA 31 solid state drive. There is a Chrome OS EC connected on LPC, 32 and it provides a 2560x1700 high resolution touch-enabled LCD 33 display. 34 35config TARGET_CROWNBAY 36 bool "Support Intel Crown Bay CRB" 37 help 38 This is the Intel Crown Bay Customer Reference Board. It contains 39 the Intel Atom Processor E6xx populated on the COM Express module 40 with 1GB DDR2 soldered down memory and a carrier board with the 41 Intel Platform Controller Hub EG20T, other system components and 42 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. 43 44config TARGET_MINNOWMAX 45 bool "Support Intel Minnowboard MAX" 46 help 47 This is the Intel Minnowboard MAX. It contains an Atom E3800 48 processor in a small form factor with Ethernet, micro-SD, USB 2, 49 USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. 50 It requires some binary blobs - see README.x86 for details. 51 52 Note that PCIE_ECAM_BASE is set up by the FSP so the value used 53 by U-Boot matches that value. 54 55config TARGET_GALILEO 56 bool "Support Intel Galileo" 57 help 58 This is the Intel Galileo board, which is the first in a family of 59 Arduino-certified development and prototyping boards based on Intel 60 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit 61 single-core, single-thread, Intel Pentium processor instrunction set 62 architecture (ISA) compatible, operating at speeds up to 400Mhz, 63 along with 256MB DDR3 memory. It supports a wide range of industry 64 standard I/O interfaces, including a full-sized mini-PCIe slot, 65 one 100Mb Ethernet port, a microSD card slot, a USB host port and 66 a USB client port. 67 68endchoice 69 70config RAMBASE 71 hex 72 default 0x100000 73 74config XIP_ROM_SIZE 75 hex 76 depends on X86_RESET_VECTOR 77 default ROM_SIZE 78 79config CPU_ADDR_BITS 80 int 81 default 36 82 83config HPET_ADDRESS 84 hex 85 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 86 87config SMM_TSEG 88 bool 89 default n 90 91config SMM_TSEG_SIZE 92 hex 93 94config X86_RESET_VECTOR 95 bool 96 default n 97 98config SYS_X86_START16 99 hex 100 depends on X86_RESET_VECTOR 101 default 0xfffff800 102 103config BOARD_ROMSIZE_KB_512 104 bool 105config BOARD_ROMSIZE_KB_1024 106 bool 107config BOARD_ROMSIZE_KB_2048 108 bool 109config BOARD_ROMSIZE_KB_4096 110 bool 111config BOARD_ROMSIZE_KB_8192 112 bool 113config BOARD_ROMSIZE_KB_16384 114 bool 115 116choice 117 prompt "ROM chip size" 118 depends on X86_RESET_VECTOR 119 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 120 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 121 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 122 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 123 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 124 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 125 help 126 Select the size of the ROM chip you intend to flash U-Boot on. 127 128 The build system will take care of creating a u-boot.rom file 129 of the matching size. 130 131config UBOOT_ROMSIZE_KB_512 132 bool "512 KB" 133 help 134 Choose this option if you have a 512 KB ROM chip. 135 136config UBOOT_ROMSIZE_KB_1024 137 bool "1024 KB (1 MB)" 138 help 139 Choose this option if you have a 1024 KB (1 MB) ROM chip. 140 141config UBOOT_ROMSIZE_KB_2048 142 bool "2048 KB (2 MB)" 143 help 144 Choose this option if you have a 2048 KB (2 MB) ROM chip. 145 146config UBOOT_ROMSIZE_KB_4096 147 bool "4096 KB (4 MB)" 148 help 149 Choose this option if you have a 4096 KB (4 MB) ROM chip. 150 151config UBOOT_ROMSIZE_KB_8192 152 bool "8192 KB (8 MB)" 153 help 154 Choose this option if you have a 8192 KB (8 MB) ROM chip. 155 156config UBOOT_ROMSIZE_KB_16384 157 bool "16384 KB (16 MB)" 158 help 159 Choose this option if you have a 16384 KB (16 MB) ROM chip. 160 161endchoice 162 163# Map the config names to an integer (KB). 164config UBOOT_ROMSIZE_KB 165 int 166 default 512 if UBOOT_ROMSIZE_KB_512 167 default 1024 if UBOOT_ROMSIZE_KB_1024 168 default 2048 if UBOOT_ROMSIZE_KB_2048 169 default 4096 if UBOOT_ROMSIZE_KB_4096 170 default 8192 if UBOOT_ROMSIZE_KB_8192 171 default 16384 if UBOOT_ROMSIZE_KB_16384 172 173# Map the config names to a hex value (bytes). 174config ROM_SIZE 175 hex 176 default 0x80000 if UBOOT_ROMSIZE_KB_512 177 default 0x100000 if UBOOT_ROMSIZE_KB_1024 178 default 0x200000 if UBOOT_ROMSIZE_KB_2048 179 default 0x400000 if UBOOT_ROMSIZE_KB_4096 180 default 0x800000 if UBOOT_ROMSIZE_KB_8192 181 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 182 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 183 184config HAVE_INTEL_ME 185 bool "Platform requires Intel Management Engine" 186 help 187 Newer higher-end devices have an Intel Management Engine (ME) 188 which is a very large binary blob (typically 1.5MB) which is 189 required for the platform to work. This enforces a particular 190 SPI flash format. You will need to supply the me.bin file in 191 your board directory. 192 193config X86_RAMTEST 194 bool "Perform a simple RAM test after SDRAM initialisation" 195 help 196 If there is something wrong with SDRAM then the platform will 197 often crash within U-Boot or the kernel. This option enables a 198 very simple RAM test that quickly checks whether the SDRAM seems 199 to work correctly. It is not exhaustive but can save time by 200 detecting obvious failures. 201 202config MARK_GRAPHICS_MEM_WRCOMB 203 bool "Mark graphics memory as write-combining." 204 default n 205 help 206 The graphics performance may increase if the graphics 207 memory is set as write-combining cache type. This option 208 enables marking the graphics memory as write-combining. 209 210menu "Display" 211 212config FRAMEBUFFER_SET_VESA_MODE 213 prompt "Set framebuffer graphics resolution" 214 bool 215 help 216 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) 217 218choice 219 prompt "framebuffer graphics resolution" 220 default FRAMEBUFFER_VESA_MODE_117 221 depends on FRAMEBUFFER_SET_VESA_MODE 222 help 223 This option sets the resolution used for the coreboot framebuffer (and 224 bootsplash screen). 225 226config FRAMEBUFFER_VESA_MODE_100 227 bool "640x400 256-color" 228 229config FRAMEBUFFER_VESA_MODE_101 230 bool "640x480 256-color" 231 232config FRAMEBUFFER_VESA_MODE_102 233 bool "800x600 16-color" 234 235config FRAMEBUFFER_VESA_MODE_103 236 bool "800x600 256-color" 237 238config FRAMEBUFFER_VESA_MODE_104 239 bool "1024x768 16-color" 240 241config FRAMEBUFFER_VESA_MODE_105 242 bool "1024x7686 256-color" 243 244config FRAMEBUFFER_VESA_MODE_106 245 bool "1280x1024 16-color" 246 247config FRAMEBUFFER_VESA_MODE_107 248 bool "1280x1024 256-color" 249 250config FRAMEBUFFER_VESA_MODE_108 251 bool "80x60 text" 252 253config FRAMEBUFFER_VESA_MODE_109 254 bool "132x25 text" 255 256config FRAMEBUFFER_VESA_MODE_10A 257 bool "132x43 text" 258 259config FRAMEBUFFER_VESA_MODE_10B 260 bool "132x50 text" 261 262config FRAMEBUFFER_VESA_MODE_10C 263 bool "132x60 text" 264 265config FRAMEBUFFER_VESA_MODE_10D 266 bool "320x200 32k-color (1:5:5:5)" 267 268config FRAMEBUFFER_VESA_MODE_10E 269 bool "320x200 64k-color (5:6:5)" 270 271config FRAMEBUFFER_VESA_MODE_10F 272 bool "320x200 16.8M-color (8:8:8)" 273 274config FRAMEBUFFER_VESA_MODE_110 275 bool "640x480 32k-color (1:5:5:5)" 276 277config FRAMEBUFFER_VESA_MODE_111 278 bool "640x480 64k-color (5:6:5)" 279 280config FRAMEBUFFER_VESA_MODE_112 281 bool "640x480 16.8M-color (8:8:8)" 282 283config FRAMEBUFFER_VESA_MODE_113 284 bool "800x600 32k-color (1:5:5:5)" 285 286config FRAMEBUFFER_VESA_MODE_114 287 bool "800x600 64k-color (5:6:5)" 288 289config FRAMEBUFFER_VESA_MODE_115 290 bool "800x600 16.8M-color (8:8:8)" 291 292config FRAMEBUFFER_VESA_MODE_116 293 bool "1024x768 32k-color (1:5:5:5)" 294 295config FRAMEBUFFER_VESA_MODE_117 296 bool "1024x768 64k-color (5:6:5)" 297 298config FRAMEBUFFER_VESA_MODE_118 299 bool "1024x768 16.8M-color (8:8:8)" 300 301config FRAMEBUFFER_VESA_MODE_119 302 bool "1280x1024 32k-color (1:5:5:5)" 303 304config FRAMEBUFFER_VESA_MODE_11A 305 bool "1280x1024 64k-color (5:6:5)" 306 307config FRAMEBUFFER_VESA_MODE_11B 308 bool "1280x1024 16.8M-color (8:8:8)" 309 310config FRAMEBUFFER_VESA_MODE_USER 311 bool "Manually select VESA mode" 312 313endchoice 314 315# Map the config names to an integer (KB). 316config FRAMEBUFFER_VESA_MODE 317 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER 318 hex 319 default 0x100 if FRAMEBUFFER_VESA_MODE_100 320 default 0x101 if FRAMEBUFFER_VESA_MODE_101 321 default 0x102 if FRAMEBUFFER_VESA_MODE_102 322 default 0x103 if FRAMEBUFFER_VESA_MODE_103 323 default 0x104 if FRAMEBUFFER_VESA_MODE_104 324 default 0x105 if FRAMEBUFFER_VESA_MODE_105 325 default 0x106 if FRAMEBUFFER_VESA_MODE_106 326 default 0x107 if FRAMEBUFFER_VESA_MODE_107 327 default 0x108 if FRAMEBUFFER_VESA_MODE_108 328 default 0x109 if FRAMEBUFFER_VESA_MODE_109 329 default 0x10A if FRAMEBUFFER_VESA_MODE_10A 330 default 0x10B if FRAMEBUFFER_VESA_MODE_10B 331 default 0x10C if FRAMEBUFFER_VESA_MODE_10C 332 default 0x10D if FRAMEBUFFER_VESA_MODE_10D 333 default 0x10E if FRAMEBUFFER_VESA_MODE_10E 334 default 0x10F if FRAMEBUFFER_VESA_MODE_10F 335 default 0x110 if FRAMEBUFFER_VESA_MODE_110 336 default 0x111 if FRAMEBUFFER_VESA_MODE_111 337 default 0x112 if FRAMEBUFFER_VESA_MODE_112 338 default 0x113 if FRAMEBUFFER_VESA_MODE_113 339 default 0x114 if FRAMEBUFFER_VESA_MODE_114 340 default 0x115 if FRAMEBUFFER_VESA_MODE_115 341 default 0x116 if FRAMEBUFFER_VESA_MODE_116 342 default 0x117 if FRAMEBUFFER_VESA_MODE_117 343 default 0x118 if FRAMEBUFFER_VESA_MODE_118 344 default 0x119 if FRAMEBUFFER_VESA_MODE_119 345 default 0x11A if FRAMEBUFFER_VESA_MODE_11A 346 default 0x11B if FRAMEBUFFER_VESA_MODE_11B 347 default 0x117 if FRAMEBUFFER_VESA_MODE_USER 348 349endmenu 350 351config HAVE_FSP 352 bool "Add an Firmware Support Package binary" 353 help 354 Select this option to add an Firmware Support Package binary to 355 the resulting U-Boot image. It is a binary blob which U-Boot uses 356 to set up SDRAM and other chipset specific initialization. 357 358 Note: Without this binary U-Boot will not be able to set up its 359 SDRAM so will not boot. 360 361config FSP_FILE 362 string "Firmware Support Package binary filename" 363 depends on HAVE_FSP 364 default "fsp.bin" 365 help 366 The filename of the file to use as Firmware Support Package binary 367 in the board directory. 368 369config FSP_ADDR 370 hex "Firmware Support Package binary location" 371 depends on HAVE_FSP 372 default 0xfffc0000 373 help 374 FSP is not Position Independent Code (PIC) and the whole FSP has to 375 be rebased if it is placed at a location which is different from the 376 perferred base address specified during the FSP build. Use Intel's 377 Binary Configuration Tool (BCT) to do the rebase. 378 379 The default base address of 0xfffc0000 indicates that the binary must 380 be located at offset 0xc0000 from the beginning of a 1MB flash device. 381 382config FSP_TEMP_RAM_ADDR 383 hex 384 default 0x2000000 385 help 386 Stack top address which is used in FspInit after DRAM is ready and 387 CAR is disabled. 388 389source "arch/x86/cpu/baytrail/Kconfig" 390 391source "arch/x86/cpu/coreboot/Kconfig" 392 393source "arch/x86/cpu/ivybridge/Kconfig" 394 395source "arch/x86/cpu/quark/Kconfig" 396 397source "arch/x86/cpu/queensbay/Kconfig" 398 399config TSC_CALIBRATION_BYPASS 400 bool "Bypass Time-Stamp Counter (TSC) calibration" 401 default n 402 help 403 By default U-Boot automatically calibrates Time-Stamp Counter (TSC) 404 running frequency via Model-Specific Register (MSR) and Programmable 405 Interval Timer (PIT). If the calibration does not work on your board, 406 select this option and provide a hardcoded TSC running frequency with 407 CONFIG_TSC_FREQ_IN_MHZ below. 408 409 Normally this option should be turned on in a simulation environment 410 like qemu. 411 412config TSC_FREQ_IN_MHZ 413 int "Time-Stamp Counter (TSC) running frequency in MHz" 414 depends on TSC_CALIBRATION_BYPASS 415 default 1000 416 help 417 The running frequency in MHz of Time-Stamp Counter (TSC). 418 419source "board/coreboot/coreboot/Kconfig" 420 421source "board/google/chromebook_link/Kconfig" 422 423source "board/intel/crownbay/Kconfig" 424 425source "board/intel/minnowmax/Kconfig" 426 427source "board/intel/galileo/Kconfig" 428 429config PCIE_ECAM_BASE 430 hex 431 default 0xe0000000 432 help 433 This is the memory-mapped address of PCI configuration space, which 434 is only available through the Enhanced Configuration Access 435 Mechanism (ECAM) with PCI Express. It can be set up almost 436 anywhere. Before it is set up, it is possible to access PCI 437 configuration space through I/O access, but memory access is more 438 convenient. Using this, PCI can be scanned and configured. This 439 should be set to a region that does not conflict with memory 440 assigned to PCI devices - i.e. the memory and prefetch regions, as 441 passed to pci_set_region(). 442 443endmenu 444