xref: /openbmc/u-boot/arch/x86/Kconfig (revision ee86e0d2)
1menu "x86 architecture"
2	depends on X86
3
4config SYS_ARCH
5	default "x86"
6
7choice
8	prompt "Mainboard vendor"
9	default VENDOR_EMULATION
10
11config VENDOR_ADVANTECH
12	bool "advantech"
13
14config VENDOR_CONGATEC
15	bool "congatec"
16
17config VENDOR_COREBOOT
18	bool "coreboot"
19
20config VENDOR_DFI
21	bool "dfi"
22
23config VENDOR_EFI
24	bool "efi"
25
26config VENDOR_EMULATION
27	bool "emulation"
28
29config VENDOR_GOOGLE
30	bool "Google"
31
32config VENDOR_INTEL
33	bool "Intel"
34
35endchoice
36
37# board-specific options below
38source "board/advantech/Kconfig"
39source "board/congatec/Kconfig"
40source "board/coreboot/Kconfig"
41source "board/dfi/Kconfig"
42source "board/efi/Kconfig"
43source "board/emulation/Kconfig"
44source "board/google/Kconfig"
45source "board/intel/Kconfig"
46
47# platform-specific options below
48source "arch/x86/cpu/baytrail/Kconfig"
49source "arch/x86/cpu/broadwell/Kconfig"
50source "arch/x86/cpu/coreboot/Kconfig"
51source "arch/x86/cpu/ivybridge/Kconfig"
52source "arch/x86/cpu/qemu/Kconfig"
53source "arch/x86/cpu/quark/Kconfig"
54source "arch/x86/cpu/queensbay/Kconfig"
55
56# architecture-specific options below
57
58config AHCI
59	default y
60
61config SYS_MALLOC_F_LEN
62	default 0x800
63
64config RAMBASE
65	hex
66	default 0x100000
67
68config XIP_ROM_SIZE
69	hex
70	depends on X86_RESET_VECTOR
71	default ROM_SIZE
72
73config CPU_ADDR_BITS
74	int
75	default 36
76
77config HPET_ADDRESS
78	hex
79	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
80
81config SMM_TSEG
82	bool
83	default n
84
85config SMM_TSEG_SIZE
86	hex
87
88config X86_RESET_VECTOR
89	bool
90	default n
91
92config RESET_SEG_START
93	hex
94	depends on X86_RESET_VECTOR
95	default 0xffff0000
96
97config RESET_SEG_SIZE
98	hex
99	depends on X86_RESET_VECTOR
100	default 0x10000
101
102config RESET_VEC_LOC
103	hex
104	depends on X86_RESET_VECTOR
105	default 0xfffffff0
106
107config SYS_X86_START16
108	hex
109	depends on X86_RESET_VECTOR
110	default 0xfffff800
111
112config BOARD_ROMSIZE_KB_512
113	bool
114config BOARD_ROMSIZE_KB_1024
115	bool
116config BOARD_ROMSIZE_KB_2048
117	bool
118config BOARD_ROMSIZE_KB_4096
119	bool
120config BOARD_ROMSIZE_KB_8192
121	bool
122config BOARD_ROMSIZE_KB_16384
123	bool
124
125choice
126	prompt "ROM chip size"
127	depends on X86_RESET_VECTOR
128	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
129	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
130	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
131	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
132	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
133	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
134	help
135	  Select the size of the ROM chip you intend to flash U-Boot on.
136
137	  The build system will take care of creating a u-boot.rom file
138	  of the matching size.
139
140config UBOOT_ROMSIZE_KB_512
141	bool "512 KB"
142	help
143	  Choose this option if you have a 512 KB ROM chip.
144
145config UBOOT_ROMSIZE_KB_1024
146	bool "1024 KB (1 MB)"
147	help
148	  Choose this option if you have a 1024 KB (1 MB) ROM chip.
149
150config UBOOT_ROMSIZE_KB_2048
151	bool "2048 KB (2 MB)"
152	help
153	  Choose this option if you have a 2048 KB (2 MB) ROM chip.
154
155config UBOOT_ROMSIZE_KB_4096
156	bool "4096 KB (4 MB)"
157	help
158	  Choose this option if you have a 4096 KB (4 MB) ROM chip.
159
160config UBOOT_ROMSIZE_KB_8192
161	bool "8192 KB (8 MB)"
162	help
163	  Choose this option if you have a 8192 KB (8 MB) ROM chip.
164
165config UBOOT_ROMSIZE_KB_16384
166	bool "16384 KB (16 MB)"
167	help
168	  Choose this option if you have a 16384 KB (16 MB) ROM chip.
169
170endchoice
171
172# Map the config names to an integer (KB).
173config UBOOT_ROMSIZE_KB
174	int
175	default 512 if UBOOT_ROMSIZE_KB_512
176	default 1024 if UBOOT_ROMSIZE_KB_1024
177	default 2048 if UBOOT_ROMSIZE_KB_2048
178	default 4096 if UBOOT_ROMSIZE_KB_4096
179	default 8192 if UBOOT_ROMSIZE_KB_8192
180	default 16384 if UBOOT_ROMSIZE_KB_16384
181
182# Map the config names to a hex value (bytes).
183config ROM_SIZE
184	hex
185	default 0x80000 if UBOOT_ROMSIZE_KB_512
186	default 0x100000 if UBOOT_ROMSIZE_KB_1024
187	default 0x200000 if UBOOT_ROMSIZE_KB_2048
188	default 0x400000 if UBOOT_ROMSIZE_KB_4096
189	default 0x800000 if UBOOT_ROMSIZE_KB_8192
190	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
191	default 0x1000000 if UBOOT_ROMSIZE_KB_16384
192
193config HAVE_INTEL_ME
194	bool "Platform requires Intel Management Engine"
195	help
196	  Newer higher-end devices have an Intel Management Engine (ME)
197	  which is a very large binary blob (typically 1.5MB) which is
198	  required for the platform to work. This enforces a particular
199	  SPI flash format. You will need to supply the me.bin file in
200	  your board directory.
201
202config X86_RAMTEST
203	bool "Perform a simple RAM test after SDRAM initialisation"
204	help
205	  If there is something wrong with SDRAM then the platform will
206	  often crash within U-Boot or the kernel. This option enables a
207	  very simple RAM test that quickly checks whether the SDRAM seems
208	  to work correctly. It is not exhaustive but can save time by
209	  detecting obvious failures.
210
211config HAVE_FSP
212	bool "Add an Firmware Support Package binary"
213	depends on !EFI
214	help
215	  Select this option to add an Firmware Support Package binary to
216	  the resulting U-Boot image. It is a binary blob which U-Boot uses
217	  to set up SDRAM and other chipset specific initialization.
218
219	  Note: Without this binary U-Boot will not be able to set up its
220	  SDRAM so will not boot.
221
222config FSP_FILE
223	string "Firmware Support Package binary filename"
224	depends on HAVE_FSP
225	default "fsp.bin"
226	help
227	  The filename of the file to use as Firmware Support Package binary
228	  in the board directory.
229
230config FSP_ADDR
231	hex "Firmware Support Package binary location"
232	depends on HAVE_FSP
233	default 0xfffc0000
234	help
235	  FSP is not Position Independent Code (PIC) and the whole FSP has to
236	  be rebased if it is placed at a location which is different from the
237	  perferred base address specified during the FSP build. Use Intel's
238	  Binary Configuration Tool (BCT) to do the rebase.
239
240	  The default base address of 0xfffc0000 indicates that the binary must
241	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
242
243config FSP_TEMP_RAM_ADDR
244	hex
245	depends on HAVE_FSP
246	default 0x2000000
247	help
248	  Stack top address which is used in fsp_init() after DRAM is ready and
249	  CAR is disabled.
250
251config FSP_SYS_MALLOC_F_LEN
252	hex
253	depends on HAVE_FSP
254	default 0x100000
255	help
256	  Additional size of malloc() pool before relocation.
257
258config FSP_USE_UPD
259	bool
260	depends on HAVE_FSP
261	default y
262	help
263	  Most FSPs use UPD data region for some FSP customization. But there
264	  are still some FSPs that might not even have UPD. For such FSPs,
265	  override this to n in their platform Kconfig files.
266
267config FSP_BROKEN_HOB
268	bool
269	depends on HAVE_FSP
270	help
271	  Indicate some buggy FSPs that does not report memory used by FSP
272	  itself as reserved in the resource descriptor HOB. Select this to
273	  tell U-Boot to do some additional work to ensure U-Boot relocation
274	  do not overwrite the important boot service data which is used by
275	  FSP, otherwise the subsequent call to fsp_notify() will fail.
276
277config ENABLE_MRC_CACHE
278	bool "Enable MRC cache"
279	depends on !EFI && !SYS_COREBOOT
280	help
281	  Enable this feature to cause MRC data to be cached in NV storage
282	  to be used for speeding up boot time on future reboots and/or
283	  power cycles.
284
285	  For platforms that use Intel FSP for the memory initialization,
286	  please check FSP output HOB via U-Boot command 'fsp hob' to see
287	  if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
288	  If such GUID does not exist, MRC cache is not avaiable on such
289	  platform (eg: Intel Queensbay), which means selecting this option
290	  here does not make any difference.
291
292config HAVE_MRC
293	bool "Add a System Agent binary"
294	depends on !HAVE_FSP
295	help
296	  Select this option to add a System Agent binary to
297	  the resulting U-Boot image. MRC stands for Memory Reference Code.
298	  It is a binary blob which U-Boot uses to set up SDRAM.
299
300	  Note: Without this binary U-Boot will not be able to set up its
301	  SDRAM so will not boot.
302
303config CACHE_MRC_BIN
304	bool
305	depends on HAVE_MRC
306	default n
307	help
308	  Enable caching for the memory reference code binary. This uses an
309	  MTRR (memory type range register) to turn on caching for the section
310	  of SPI flash that contains the memory reference code. This makes
311	  SDRAM init run faster.
312
313config CACHE_MRC_SIZE_KB
314	int
315	depends on HAVE_MRC
316	default 512
317	help
318	  Sets the size of the cached area for the memory reference code.
319	  This ends at the end of SPI flash (address 0xffffffff) and is
320	  measured in KB. Typically this is set to 512, providing for 0.5MB
321	  of cached space.
322
323config DCACHE_RAM_BASE
324	hex
325	depends on HAVE_MRC
326	help
327	  Sets the base of the data cache area in memory space. This is the
328	  start address of the cache-as-RAM (CAR) area and the address varies
329	  depending on the CPU. Once CAR is set up, read/write memory becomes
330	  available at this address and can be used temporarily until SDRAM
331	  is working.
332
333config DCACHE_RAM_SIZE
334	hex
335	depends on HAVE_MRC
336	default 0x40000
337	help
338	  Sets the total size of the data cache area in memory space. This
339	  sets the size of the cache-as-RAM (CAR) area. Note that much of the
340	  CAR space is required by the MRC. The CAR space available to U-Boot
341	  is normally at the start and typically extends to 1/4 or 1/2 of the
342	  available size.
343
344config DCACHE_RAM_MRC_VAR_SIZE
345	hex
346	depends on HAVE_MRC
347	help
348	  This is the amount of CAR (Cache as RAM) reserved for use by the
349	  memory reference code. This depends on the implementation of the
350	  memory reference code and must be set correctly or the board will
351	  not boot.
352
353config HAVE_REFCODE
354        bool "Add a Reference Code binary"
355        help
356          Select this option to add a Reference Code binary to the resulting
357          U-Boot image. This is an Intel binary blob that handles system
358          initialisation, in this case the PCH and System Agent.
359
360          Note: Without this binary (on platforms that need it such as
361          broadwell) U-Boot will be missing some critical setup steps.
362          Various peripherals may fail to work.
363
364config SMP
365	bool "Enable Symmetric Multiprocessing"
366	default n
367	help
368	  Enable use of more than one CPU in U-Boot and the Operating System
369	  when loaded. Each CPU will be started up and information can be
370	  obtained using the 'cpu' command. If this option is disabled, then
371	  only one CPU will be enabled regardless of the number of CPUs
372	  available.
373
374config MAX_CPUS
375	int "Maximum number of CPUs permitted"
376	depends on SMP
377	default 4
378	help
379	  When using multi-CPU chips it is possible for U-Boot to start up
380	  more than one CPU. The stack memory used by all of these CPUs is
381	  pre-allocated so at present U-Boot wants to know the maximum
382	  number of CPUs that may be present. Set this to at least as high
383	  as the number of CPUs in your system (it uses about 4KB of RAM for
384	  each CPU).
385
386config AP_STACK_SIZE
387	hex
388	depends on SMP
389	default 0x1000
390	help
391	  Each additional CPU started by U-Boot requires its own stack. This
392	  option sets the stack size used by each CPU and directly affects
393	  the memory used by this initialisation process. Typically 4KB is
394	  enough space.
395
396config HAVE_VGA_BIOS
397	bool "Add a VGA BIOS image"
398	help
399	  Select this option if you have a VGA BIOS image that you would
400	  like to add to your ROM.
401
402config VGA_BIOS_FILE
403	string "VGA BIOS image filename"
404	depends on HAVE_VGA_BIOS
405	default "vga.bin"
406	help
407	  The filename of the VGA BIOS image in the board directory.
408
409config VGA_BIOS_ADDR
410	hex "VGA BIOS image location"
411	depends on HAVE_VGA_BIOS
412	default 0xfff90000
413	help
414	  The location of VGA BIOS image in the SPI flash. For example, base
415	  address of 0xfff90000 indicates that the image will be put at offset
416	  0x90000 from the beginning of a 1MB flash device.
417
418menu "System tables"
419	depends on !EFI && !SYS_COREBOOT
420
421config GENERATE_PIRQ_TABLE
422	bool "Generate a PIRQ table"
423	default n
424	help
425	  Generate a PIRQ routing table for this board. The PIRQ routing table
426	  is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
427	  at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
428	  It specifies the interrupt router information as well how all the PCI
429	  devices' interrupt pins are wired to PIRQs.
430
431config GENERATE_SFI_TABLE
432	bool "Generate a SFI (Simple Firmware Interface) table"
433	help
434	  The Simple Firmware Interface (SFI) provides a lightweight method
435	  for platform firmware to pass information to the operating system
436	  via static tables in memory.  Kernel SFI support is required to
437	  boot on SFI-only platforms.  If you have ACPI tables then these are
438	  used instead.
439
440	  U-Boot writes this table in write_sfi_table() just before booting
441	  the OS.
442
443	  For more information, see http://simplefirmware.org
444
445config GENERATE_MP_TABLE
446	bool "Generate an MP (Multi-Processor) table"
447	default n
448	help
449	  Generate an MP (Multi-Processor) table for this board. The MP table
450	  provides a way for the operating system to support for symmetric
451	  multiprocessing as well as symmetric I/O interrupt handling with
452	  the local APIC and I/O APIC.
453
454config GENERATE_ACPI_TABLE
455	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
456	default n
457	select QFW if QEMU
458	help
459	  The Advanced Configuration and Power Interface (ACPI) specification
460	  provides an open standard for device configuration and management
461	  by the operating system. It defines platform-independent interfaces
462	  for configuration and power management monitoring.
463
464endmenu
465
466config MAX_PIRQ_LINKS
467	int
468	default 8
469	help
470	  This variable specifies the number of PIRQ interrupt links which are
471	  routable. On most older chipsets, this is 4, PIRQA through PIRQD.
472	  Some newer chipsets offer more than four links, commonly up to PIRQH.
473
474config IRQ_SLOT_COUNT
475	int
476	default 128
477	help
478	  U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
479	  which in turns forms a table of exact 4KiB. The default value 128
480	  should be enough for most boards. If this does not fit your board,
481	  change it according to your needs.
482
483config PCIE_ECAM_BASE
484	hex
485	default 0xe0000000
486	help
487	  This is the memory-mapped address of PCI configuration space, which
488	  is only available through the Enhanced Configuration Access
489	  Mechanism (ECAM) with PCI Express. It can be set up almost
490	  anywhere. Before it is set up, it is possible to access PCI
491	  configuration space through I/O access, but memory access is more
492	  convenient. Using this, PCI can be scanned and configured. This
493	  should be set to a region that does not conflict with memory
494	  assigned to PCI devices - i.e. the memory and prefetch regions, as
495	  passed to pci_set_region().
496
497config PCIE_ECAM_SIZE
498	hex
499	default 0x10000000
500	help
501	  This is the size of memory-mapped address of PCI configuration space,
502	  which is only available through the Enhanced Configuration Access
503	  Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
504	  so a default 0x10000000 size covers all of the 256 buses which is the
505	  maximum number of PCI buses as defined by the PCI specification.
506
507config I8259_PIC
508	bool
509	default y
510	help
511	  Intel 8259 ISA compatible chipset incorporates two 8259 (master and
512	  slave) interrupt controllers. Include this to have U-Boot set up
513	  the interrupt correctly.
514
515config I8254_TIMER
516	bool
517	default y
518	help
519	  Intel 8254 timer contains three counters which have fixed uses.
520	  Include this to have U-Boot set up the timer correctly.
521
522config SEABIOS
523	bool "Support booting SeaBIOS"
524	help
525	  SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
526	  It can run in an emulator or natively on X86 hardware with the use
527	  of coreboot/U-Boot. By turning on this option, U-Boot prepares
528	  all the configuration tables that are necessary to boot SeaBIOS.
529
530	  Check http://www.seabios.org/SeaBIOS for details.
531
532config HIGH_TABLE_SIZE
533	hex "Size of configuration tables which reside in high memory"
534	default 0x10000
535	depends on SEABIOS
536	help
537	  SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
538	  configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
539	  puts a copy of configuration tables in high memory region which
540	  is reserved on the stack before relocation. The region size is
541	  determined by this option.
542
543	  Increse it if the default size does not fit the board's needs.
544	  This is most likely due to a large ACPI DSDT table is used.
545
546source "arch/x86/lib/efi/Kconfig"
547
548endmenu
549