1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Run U-Boot in 32/64-bit mode" 9 default X86_RUN_32BIT 10 help 11 U-Boot can be built as a 32-bit binary which runs in 32-bit mode 12 even on 64-bit machines. In this case SPL is not used, and U-Boot 13 runs directly from the reset vector (via 16-bit start-up). 14 15 Alternatively it can be run as a 64-bit binary, thus requiring a 16 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit 17 start-up) then jumps to U-Boot in 64-bit mode. 18 19 For now, 32-bit mode is recommended, as 64-bit is still 20 experimental and is missing a lot of features. 21 22config X86_RUN_32BIT 23 bool "32-bit" 24 help 25 Build U-Boot as a 32-bit binary with no SPL. This is the currently 26 supported normal setup. U-Boot will stay in 32-bit mode even on 27 64-bit machines. When booting a 64-bit kernel, U-Boot will switch 28 to 64-bit just before starting the kernel. Only the bottom 4GB of 29 memory can be accessed through normal means, although 30 arch_phys_memset() can be used for basic access to other memory. 31 32config X86_RUN_64BIT 33 bool "64-bit" 34 select X86_64 35 select SUPPORT_SPL 36 select SPL 37 select SPL_SEPARATE_BSS 38 help 39 Build U-Boot as a 64-bit binary with a 32-bit SPL. This is 40 experimental and many features are missing. U-Boot SPL starts up, 41 runs through the 16-bit and 32-bit init, then switches to 64-bit 42 mode and jumps to U-Boot proper. 43 44endchoice 45 46config X86_64 47 bool 48 49config SPL_X86_64 50 bool 51 depends on SPL 52 53choice 54 prompt "Mainboard vendor" 55 default VENDOR_EMULATION 56 57config VENDOR_ADVANTECH 58 bool "advantech" 59 60config VENDOR_CONGATEC 61 bool "congatec" 62 63config VENDOR_COREBOOT 64 bool "coreboot" 65 66config VENDOR_DFI 67 bool "dfi" 68 69config VENDOR_EFI 70 bool "efi" 71 72config VENDOR_EMULATION 73 bool "emulation" 74 75config VENDOR_GOOGLE 76 bool "Google" 77 78config VENDOR_INTEL 79 bool "Intel" 80 81endchoice 82 83# subarchitectures-specific options below 84config INTEL_MID 85 bool "Intel MID platform support" 86 select REGMAP 87 select SYSCON 88 help 89 Select to build a U-Boot capable of supporting Intel MID 90 (Mobile Internet Device) platform systems which do not have 91 the PCI legacy interfaces. 92 93 If you are building for a PC class system say N here. 94 95 Intel MID platforms are based on an Intel processor and 96 chipset which consume less power than most of the x86 97 derivatives. 98 99# board-specific options below 100source "board/advantech/Kconfig" 101source "board/congatec/Kconfig" 102source "board/coreboot/Kconfig" 103source "board/dfi/Kconfig" 104source "board/efi/Kconfig" 105source "board/emulation/Kconfig" 106source "board/google/Kconfig" 107source "board/intel/Kconfig" 108 109# platform-specific options below 110source "arch/x86/cpu/baytrail/Kconfig" 111source "arch/x86/cpu/braswell/Kconfig" 112source "arch/x86/cpu/broadwell/Kconfig" 113source "arch/x86/cpu/coreboot/Kconfig" 114source "arch/x86/cpu/ivybridge/Kconfig" 115source "arch/x86/cpu/qemu/Kconfig" 116source "arch/x86/cpu/quark/Kconfig" 117source "arch/x86/cpu/queensbay/Kconfig" 118source "arch/x86/cpu/tangier/Kconfig" 119 120# architecture-specific options below 121 122config AHCI 123 default y 124 125config SYS_MALLOC_F_LEN 126 default 0x800 127 128config RAMBASE 129 hex 130 default 0x100000 131 132config XIP_ROM_SIZE 133 hex 134 depends on X86_RESET_VECTOR 135 default ROM_SIZE 136 137config CPU_ADDR_BITS 138 int 139 default 36 140 141config HPET_ADDRESS 142 hex 143 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 144 145config SMM_TSEG 146 bool 147 default n 148 149config SMM_TSEG_SIZE 150 hex 151 152config X86_RESET_VECTOR 153 bool 154 default n 155 156# The following options control where the 16-bit and 32-bit init lies 157# If SPL is enabled then it normally holds this init code, and U-Boot proper 158# is normally a 64-bit build. 159# 160# The 16-bit init refers to the reset vector and the small amount of code to 161# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper, 162# or missing altogether if U-Boot is started from EFI or coreboot. 163# 164# The 32-bit init refers to processor init, running binary blobs including 165# FSP, setting up interrupts and anything else that needs to be done in 166# 32-bit code. It is normally in the same place as 16-bit init if that is 167# enabled (i.e. they are both in SPL, or both in U-Boot proper). 168config X86_16BIT_INIT 169 bool 170 depends on X86_RESET_VECTOR 171 default y if X86_RESET_VECTOR && !SPL 172 help 173 This is enabled when 16-bit init is in U-Boot proper 174 175config SPL_X86_16BIT_INIT 176 bool 177 depends on X86_RESET_VECTOR 178 default y if X86_RESET_VECTOR && SPL 179 help 180 This is enabled when 16-bit init is in SPL 181 182config X86_32BIT_INIT 183 bool 184 depends on X86_RESET_VECTOR 185 default y if X86_RESET_VECTOR && !SPL 186 help 187 This is enabled when 32-bit init is in U-Boot proper 188 189config SPL_X86_32BIT_INIT 190 bool 191 depends on X86_RESET_VECTOR 192 default y if X86_RESET_VECTOR && SPL 193 help 194 This is enabled when 32-bit init is in SPL 195 196config RESET_SEG_START 197 hex 198 depends on X86_RESET_VECTOR 199 default 0xffff0000 200 201config RESET_SEG_SIZE 202 hex 203 depends on X86_RESET_VECTOR 204 default 0x10000 205 206config RESET_VEC_LOC 207 hex 208 depends on X86_RESET_VECTOR 209 default 0xfffffff0 210 211config SYS_X86_START16 212 hex 213 depends on X86_RESET_VECTOR 214 default 0xfffff800 215 216config X86_LOAD_FROM_32_BIT 217 bool "Boot from a 32-bit program" 218 help 219 Define this to boot U-Boot from a 32-bit program which sets 220 the GDT differently. This can be used to boot directly from 221 any stage of coreboot, for example, bypassing the normal 222 payload-loading feature. 223 224config BOARD_ROMSIZE_KB_512 225 bool 226config BOARD_ROMSIZE_KB_1024 227 bool 228config BOARD_ROMSIZE_KB_2048 229 bool 230config BOARD_ROMSIZE_KB_4096 231 bool 232config BOARD_ROMSIZE_KB_8192 233 bool 234config BOARD_ROMSIZE_KB_16384 235 bool 236 237choice 238 prompt "ROM chip size" 239 depends on X86_RESET_VECTOR 240 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 241 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 242 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 243 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 244 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 245 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 246 help 247 Select the size of the ROM chip you intend to flash U-Boot on. 248 249 The build system will take care of creating a u-boot.rom file 250 of the matching size. 251 252config UBOOT_ROMSIZE_KB_512 253 bool "512 KB" 254 help 255 Choose this option if you have a 512 KB ROM chip. 256 257config UBOOT_ROMSIZE_KB_1024 258 bool "1024 KB (1 MB)" 259 help 260 Choose this option if you have a 1024 KB (1 MB) ROM chip. 261 262config UBOOT_ROMSIZE_KB_2048 263 bool "2048 KB (2 MB)" 264 help 265 Choose this option if you have a 2048 KB (2 MB) ROM chip. 266 267config UBOOT_ROMSIZE_KB_4096 268 bool "4096 KB (4 MB)" 269 help 270 Choose this option if you have a 4096 KB (4 MB) ROM chip. 271 272config UBOOT_ROMSIZE_KB_8192 273 bool "8192 KB (8 MB)" 274 help 275 Choose this option if you have a 8192 KB (8 MB) ROM chip. 276 277config UBOOT_ROMSIZE_KB_16384 278 bool "16384 KB (16 MB)" 279 help 280 Choose this option if you have a 16384 KB (16 MB) ROM chip. 281 282endchoice 283 284# Map the config names to an integer (KB). 285config UBOOT_ROMSIZE_KB 286 int 287 default 512 if UBOOT_ROMSIZE_KB_512 288 default 1024 if UBOOT_ROMSIZE_KB_1024 289 default 2048 if UBOOT_ROMSIZE_KB_2048 290 default 4096 if UBOOT_ROMSIZE_KB_4096 291 default 8192 if UBOOT_ROMSIZE_KB_8192 292 default 16384 if UBOOT_ROMSIZE_KB_16384 293 294# Map the config names to a hex value (bytes). 295config ROM_SIZE 296 hex 297 default 0x80000 if UBOOT_ROMSIZE_KB_512 298 default 0x100000 if UBOOT_ROMSIZE_KB_1024 299 default 0x200000 if UBOOT_ROMSIZE_KB_2048 300 default 0x400000 if UBOOT_ROMSIZE_KB_4096 301 default 0x800000 if UBOOT_ROMSIZE_KB_8192 302 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 303 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 304 305config HAVE_INTEL_ME 306 bool "Platform requires Intel Management Engine" 307 help 308 Newer higher-end devices have an Intel Management Engine (ME) 309 which is a very large binary blob (typically 1.5MB) which is 310 required for the platform to work. This enforces a particular 311 SPI flash format. You will need to supply the me.bin file in 312 your board directory. 313 314config X86_RAMTEST 315 bool "Perform a simple RAM test after SDRAM initialisation" 316 help 317 If there is something wrong with SDRAM then the platform will 318 often crash within U-Boot or the kernel. This option enables a 319 very simple RAM test that quickly checks whether the SDRAM seems 320 to work correctly. It is not exhaustive but can save time by 321 detecting obvious failures. 322 323config FLASH_DESCRIPTOR_FILE 324 string "Flash descriptor binary filename" 325 depends on HAVE_INTEL_ME 326 default "descriptor.bin" 327 help 328 The filename of the file to use as flash descriptor in the 329 board directory. 330 331config INTEL_ME_FILE 332 string "Intel Management Engine binary filename" 333 depends on HAVE_INTEL_ME 334 default "me.bin" 335 help 336 The filename of the file to use as Intel Management Engine in the 337 board directory. 338 339config HAVE_FSP 340 bool "Add an Firmware Support Package binary" 341 depends on !EFI 342 help 343 Select this option to add an Firmware Support Package binary to 344 the resulting U-Boot image. It is a binary blob which U-Boot uses 345 to set up SDRAM and other chipset specific initialization. 346 347 Note: Without this binary U-Boot will not be able to set up its 348 SDRAM so will not boot. 349 350config FSP_FILE 351 string "Firmware Support Package binary filename" 352 depends on HAVE_FSP 353 default "fsp.bin" 354 help 355 The filename of the file to use as Firmware Support Package binary 356 in the board directory. 357 358config FSP_ADDR 359 hex "Firmware Support Package binary location" 360 depends on HAVE_FSP 361 default 0xfffc0000 362 help 363 FSP is not Position Independent Code (PIC) and the whole FSP has to 364 be rebased if it is placed at a location which is different from the 365 perferred base address specified during the FSP build. Use Intel's 366 Binary Configuration Tool (BCT) to do the rebase. 367 368 The default base address of 0xfffc0000 indicates that the binary must 369 be located at offset 0xc0000 from the beginning of a 1MB flash device. 370 371config FSP_TEMP_RAM_ADDR 372 hex 373 depends on HAVE_FSP 374 default 0x2000000 375 help 376 Stack top address which is used in fsp_init() after DRAM is ready and 377 CAR is disabled. 378 379config FSP_SYS_MALLOC_F_LEN 380 hex 381 depends on HAVE_FSP 382 default 0x100000 383 help 384 Additional size of malloc() pool before relocation. 385 386config FSP_USE_UPD 387 bool 388 depends on HAVE_FSP 389 default y 390 help 391 Most FSPs use UPD data region for some FSP customization. But there 392 are still some FSPs that might not even have UPD. For such FSPs, 393 override this to n in their platform Kconfig files. 394 395config FSP_BROKEN_HOB 396 bool 397 depends on HAVE_FSP 398 help 399 Indicate some buggy FSPs that does not report memory used by FSP 400 itself as reserved in the resource descriptor HOB. Select this to 401 tell U-Boot to do some additional work to ensure U-Boot relocation 402 do not overwrite the important boot service data which is used by 403 FSP, otherwise the subsequent call to fsp_notify() will fail. 404 405config ENABLE_MRC_CACHE 406 bool "Enable MRC cache" 407 depends on !EFI && !SYS_COREBOOT 408 help 409 Enable this feature to cause MRC data to be cached in NV storage 410 to be used for speeding up boot time on future reboots and/or 411 power cycles. 412 413 For platforms that use Intel FSP for the memory initialization, 414 please check FSP output HOB via U-Boot command 'fsp hob' to see 415 if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h). 416 If such GUID does not exist, MRC cache is not avaiable on such 417 platform (eg: Intel Queensbay), which means selecting this option 418 here does not make any difference. 419 420config HAVE_MRC 421 bool "Add a System Agent binary" 422 depends on !HAVE_FSP 423 help 424 Select this option to add a System Agent binary to 425 the resulting U-Boot image. MRC stands for Memory Reference Code. 426 It is a binary blob which U-Boot uses to set up SDRAM. 427 428 Note: Without this binary U-Boot will not be able to set up its 429 SDRAM so will not boot. 430 431config CACHE_MRC_BIN 432 bool 433 depends on HAVE_MRC 434 default n 435 help 436 Enable caching for the memory reference code binary. This uses an 437 MTRR (memory type range register) to turn on caching for the section 438 of SPI flash that contains the memory reference code. This makes 439 SDRAM init run faster. 440 441config CACHE_MRC_SIZE_KB 442 int 443 depends on HAVE_MRC 444 default 512 445 help 446 Sets the size of the cached area for the memory reference code. 447 This ends at the end of SPI flash (address 0xffffffff) and is 448 measured in KB. Typically this is set to 512, providing for 0.5MB 449 of cached space. 450 451config DCACHE_RAM_BASE 452 hex 453 depends on HAVE_MRC 454 help 455 Sets the base of the data cache area in memory space. This is the 456 start address of the cache-as-RAM (CAR) area and the address varies 457 depending on the CPU. Once CAR is set up, read/write memory becomes 458 available at this address and can be used temporarily until SDRAM 459 is working. 460 461config DCACHE_RAM_SIZE 462 hex 463 depends on HAVE_MRC 464 default 0x40000 465 help 466 Sets the total size of the data cache area in memory space. This 467 sets the size of the cache-as-RAM (CAR) area. Note that much of the 468 CAR space is required by the MRC. The CAR space available to U-Boot 469 is normally at the start and typically extends to 1/4 or 1/2 of the 470 available size. 471 472config DCACHE_RAM_MRC_VAR_SIZE 473 hex 474 depends on HAVE_MRC 475 help 476 This is the amount of CAR (Cache as RAM) reserved for use by the 477 memory reference code. This depends on the implementation of the 478 memory reference code and must be set correctly or the board will 479 not boot. 480 481config HAVE_REFCODE 482 bool "Add a Reference Code binary" 483 help 484 Select this option to add a Reference Code binary to the resulting 485 U-Boot image. This is an Intel binary blob that handles system 486 initialisation, in this case the PCH and System Agent. 487 488 Note: Without this binary (on platforms that need it such as 489 broadwell) U-Boot will be missing some critical setup steps. 490 Various peripherals may fail to work. 491 492config SMP 493 bool "Enable Symmetric Multiprocessing" 494 default n 495 help 496 Enable use of more than one CPU in U-Boot and the Operating System 497 when loaded. Each CPU will be started up and information can be 498 obtained using the 'cpu' command. If this option is disabled, then 499 only one CPU will be enabled regardless of the number of CPUs 500 available. 501 502config MAX_CPUS 503 int "Maximum number of CPUs permitted" 504 depends on SMP 505 default 4 506 help 507 When using multi-CPU chips it is possible for U-Boot to start up 508 more than one CPU. The stack memory used by all of these CPUs is 509 pre-allocated so at present U-Boot wants to know the maximum 510 number of CPUs that may be present. Set this to at least as high 511 as the number of CPUs in your system (it uses about 4KB of RAM for 512 each CPU). 513 514config AP_STACK_SIZE 515 hex 516 depends on SMP 517 default 0x1000 518 help 519 Each additional CPU started by U-Boot requires its own stack. This 520 option sets the stack size used by each CPU and directly affects 521 the memory used by this initialisation process. Typically 4KB is 522 enough space. 523 524config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED 525 bool 526 help 527 This option indicates that the turbo mode setting is not package 528 scoped. i.e. turbo_enable() needs to be called on not just the 529 bootstrap processor (BSP). 530 531config HAVE_VGA_BIOS 532 bool "Add a VGA BIOS image" 533 help 534 Select this option if you have a VGA BIOS image that you would 535 like to add to your ROM. 536 537config VGA_BIOS_FILE 538 string "VGA BIOS image filename" 539 depends on HAVE_VGA_BIOS 540 default "vga.bin" 541 help 542 The filename of the VGA BIOS image in the board directory. 543 544config VGA_BIOS_ADDR 545 hex "VGA BIOS image location" 546 depends on HAVE_VGA_BIOS 547 default 0xfff90000 548 help 549 The location of VGA BIOS image in the SPI flash. For example, base 550 address of 0xfff90000 indicates that the image will be put at offset 551 0x90000 from the beginning of a 1MB flash device. 552 553config HAVE_VBT 554 bool "Add a Video BIOS Table (VBT) image" 555 depends on HAVE_FSP 556 help 557 Select this option if you have a Video BIOS Table (VBT) image that 558 you would like to add to your ROM. This is normally required if you 559 are using an Intel FSP firmware that is complaint with spec 1.1 or 560 later to initialize the integrated graphics device (IGD). 561 562 Video BIOS Table, or VBT, provides platform and board specific 563 configuration information to the driver that is not discoverable 564 or available through other means. By other means the most used 565 method here is to read EDID table from the attached monitor, over 566 Display Data Channel (DDC) using two pin I2C serial interface. VBT 567 configuration is related to display hardware and is available via 568 the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM). 569 570config VBT_FILE 571 string "Video BIOS Table (VBT) image filename" 572 depends on HAVE_VBT 573 default "vbt.bin" 574 help 575 The filename of the file to use as Video BIOS Table (VBT) image 576 in the board directory. 577 578config VBT_ADDR 579 hex "Video BIOS Table (VBT) image location" 580 depends on HAVE_VBT 581 default 0xfff90000 582 help 583 The location of Video BIOS Table (VBT) image in the SPI flash. For 584 example, base address of 0xfff90000 indicates that the image will 585 be put at offset 0x90000 from the beginning of a 1MB flash device. 586 587config VIDEO_FSP 588 bool "Enable FSP framebuffer driver support" 589 depends on HAVE_VBT && DM_VIDEO 590 help 591 Turn on this option to enable a framebuffer driver when U-Boot is 592 using Video BIOS Table (VBT) image for FSP firmware to initialize 593 the integrated graphics device. 594 595config ROM_TABLE_ADDR 596 hex 597 default 0xf0000 598 help 599 All x86 tables happen to like the address range from 0x0f0000 600 to 0x100000. We use 0xf0000 as the starting address to store 601 those tables, including PIRQ routing table, Multi-Processor 602 table and ACPI table. 603 604config ROM_TABLE_SIZE 605 hex 606 default 0x10000 607 608menu "System tables" 609 depends on !EFI && !SYS_COREBOOT 610 611config GENERATE_PIRQ_TABLE 612 bool "Generate a PIRQ table" 613 default n 614 help 615 Generate a PIRQ routing table for this board. The PIRQ routing table 616 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 617 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 618 It specifies the interrupt router information as well how all the PCI 619 devices' interrupt pins are wired to PIRQs. 620 621config GENERATE_SFI_TABLE 622 bool "Generate a SFI (Simple Firmware Interface) table" 623 help 624 The Simple Firmware Interface (SFI) provides a lightweight method 625 for platform firmware to pass information to the operating system 626 via static tables in memory. Kernel SFI support is required to 627 boot on SFI-only platforms. If you have ACPI tables then these are 628 used instead. 629 630 U-Boot writes this table in write_sfi_table() just before booting 631 the OS. 632 633 For more information, see http://simplefirmware.org 634 635config GENERATE_MP_TABLE 636 bool "Generate an MP (Multi-Processor) table" 637 default n 638 help 639 Generate an MP (Multi-Processor) table for this board. The MP table 640 provides a way for the operating system to support for symmetric 641 multiprocessing as well as symmetric I/O interrupt handling with 642 the local APIC and I/O APIC. 643 644config GENERATE_ACPI_TABLE 645 bool "Generate an ACPI (Advanced Configuration and Power Interface) table" 646 default n 647 select QFW if QEMU 648 help 649 The Advanced Configuration and Power Interface (ACPI) specification 650 provides an open standard for device configuration and management 651 by the operating system. It defines platform-independent interfaces 652 for configuration and power management monitoring. 653 654endmenu 655 656config HAVE_ACPI_RESUME 657 bool "Enable ACPI S3 resume" 658 select ENABLE_MRC_CACHE 659 help 660 Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping 661 state where all system context is lost except system memory. U-Boot 662 is responsible for restoring the machine state as it was before sleep. 663 It needs restore the memory controller, without overwriting memory 664 which is not marked as reserved. For the peripherals which lose their 665 registers, U-Boot needs to write the original value. When everything 666 is done, U-Boot needs to find out the wakeup vector provided by OSes 667 and jump there. 668 669config S3_VGA_ROM_RUN 670 bool "Re-run VGA option ROMs on S3 resume" 671 depends on HAVE_ACPI_RESUME 672 help 673 Execute VGA option ROMs in U-Boot when resuming from S3. Normally 674 this is needed when graphics console is being used in the kernel. 675 676 Turning it off can reduce some resume time, but be aware that your 677 graphics console won't work without VGA options ROMs. Set it to N 678 if your kernel is only on a serial console. 679 680config STACK_SIZE 681 hex 682 depends on HAVE_ACPI_RESUME 683 default 0x1000 684 help 685 Estimated U-Boot's runtime stack size that needs to be reserved 686 during an ACPI S3 resume. 687 688config MAX_PIRQ_LINKS 689 int 690 default 8 691 help 692 This variable specifies the number of PIRQ interrupt links which are 693 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 694 Some newer chipsets offer more than four links, commonly up to PIRQH. 695 696config IRQ_SLOT_COUNT 697 int 698 default 128 699 help 700 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 701 which in turns forms a table of exact 4KiB. The default value 128 702 should be enough for most boards. If this does not fit your board, 703 change it according to your needs. 704 705config PCIE_ECAM_BASE 706 hex 707 default 0xe0000000 708 help 709 This is the memory-mapped address of PCI configuration space, which 710 is only available through the Enhanced Configuration Access 711 Mechanism (ECAM) with PCI Express. It can be set up almost 712 anywhere. Before it is set up, it is possible to access PCI 713 configuration space through I/O access, but memory access is more 714 convenient. Using this, PCI can be scanned and configured. This 715 should be set to a region that does not conflict with memory 716 assigned to PCI devices - i.e. the memory and prefetch regions, as 717 passed to pci_set_region(). 718 719config PCIE_ECAM_SIZE 720 hex 721 default 0x10000000 722 help 723 This is the size of memory-mapped address of PCI configuration space, 724 which is only available through the Enhanced Configuration Access 725 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, 726 so a default 0x10000000 size covers all of the 256 buses which is the 727 maximum number of PCI buses as defined by the PCI specification. 728 729config I8259_PIC 730 bool 731 default y 732 help 733 Intel 8259 ISA compatible chipset incorporates two 8259 (master and 734 slave) interrupt controllers. Include this to have U-Boot set up 735 the interrupt correctly. 736 737config I8254_TIMER 738 bool 739 default y 740 help 741 Intel 8254 timer contains three counters which have fixed uses. 742 Include this to have U-Boot set up the timer correctly. 743 744config SEABIOS 745 bool "Support booting SeaBIOS" 746 help 747 SeaBIOS is an open source implementation of a 16-bit X86 BIOS. 748 It can run in an emulator or natively on X86 hardware with the use 749 of coreboot/U-Boot. By turning on this option, U-Boot prepares 750 all the configuration tables that are necessary to boot SeaBIOS. 751 752 Check http://www.seabios.org/SeaBIOS for details. 753 754config HIGH_TABLE_SIZE 755 hex "Size of configuration tables which reside in high memory" 756 default 0x10000 757 depends on SEABIOS 758 help 759 SeaBIOS itself resides in E seg and F seg, where U-Boot puts all 760 configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot 761 puts a copy of configuration tables in high memory region which 762 is reserved on the stack before relocation. The region size is 763 determined by this option. 764 765 Increse it if the default size does not fit the board's needs. 766 This is most likely due to a large ACPI DSDT table is used. 767 768source "arch/x86/lib/efi/Kconfig" 769 770endmenu 771