xref: /openbmc/u-boot/arch/x86/Kconfig (revision dffceb4b) 
1menu "x86 architecture"
2	depends on X86
3
4config SYS_ARCH
5	default "x86"
6
7choice
8	prompt "Mainboard vendor"
9	default VENDOR_EMULATION
10
11config VENDOR_COREBOOT
12	bool "coreboot"
13
14config VENDOR_EFI
15	bool "efi"
16
17config VENDOR_EMULATION
18	bool "emulation"
19
20config VENDOR_GOOGLE
21	bool "Google"
22
23config VENDOR_INTEL
24	bool "Intel"
25
26endchoice
27
28# board-specific options below
29source "board/coreboot/Kconfig"
30source "board/efi/Kconfig"
31source "board/emulation/Kconfig"
32source "board/google/Kconfig"
33source "board/intel/Kconfig"
34
35# platform-specific options below
36source "arch/x86/cpu/baytrail/Kconfig"
37source "arch/x86/cpu/coreboot/Kconfig"
38source "arch/x86/cpu/ivybridge/Kconfig"
39source "arch/x86/cpu/qemu/Kconfig"
40source "arch/x86/cpu/quark/Kconfig"
41source "arch/x86/cpu/queensbay/Kconfig"
42
43# architecture-specific options below
44
45config SYS_MALLOC_F_LEN
46	default 0x800
47
48config RAMBASE
49	hex
50	default 0x100000
51
52config XIP_ROM_SIZE
53	hex
54	depends on X86_RESET_VECTOR
55	default ROM_SIZE
56
57config CPU_ADDR_BITS
58	int
59	default 36
60
61config HPET_ADDRESS
62	hex
63	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
64
65config SMM_TSEG
66	bool
67	default n
68
69config SMM_TSEG_SIZE
70	hex
71
72config X86_RESET_VECTOR
73	bool
74	default n
75
76config RESET_SEG_START
77	hex
78	depends on X86_RESET_VECTOR
79	default 0xffff0000
80
81config RESET_SEG_SIZE
82	hex
83	depends on X86_RESET_VECTOR
84	default 0x10000
85
86config RESET_VEC_LOC
87	hex
88	depends on X86_RESET_VECTOR
89	default 0xfffffff0
90
91config SYS_X86_START16
92	hex
93	depends on X86_RESET_VECTOR
94	default 0xfffff800
95
96config BOARD_ROMSIZE_KB_512
97	bool
98config BOARD_ROMSIZE_KB_1024
99	bool
100config BOARD_ROMSIZE_KB_2048
101	bool
102config BOARD_ROMSIZE_KB_4096
103	bool
104config BOARD_ROMSIZE_KB_8192
105	bool
106config BOARD_ROMSIZE_KB_16384
107	bool
108
109choice
110	prompt "ROM chip size"
111	depends on X86_RESET_VECTOR
112	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
113	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
114	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
115	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
116	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
117	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
118	help
119	  Select the size of the ROM chip you intend to flash U-Boot on.
120
121	  The build system will take care of creating a u-boot.rom file
122	  of the matching size.
123
124config UBOOT_ROMSIZE_KB_512
125	bool "512 KB"
126	help
127	  Choose this option if you have a 512 KB ROM chip.
128
129config UBOOT_ROMSIZE_KB_1024
130	bool "1024 KB (1 MB)"
131	help
132	  Choose this option if you have a 1024 KB (1 MB) ROM chip.
133
134config UBOOT_ROMSIZE_KB_2048
135	bool "2048 KB (2 MB)"
136	help
137	  Choose this option if you have a 2048 KB (2 MB) ROM chip.
138
139config UBOOT_ROMSIZE_KB_4096
140	bool "4096 KB (4 MB)"
141	help
142	  Choose this option if you have a 4096 KB (4 MB) ROM chip.
143
144config UBOOT_ROMSIZE_KB_8192
145	bool "8192 KB (8 MB)"
146	help
147	  Choose this option if you have a 8192 KB (8 MB) ROM chip.
148
149config UBOOT_ROMSIZE_KB_16384
150	bool "16384 KB (16 MB)"
151	help
152	  Choose this option if you have a 16384 KB (16 MB) ROM chip.
153
154endchoice
155
156# Map the config names to an integer (KB).
157config UBOOT_ROMSIZE_KB
158	int
159	default 512 if UBOOT_ROMSIZE_KB_512
160	default 1024 if UBOOT_ROMSIZE_KB_1024
161	default 2048 if UBOOT_ROMSIZE_KB_2048
162	default 4096 if UBOOT_ROMSIZE_KB_4096
163	default 8192 if UBOOT_ROMSIZE_KB_8192
164	default 16384 if UBOOT_ROMSIZE_KB_16384
165
166# Map the config names to a hex value (bytes).
167config ROM_SIZE
168	hex
169	default 0x80000 if UBOOT_ROMSIZE_KB_512
170	default 0x100000 if UBOOT_ROMSIZE_KB_1024
171	default 0x200000 if UBOOT_ROMSIZE_KB_2048
172	default 0x400000 if UBOOT_ROMSIZE_KB_4096
173	default 0x800000 if UBOOT_ROMSIZE_KB_8192
174	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
175	default 0x1000000 if UBOOT_ROMSIZE_KB_16384
176
177config HAVE_INTEL_ME
178	bool "Platform requires Intel Management Engine"
179	help
180	  Newer higher-end devices have an Intel Management Engine (ME)
181	  which is a very large binary blob (typically 1.5MB) which is
182	  required for the platform to work. This enforces a particular
183	  SPI flash format. You will need to supply the me.bin file in
184	  your board directory.
185
186config X86_RAMTEST
187	bool "Perform a simple RAM test after SDRAM initialisation"
188	help
189	  If there is something wrong with SDRAM then the platform will
190	  often crash within U-Boot or the kernel. This option enables a
191	  very simple RAM test that quickly checks whether the SDRAM seems
192	  to work correctly. It is not exhaustive but can save time by
193	  detecting obvious failures.
194
195config HAVE_FSP
196	bool "Add an Firmware Support Package binary"
197	depends on !EFI
198	help
199	  Select this option to add an Firmware Support Package binary to
200	  the resulting U-Boot image. It is a binary blob which U-Boot uses
201	  to set up SDRAM and other chipset specific initialization.
202
203	  Note: Without this binary U-Boot will not be able to set up its
204	  SDRAM so will not boot.
205
206config FSP_FILE
207	string "Firmware Support Package binary filename"
208	depends on HAVE_FSP
209	default "fsp.bin"
210	help
211	  The filename of the file to use as Firmware Support Package binary
212	  in the board directory.
213
214config FSP_ADDR
215	hex "Firmware Support Package binary location"
216	depends on HAVE_FSP
217	default 0xfffc0000
218	help
219	  FSP is not Position Independent Code (PIC) and the whole FSP has to
220	  be rebased if it is placed at a location which is different from the
221	  perferred base address specified during the FSP build. Use Intel's
222	  Binary Configuration Tool (BCT) to do the rebase.
223
224	  The default base address of 0xfffc0000 indicates that the binary must
225	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
226
227config FSP_TEMP_RAM_ADDR
228	hex
229	depends on HAVE_FSP
230	default 0x2000000
231	help
232	  Stack top address which is used in fsp_init() after DRAM is ready and
233	  CAR is disabled.
234
235config FSP_SYS_MALLOC_F_LEN
236	hex
237	depends on HAVE_FSP
238	default 0x100000
239	help
240	  Additional size of malloc() pool before relocation.
241
242config FSP_USE_UPD
243	bool
244	depends on HAVE_FSP
245	default y
246	help
247	  Most FSPs use UPD data region for some FSP customization. But there
248	  are still some FSPs that might not even have UPD. For such FSPs,
249	  override this to n in their platform Kconfig files.
250
251config ENABLE_MRC_CACHE
252	bool "Enable MRC cache"
253	depends on !EFI && !SYS_COREBOOT
254	help
255	  Enable this feature to cause MRC data to be cached in NV storage
256	  to be used for speeding up boot time on future reboots and/or
257	  power cycles.
258
259config SMP
260	bool "Enable Symmetric Multiprocessing"
261	default n
262	help
263	  Enable use of more than one CPU in U-Boot and the Operating System
264	  when loaded. Each CPU will be started up and information can be
265	  obtained using the 'cpu' command. If this option is disabled, then
266	  only one CPU will be enabled regardless of the number of CPUs
267	  available.
268
269config MAX_CPUS
270	int "Maximum number of CPUs permitted"
271	depends on SMP
272	default 4
273	help
274	  When using multi-CPU chips it is possible for U-Boot to start up
275	  more than one CPU. The stack memory used by all of these CPUs is
276	  pre-allocated so at present U-Boot wants to know the maximum
277	  number of CPUs that may be present. Set this to at least as high
278	  as the number of CPUs in your system (it uses about 4KB of RAM for
279	  each CPU).
280
281config AP_STACK_SIZE
282	hex
283	depends on SMP
284	default 0x1000
285	help
286	  Each additional CPU started by U-Boot requires its own stack. This
287	  option sets the stack size used by each CPU and directly affects
288	  the memory used by this initialisation process. Typically 4KB is
289	  enough space.
290
291config HAVE_VGA_BIOS
292	bool "Add a VGA BIOS image"
293	help
294	  Select this option if you have a VGA BIOS image that you would
295	  like to add to your ROM.
296
297config VGA_BIOS_FILE
298	string "VGA BIOS image filename"
299	depends on HAVE_VGA_BIOS
300	default "vga.bin"
301	help
302	  The filename of the VGA BIOS image in the board directory.
303
304config VGA_BIOS_ADDR
305	hex "VGA BIOS image location"
306	depends on HAVE_VGA_BIOS
307	default 0xfff90000
308	help
309	  The location of VGA BIOS image in the SPI flash. For example, base
310	  address of 0xfff90000 indicates that the image will be put at offset
311	  0x90000 from the beginning of a 1MB flash device.
312
313menu "System tables"
314	depends on !EFI && !SYS_COREBOOT
315
316config GENERATE_PIRQ_TABLE
317	bool "Generate a PIRQ table"
318	default n
319	help
320	  Generate a PIRQ routing table for this board. The PIRQ routing table
321	  is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
322	  at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
323	  It specifies the interrupt router information as well how all the PCI
324	  devices' interrupt pins are wired to PIRQs.
325
326config GENERATE_SFI_TABLE
327	bool "Generate a SFI (Simple Firmware Interface) table"
328	help
329	  The Simple Firmware Interface (SFI) provides a lightweight method
330	  for platform firmware to pass information to the operating system
331	  via static tables in memory.  Kernel SFI support is required to
332	  boot on SFI-only platforms.  If you have ACPI tables then these are
333	  used instead.
334
335	  U-Boot writes this table in write_sfi_table() just before booting
336	  the OS.
337
338	  For more information, see http://simplefirmware.org
339
340config GENERATE_MP_TABLE
341	bool "Generate an MP (Multi-Processor) table"
342	default n
343	help
344	  Generate an MP (Multi-Processor) table for this board. The MP table
345	  provides a way for the operating system to support for symmetric
346	  multiprocessing as well as symmetric I/O interrupt handling with
347	  the local APIC and I/O APIC.
348
349config GENERATE_ACPI_TABLE
350	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
351	default n
352	help
353	  The Advanced Configuration and Power Interface (ACPI) specification
354	  provides an open standard for device configuration and management
355	  by the operating system. It defines platform-independent interfaces
356	  for configuration and power management monitoring.
357
358config QEMU_ACPI_TABLE
359	bool "Load ACPI table from QEMU fw_cfg interface"
360	depends on GENERATE_ACPI_TABLE && QEMU
361	default y
362	help
363	  By default, U-Boot generates its own ACPI tables. This option, if
364	  enabled, disables U-Boot's version and loads ACPI tables generated
365	  by QEMU.
366
367config GENERATE_SMBIOS_TABLE
368	bool "Generate an SMBIOS (System Management BIOS) table"
369	default y
370	help
371	  The System Management BIOS (SMBIOS) specification addresses how
372	  motherboard and system vendors present management information about
373	  their products in a standard format by extending the BIOS interface
374	  on Intel architecture systems.
375
376	  Check http://www.dmtf.org/standards/smbios for details.
377
378endmenu
379
380config MAX_PIRQ_LINKS
381	int
382	default 8
383	help
384	  This variable specifies the number of PIRQ interrupt links which are
385	  routable. On most older chipsets, this is 4, PIRQA through PIRQD.
386	  Some newer chipsets offer more than four links, commonly up to PIRQH.
387
388config IRQ_SLOT_COUNT
389	int
390	default 128
391	help
392	  U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
393	  which in turns forms a table of exact 4KiB. The default value 128
394	  should be enough for most boards. If this does not fit your board,
395	  change it according to your needs.
396
397config PCIE_ECAM_BASE
398	hex
399	default 0xe0000000
400	help
401	  This is the memory-mapped address of PCI configuration space, which
402	  is only available through the Enhanced Configuration Access
403	  Mechanism (ECAM) with PCI Express. It can be set up almost
404	  anywhere. Before it is set up, it is possible to access PCI
405	  configuration space through I/O access, but memory access is more
406	  convenient. Using this, PCI can be scanned and configured. This
407	  should be set to a region that does not conflict with memory
408	  assigned to PCI devices - i.e. the memory and prefetch regions, as
409	  passed to pci_set_region().
410
411config PCIE_ECAM_SIZE
412	hex
413	default 0x10000000
414	help
415	  This is the size of memory-mapped address of PCI configuration space,
416	  which is only available through the Enhanced Configuration Access
417	  Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
418	  so a default 0x10000000 size covers all of the 256 buses which is the
419	  maximum number of PCI buses as defined by the PCI specification.
420
421config I8259_PIC
422	bool
423	default y
424	help
425	  Intel 8259 ISA compatible chipset incorporates two 8259 (master and
426	  slave) interrupt controllers. Include this to have U-Boot set up
427	  the interrupt correctly.
428
429config I8254_TIMER
430	bool
431	default y
432	help
433	  Intel 8254 timer contains three counters which have fixed uses.
434	  Include this to have U-Boot set up the timer correctly.
435
436config I8042_KEYB
437	default y
438
439config DM_KEYBOARD
440	default y
441
442source "arch/x86/lib/efi/Kconfig"
443
444endmenu
445