1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7config USE_PRIVATE_LIBGCC 8 default y 9 10choice 11 prompt "Target select" 12 13config TARGET_COREBOOT 14 bool "Support coreboot" 15 help 16 This target is used for running U-Boot on top of Coreboot. In 17 this case Coreboot does the early inititalisation, and U-Boot 18 takes over once the RAM, video and CPU are fully running. 19 U-Boot is loaded as a fallback payload from Coreboot, in 20 Coreboot terminology. This method was used for the Chromebook 21 Pixel when launched. 22 23config TARGET_CHROMEBOOK_LINK 24 bool "Support Chromebook link" 25 help 26 This is the Chromebook Pixel released in 2013. It uses an Intel 27 i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of 28 SDRAM. It has a Panther Point platform controller hub, PCIe 29 WiFi and Bluetooth. It also includes a 720p webcam, USB SD 30 reader, microphone and speakers, display port and 32GB SATA 31 solid state drive. There is a Chrome OS EC connected on LPC, 32 and it provides a 2560x1700 high resolution touch-enabled LCD 33 display. 34 35config TARGET_CHROMEBOX_PANTHER 36 bool "Support Chromebox panther (not available)" 37 select n 38 help 39 Note: At present this must be used with Coreboot. See README.x86 40 for instructions. 41 42 This is the Asus Chromebox CN60 released in 2014. It uses an Intel 43 Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a 44 Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also 45 includes a USB SD reader, four USB3 ports, display port and HDMI 46 video output and a 16GB SATA solid state drive. There is no Chrome 47 OS EC on this model. 48 49config TARGET_CROWNBAY 50 bool "Support Intel Crown Bay CRB" 51 help 52 This is the Intel Crown Bay Customer Reference Board. It contains 53 the Intel Atom Processor E6xx populated on the COM Express module 54 with 1GB DDR2 soldered down memory and a carrier board with the 55 Intel Platform Controller Hub EG20T, other system components and 56 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS. 57 58config TARGET_MINNOWMAX 59 bool "Support Intel Minnowboard MAX" 60 help 61 This is the Intel Minnowboard MAX. It contains an Atom E3800 62 processor in a small form factor with Ethernet, micro-SD, USB 2, 63 USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out. 64 It requires some binary blobs - see README.x86 for details. 65 66 Note that PCIE_ECAM_BASE is set up by the FSP so the value used 67 by U-Boot matches that value. 68 69config TARGET_GALILEO 70 bool "Support Intel Galileo" 71 help 72 This is the Intel Galileo board, which is the first in a family of 73 Arduino-certified development and prototyping boards based on Intel 74 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit 75 single-core, single-thread, Intel Pentium processor instrunction set 76 architecture (ISA) compatible, operating at speeds up to 400Mhz, 77 along with 256MB DDR3 memory. It supports a wide range of industry 78 standard I/O interfaces, including a full-sized mini-PCIe slot, 79 one 100Mb Ethernet port, a microSD card slot, a USB host port and 80 a USB client port. 81 82endchoice 83 84config DM 85 default y 86 87config DM_GPIO 88 default y 89 90config DM_SERIAL 91 default y 92 93config SYS_MALLOC_F_LEN 94 default 0x800 95 96config RAMBASE 97 hex 98 default 0x100000 99 100config XIP_ROM_SIZE 101 hex 102 depends on X86_RESET_VECTOR 103 default ROM_SIZE 104 105config CPU_ADDR_BITS 106 int 107 default 36 108 109config HPET_ADDRESS 110 hex 111 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 112 113config SMM_TSEG 114 bool 115 default n 116 117config SMM_TSEG_SIZE 118 hex 119 120config X86_RESET_VECTOR 121 bool 122 default n 123 124config SYS_X86_START16 125 hex 126 depends on X86_RESET_VECTOR 127 default 0xfffff800 128 129config BOARD_ROMSIZE_KB_512 130 bool 131config BOARD_ROMSIZE_KB_1024 132 bool 133config BOARD_ROMSIZE_KB_2048 134 bool 135config BOARD_ROMSIZE_KB_4096 136 bool 137config BOARD_ROMSIZE_KB_8192 138 bool 139config BOARD_ROMSIZE_KB_16384 140 bool 141 142choice 143 prompt "ROM chip size" 144 depends on X86_RESET_VECTOR 145 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 146 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 147 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 148 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 149 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 150 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 151 help 152 Select the size of the ROM chip you intend to flash U-Boot on. 153 154 The build system will take care of creating a u-boot.rom file 155 of the matching size. 156 157config UBOOT_ROMSIZE_KB_512 158 bool "512 KB" 159 help 160 Choose this option if you have a 512 KB ROM chip. 161 162config UBOOT_ROMSIZE_KB_1024 163 bool "1024 KB (1 MB)" 164 help 165 Choose this option if you have a 1024 KB (1 MB) ROM chip. 166 167config UBOOT_ROMSIZE_KB_2048 168 bool "2048 KB (2 MB)" 169 help 170 Choose this option if you have a 2048 KB (2 MB) ROM chip. 171 172config UBOOT_ROMSIZE_KB_4096 173 bool "4096 KB (4 MB)" 174 help 175 Choose this option if you have a 4096 KB (4 MB) ROM chip. 176 177config UBOOT_ROMSIZE_KB_8192 178 bool "8192 KB (8 MB)" 179 help 180 Choose this option if you have a 8192 KB (8 MB) ROM chip. 181 182config UBOOT_ROMSIZE_KB_16384 183 bool "16384 KB (16 MB)" 184 help 185 Choose this option if you have a 16384 KB (16 MB) ROM chip. 186 187endchoice 188 189# Map the config names to an integer (KB). 190config UBOOT_ROMSIZE_KB 191 int 192 default 512 if UBOOT_ROMSIZE_KB_512 193 default 1024 if UBOOT_ROMSIZE_KB_1024 194 default 2048 if UBOOT_ROMSIZE_KB_2048 195 default 4096 if UBOOT_ROMSIZE_KB_4096 196 default 8192 if UBOOT_ROMSIZE_KB_8192 197 default 16384 if UBOOT_ROMSIZE_KB_16384 198 199# Map the config names to a hex value (bytes). 200config ROM_SIZE 201 hex 202 default 0x80000 if UBOOT_ROMSIZE_KB_512 203 default 0x100000 if UBOOT_ROMSIZE_KB_1024 204 default 0x200000 if UBOOT_ROMSIZE_KB_2048 205 default 0x400000 if UBOOT_ROMSIZE_KB_4096 206 default 0x800000 if UBOOT_ROMSIZE_KB_8192 207 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 208 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 209 210config HAVE_INTEL_ME 211 bool "Platform requires Intel Management Engine" 212 help 213 Newer higher-end devices have an Intel Management Engine (ME) 214 which is a very large binary blob (typically 1.5MB) which is 215 required for the platform to work. This enforces a particular 216 SPI flash format. You will need to supply the me.bin file in 217 your board directory. 218 219config X86_RAMTEST 220 bool "Perform a simple RAM test after SDRAM initialisation" 221 help 222 If there is something wrong with SDRAM then the platform will 223 often crash within U-Boot or the kernel. This option enables a 224 very simple RAM test that quickly checks whether the SDRAM seems 225 to work correctly. It is not exhaustive but can save time by 226 detecting obvious failures. 227 228config MARK_GRAPHICS_MEM_WRCOMB 229 bool "Mark graphics memory as write-combining." 230 default n 231 help 232 The graphics performance may increase if the graphics 233 memory is set as write-combining cache type. This option 234 enables marking the graphics memory as write-combining. 235 236menu "Display" 237 238config FRAMEBUFFER_SET_VESA_MODE 239 prompt "Set framebuffer graphics resolution" 240 bool 241 help 242 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) 243 244choice 245 prompt "framebuffer graphics resolution" 246 default FRAMEBUFFER_VESA_MODE_117 247 depends on FRAMEBUFFER_SET_VESA_MODE 248 help 249 This option sets the resolution used for the coreboot framebuffer (and 250 bootsplash screen). 251 252config FRAMEBUFFER_VESA_MODE_100 253 bool "640x400 256-color" 254 255config FRAMEBUFFER_VESA_MODE_101 256 bool "640x480 256-color" 257 258config FRAMEBUFFER_VESA_MODE_102 259 bool "800x600 16-color" 260 261config FRAMEBUFFER_VESA_MODE_103 262 bool "800x600 256-color" 263 264config FRAMEBUFFER_VESA_MODE_104 265 bool "1024x768 16-color" 266 267config FRAMEBUFFER_VESA_MODE_105 268 bool "1024x7686 256-color" 269 270config FRAMEBUFFER_VESA_MODE_106 271 bool "1280x1024 16-color" 272 273config FRAMEBUFFER_VESA_MODE_107 274 bool "1280x1024 256-color" 275 276config FRAMEBUFFER_VESA_MODE_108 277 bool "80x60 text" 278 279config FRAMEBUFFER_VESA_MODE_109 280 bool "132x25 text" 281 282config FRAMEBUFFER_VESA_MODE_10A 283 bool "132x43 text" 284 285config FRAMEBUFFER_VESA_MODE_10B 286 bool "132x50 text" 287 288config FRAMEBUFFER_VESA_MODE_10C 289 bool "132x60 text" 290 291config FRAMEBUFFER_VESA_MODE_10D 292 bool "320x200 32k-color (1:5:5:5)" 293 294config FRAMEBUFFER_VESA_MODE_10E 295 bool "320x200 64k-color (5:6:5)" 296 297config FRAMEBUFFER_VESA_MODE_10F 298 bool "320x200 16.8M-color (8:8:8)" 299 300config FRAMEBUFFER_VESA_MODE_110 301 bool "640x480 32k-color (1:5:5:5)" 302 303config FRAMEBUFFER_VESA_MODE_111 304 bool "640x480 64k-color (5:6:5)" 305 306config FRAMEBUFFER_VESA_MODE_112 307 bool "640x480 16.8M-color (8:8:8)" 308 309config FRAMEBUFFER_VESA_MODE_113 310 bool "800x600 32k-color (1:5:5:5)" 311 312config FRAMEBUFFER_VESA_MODE_114 313 bool "800x600 64k-color (5:6:5)" 314 315config FRAMEBUFFER_VESA_MODE_115 316 bool "800x600 16.8M-color (8:8:8)" 317 318config FRAMEBUFFER_VESA_MODE_116 319 bool "1024x768 32k-color (1:5:5:5)" 320 321config FRAMEBUFFER_VESA_MODE_117 322 bool "1024x768 64k-color (5:6:5)" 323 324config FRAMEBUFFER_VESA_MODE_118 325 bool "1024x768 16.8M-color (8:8:8)" 326 327config FRAMEBUFFER_VESA_MODE_119 328 bool "1280x1024 32k-color (1:5:5:5)" 329 330config FRAMEBUFFER_VESA_MODE_11A 331 bool "1280x1024 64k-color (5:6:5)" 332 333config FRAMEBUFFER_VESA_MODE_11B 334 bool "1280x1024 16.8M-color (8:8:8)" 335 336config FRAMEBUFFER_VESA_MODE_USER 337 bool "Manually select VESA mode" 338 339endchoice 340 341# Map the config names to an integer (KB). 342config FRAMEBUFFER_VESA_MODE 343 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER 344 hex 345 default 0x100 if FRAMEBUFFER_VESA_MODE_100 346 default 0x101 if FRAMEBUFFER_VESA_MODE_101 347 default 0x102 if FRAMEBUFFER_VESA_MODE_102 348 default 0x103 if FRAMEBUFFER_VESA_MODE_103 349 default 0x104 if FRAMEBUFFER_VESA_MODE_104 350 default 0x105 if FRAMEBUFFER_VESA_MODE_105 351 default 0x106 if FRAMEBUFFER_VESA_MODE_106 352 default 0x107 if FRAMEBUFFER_VESA_MODE_107 353 default 0x108 if FRAMEBUFFER_VESA_MODE_108 354 default 0x109 if FRAMEBUFFER_VESA_MODE_109 355 default 0x10A if FRAMEBUFFER_VESA_MODE_10A 356 default 0x10B if FRAMEBUFFER_VESA_MODE_10B 357 default 0x10C if FRAMEBUFFER_VESA_MODE_10C 358 default 0x10D if FRAMEBUFFER_VESA_MODE_10D 359 default 0x10E if FRAMEBUFFER_VESA_MODE_10E 360 default 0x10F if FRAMEBUFFER_VESA_MODE_10F 361 default 0x110 if FRAMEBUFFER_VESA_MODE_110 362 default 0x111 if FRAMEBUFFER_VESA_MODE_111 363 default 0x112 if FRAMEBUFFER_VESA_MODE_112 364 default 0x113 if FRAMEBUFFER_VESA_MODE_113 365 default 0x114 if FRAMEBUFFER_VESA_MODE_114 366 default 0x115 if FRAMEBUFFER_VESA_MODE_115 367 default 0x116 if FRAMEBUFFER_VESA_MODE_116 368 default 0x117 if FRAMEBUFFER_VESA_MODE_117 369 default 0x118 if FRAMEBUFFER_VESA_MODE_118 370 default 0x119 if FRAMEBUFFER_VESA_MODE_119 371 default 0x11A if FRAMEBUFFER_VESA_MODE_11A 372 default 0x11B if FRAMEBUFFER_VESA_MODE_11B 373 default 0x117 if FRAMEBUFFER_VESA_MODE_USER 374 375endmenu 376 377config HAVE_FSP 378 bool "Add an Firmware Support Package binary" 379 help 380 Select this option to add an Firmware Support Package binary to 381 the resulting U-Boot image. It is a binary blob which U-Boot uses 382 to set up SDRAM and other chipset specific initialization. 383 384 Note: Without this binary U-Boot will not be able to set up its 385 SDRAM so will not boot. 386 387config FSP_FILE 388 string "Firmware Support Package binary filename" 389 depends on HAVE_FSP 390 default "fsp.bin" 391 help 392 The filename of the file to use as Firmware Support Package binary 393 in the board directory. 394 395config FSP_ADDR 396 hex "Firmware Support Package binary location" 397 depends on HAVE_FSP 398 default 0xfffc0000 399 help 400 FSP is not Position Independent Code (PIC) and the whole FSP has to 401 be rebased if it is placed at a location which is different from the 402 perferred base address specified during the FSP build. Use Intel's 403 Binary Configuration Tool (BCT) to do the rebase. 404 405 The default base address of 0xfffc0000 indicates that the binary must 406 be located at offset 0xc0000 from the beginning of a 1MB flash device. 407 408config FSP_TEMP_RAM_ADDR 409 hex 410 default 0x2000000 411 help 412 Stack top address which is used in FspInit after DRAM is ready and 413 CAR is disabled. 414 415source "arch/x86/cpu/baytrail/Kconfig" 416 417source "arch/x86/cpu/coreboot/Kconfig" 418 419source "arch/x86/cpu/ivybridge/Kconfig" 420 421source "arch/x86/cpu/quark/Kconfig" 422 423source "arch/x86/cpu/queensbay/Kconfig" 424 425config TSC_CALIBRATION_BYPASS 426 bool "Bypass Time-Stamp Counter (TSC) calibration" 427 default n 428 help 429 By default U-Boot automatically calibrates Time-Stamp Counter (TSC) 430 running frequency via Model-Specific Register (MSR) and Programmable 431 Interval Timer (PIT). If the calibration does not work on your board, 432 select this option and provide a hardcoded TSC running frequency with 433 CONFIG_TSC_FREQ_IN_MHZ below. 434 435 Normally this option should be turned on in a simulation environment 436 like qemu. 437 438config TSC_FREQ_IN_MHZ 439 int "Time-Stamp Counter (TSC) running frequency in MHz" 440 depends on TSC_CALIBRATION_BYPASS 441 default 1000 442 help 443 The running frequency in MHz of Time-Stamp Counter (TSC). 444 445source "board/coreboot/coreboot/Kconfig" 446 447source "board/google/chromebook_link/Kconfig" 448 449source "board/google/chromebox_panther/Kconfig" 450 451source "board/intel/crownbay/Kconfig" 452 453source "board/intel/minnowmax/Kconfig" 454 455source "board/intel/galileo/Kconfig" 456 457config PCIE_ECAM_BASE 458 hex 459 default 0xe0000000 460 help 461 This is the memory-mapped address of PCI configuration space, which 462 is only available through the Enhanced Configuration Access 463 Mechanism (ECAM) with PCI Express. It can be set up almost 464 anywhere. Before it is set up, it is possible to access PCI 465 configuration space through I/O access, but memory access is more 466 convenient. Using this, PCI can be scanned and configured. This 467 should be set to a region that does not conflict with memory 468 assigned to PCI devices - i.e. the memory and prefetch regions, as 469 passed to pci_set_region(). 470 471endmenu 472