1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Mainboard vendor" 9 default VENDOR_EMULATION 10 11config VENDOR_COREBOOT 12 bool "coreboot" 13 14config VENDOR_EFI 15 bool "efi" 16 17config VENDOR_EMULATION 18 bool "emulation" 19 20config VENDOR_GOOGLE 21 bool "Google" 22 23config VENDOR_INTEL 24 bool "Intel" 25 26endchoice 27 28# board-specific options below 29source "board/coreboot/Kconfig" 30source "board/efi/Kconfig" 31source "board/emulation/Kconfig" 32source "board/google/Kconfig" 33source "board/intel/Kconfig" 34 35# platform-specific options below 36source "arch/x86/cpu/baytrail/Kconfig" 37source "arch/x86/cpu/coreboot/Kconfig" 38source "arch/x86/cpu/ivybridge/Kconfig" 39source "arch/x86/cpu/qemu/Kconfig" 40source "arch/x86/cpu/quark/Kconfig" 41source "arch/x86/cpu/queensbay/Kconfig" 42 43# architecture-specific options below 44 45config SYS_MALLOC_F_LEN 46 default 0x800 47 48config RAMBASE 49 hex 50 default 0x100000 51 52config XIP_ROM_SIZE 53 hex 54 depends on X86_RESET_VECTOR 55 default ROM_SIZE 56 57config CPU_ADDR_BITS 58 int 59 default 36 60 61config HPET_ADDRESS 62 hex 63 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 64 65config SMM_TSEG 66 bool 67 default n 68 69config SMM_TSEG_SIZE 70 hex 71 72config X86_RESET_VECTOR 73 bool 74 default n 75 76config RESET_SEG_START 77 hex 78 depends on X86_RESET_VECTOR 79 default 0xffff0000 80 81config RESET_SEG_SIZE 82 hex 83 depends on X86_RESET_VECTOR 84 default 0x10000 85 86config RESET_VEC_LOC 87 hex 88 depends on X86_RESET_VECTOR 89 default 0xfffffff0 90 91config SYS_X86_START16 92 hex 93 depends on X86_RESET_VECTOR 94 default 0xfffff800 95 96config BOARD_ROMSIZE_KB_512 97 bool 98config BOARD_ROMSIZE_KB_1024 99 bool 100config BOARD_ROMSIZE_KB_2048 101 bool 102config BOARD_ROMSIZE_KB_4096 103 bool 104config BOARD_ROMSIZE_KB_8192 105 bool 106config BOARD_ROMSIZE_KB_16384 107 bool 108 109choice 110 prompt "ROM chip size" 111 depends on X86_RESET_VECTOR 112 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 113 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 114 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 115 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 116 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 117 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 118 help 119 Select the size of the ROM chip you intend to flash U-Boot on. 120 121 The build system will take care of creating a u-boot.rom file 122 of the matching size. 123 124config UBOOT_ROMSIZE_KB_512 125 bool "512 KB" 126 help 127 Choose this option if you have a 512 KB ROM chip. 128 129config UBOOT_ROMSIZE_KB_1024 130 bool "1024 KB (1 MB)" 131 help 132 Choose this option if you have a 1024 KB (1 MB) ROM chip. 133 134config UBOOT_ROMSIZE_KB_2048 135 bool "2048 KB (2 MB)" 136 help 137 Choose this option if you have a 2048 KB (2 MB) ROM chip. 138 139config UBOOT_ROMSIZE_KB_4096 140 bool "4096 KB (4 MB)" 141 help 142 Choose this option if you have a 4096 KB (4 MB) ROM chip. 143 144config UBOOT_ROMSIZE_KB_8192 145 bool "8192 KB (8 MB)" 146 help 147 Choose this option if you have a 8192 KB (8 MB) ROM chip. 148 149config UBOOT_ROMSIZE_KB_16384 150 bool "16384 KB (16 MB)" 151 help 152 Choose this option if you have a 16384 KB (16 MB) ROM chip. 153 154endchoice 155 156# Map the config names to an integer (KB). 157config UBOOT_ROMSIZE_KB 158 int 159 default 512 if UBOOT_ROMSIZE_KB_512 160 default 1024 if UBOOT_ROMSIZE_KB_1024 161 default 2048 if UBOOT_ROMSIZE_KB_2048 162 default 4096 if UBOOT_ROMSIZE_KB_4096 163 default 8192 if UBOOT_ROMSIZE_KB_8192 164 default 16384 if UBOOT_ROMSIZE_KB_16384 165 166# Map the config names to a hex value (bytes). 167config ROM_SIZE 168 hex 169 default 0x80000 if UBOOT_ROMSIZE_KB_512 170 default 0x100000 if UBOOT_ROMSIZE_KB_1024 171 default 0x200000 if UBOOT_ROMSIZE_KB_2048 172 default 0x400000 if UBOOT_ROMSIZE_KB_4096 173 default 0x800000 if UBOOT_ROMSIZE_KB_8192 174 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 175 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 176 177config HAVE_INTEL_ME 178 bool "Platform requires Intel Management Engine" 179 help 180 Newer higher-end devices have an Intel Management Engine (ME) 181 which is a very large binary blob (typically 1.5MB) which is 182 required for the platform to work. This enforces a particular 183 SPI flash format. You will need to supply the me.bin file in 184 your board directory. 185 186config X86_RAMTEST 187 bool "Perform a simple RAM test after SDRAM initialisation" 188 help 189 If there is something wrong with SDRAM then the platform will 190 often crash within U-Boot or the kernel. This option enables a 191 very simple RAM test that quickly checks whether the SDRAM seems 192 to work correctly. It is not exhaustive but can save time by 193 detecting obvious failures. 194 195config HAVE_FSP 196 bool "Add an Firmware Support Package binary" 197 depends on !EFI 198 help 199 Select this option to add an Firmware Support Package binary to 200 the resulting U-Boot image. It is a binary blob which U-Boot uses 201 to set up SDRAM and other chipset specific initialization. 202 203 Note: Without this binary U-Boot will not be able to set up its 204 SDRAM so will not boot. 205 206config FSP_FILE 207 string "Firmware Support Package binary filename" 208 depends on HAVE_FSP 209 default "fsp.bin" 210 help 211 The filename of the file to use as Firmware Support Package binary 212 in the board directory. 213 214config FSP_ADDR 215 hex "Firmware Support Package binary location" 216 depends on HAVE_FSP 217 default 0xfffc0000 218 help 219 FSP is not Position Independent Code (PIC) and the whole FSP has to 220 be rebased if it is placed at a location which is different from the 221 perferred base address specified during the FSP build. Use Intel's 222 Binary Configuration Tool (BCT) to do the rebase. 223 224 The default base address of 0xfffc0000 indicates that the binary must 225 be located at offset 0xc0000 from the beginning of a 1MB flash device. 226 227config FSP_TEMP_RAM_ADDR 228 hex 229 depends on HAVE_FSP 230 default 0x2000000 231 help 232 Stack top address which is used in fsp_init() after DRAM is ready and 233 CAR is disabled. 234 235config FSP_SYS_MALLOC_F_LEN 236 hex 237 depends on HAVE_FSP 238 default 0x100000 239 help 240 Additional size of malloc() pool before relocation. 241 242config FSP_USE_UPD 243 bool 244 depends on HAVE_FSP 245 default y 246 help 247 Most FSPs use UPD data region for some FSP customization. But there 248 are still some FSPs that might not even have UPD. For such FSPs, 249 override this to n in their platform Kconfig files. 250 251config FSP_BROKEN_HOB 252 bool 253 depends on HAVE_FSP 254 help 255 Indicate some buggy FSPs that does not report memory used by FSP 256 itself as reserved in the resource descriptor HOB. Select this to 257 tell U-Boot to do some additional work to ensure U-Boot relocation 258 do not overwrite the important boot service data which is used by 259 FSP, otherwise the subsequent call to fsp_notify() will fail. 260 261config ENABLE_MRC_CACHE 262 bool "Enable MRC cache" 263 depends on !EFI && !SYS_COREBOOT 264 help 265 Enable this feature to cause MRC data to be cached in NV storage 266 to be used for speeding up boot time on future reboots and/or 267 power cycles. 268 269config HAVE_MRC 270 bool "Add a System Agent binary" 271 depends on !HAVE_FSP 272 help 273 Select this option to add a System Agent binary to 274 the resulting U-Boot image. MRC stands for Memory Reference Code. 275 It is a binary blob which U-Boot uses to set up SDRAM. 276 277 Note: Without this binary U-Boot will not be able to set up its 278 SDRAM so will not boot. 279 280config CACHE_MRC_BIN 281 bool 282 depends on HAVE_MRC 283 default n 284 help 285 Enable caching for the memory reference code binary. This uses an 286 MTRR (memory type range register) to turn on caching for the section 287 of SPI flash that contains the memory reference code. This makes 288 SDRAM init run faster. 289 290config CACHE_MRC_SIZE_KB 291 int 292 depends on HAVE_MRC 293 default 512 294 help 295 Sets the size of the cached area for the memory reference code. 296 This ends at the end of SPI flash (address 0xffffffff) and is 297 measured in KB. Typically this is set to 512, providing for 0.5MB 298 of cached space. 299 300config DCACHE_RAM_BASE 301 hex 302 depends on HAVE_MRC 303 help 304 Sets the base of the data cache area in memory space. This is the 305 start address of the cache-as-RAM (CAR) area and the address varies 306 depending on the CPU. Once CAR is set up, read/write memory becomes 307 available at this address and can be used temporarily until SDRAM 308 is working. 309 310config DCACHE_RAM_SIZE 311 hex 312 depends on HAVE_MRC 313 default 0x40000 314 help 315 Sets the total size of the data cache area in memory space. This 316 sets the size of the cache-as-RAM (CAR) area. Note that much of the 317 CAR space is required by the MRC. The CAR space available to U-Boot 318 is normally at the start and typically extends to 1/4 or 1/2 of the 319 available size. 320 321config DCACHE_RAM_MRC_VAR_SIZE 322 hex 323 depends on HAVE_MRC 324 help 325 This is the amount of CAR (Cache as RAM) reserved for use by the 326 memory reference code. This depends on the implementation of the 327 memory reference code and must be set correctly or the board will 328 not boot. 329 330config HAVE_REFCODE 331 bool "Add a Reference Code binary" 332 help 333 Select this option to add a Reference Code binary to the resulting 334 U-Boot image. This is an Intel binary blob that handles system 335 initialisation, in this case the PCH and System Agent. 336 337 Note: Without this binary (on platforms that need it such as 338 broadwell) U-Boot will be missing some critical setup steps. 339 Various peripherals may fail to work. 340 341config SMP 342 bool "Enable Symmetric Multiprocessing" 343 default n 344 help 345 Enable use of more than one CPU in U-Boot and the Operating System 346 when loaded. Each CPU will be started up and information can be 347 obtained using the 'cpu' command. If this option is disabled, then 348 only one CPU will be enabled regardless of the number of CPUs 349 available. 350 351config MAX_CPUS 352 int "Maximum number of CPUs permitted" 353 depends on SMP 354 default 4 355 help 356 When using multi-CPU chips it is possible for U-Boot to start up 357 more than one CPU. The stack memory used by all of these CPUs is 358 pre-allocated so at present U-Boot wants to know the maximum 359 number of CPUs that may be present. Set this to at least as high 360 as the number of CPUs in your system (it uses about 4KB of RAM for 361 each CPU). 362 363config AP_STACK_SIZE 364 hex 365 depends on SMP 366 default 0x1000 367 help 368 Each additional CPU started by U-Boot requires its own stack. This 369 option sets the stack size used by each CPU and directly affects 370 the memory used by this initialisation process. Typically 4KB is 371 enough space. 372 373config HAVE_VGA_BIOS 374 bool "Add a VGA BIOS image" 375 help 376 Select this option if you have a VGA BIOS image that you would 377 like to add to your ROM. 378 379config VGA_BIOS_FILE 380 string "VGA BIOS image filename" 381 depends on HAVE_VGA_BIOS 382 default "vga.bin" 383 help 384 The filename of the VGA BIOS image in the board directory. 385 386config VGA_BIOS_ADDR 387 hex "VGA BIOS image location" 388 depends on HAVE_VGA_BIOS 389 default 0xfff90000 390 help 391 The location of VGA BIOS image in the SPI flash. For example, base 392 address of 0xfff90000 indicates that the image will be put at offset 393 0x90000 from the beginning of a 1MB flash device. 394 395menu "System tables" 396 depends on !EFI && !SYS_COREBOOT 397 398config GENERATE_PIRQ_TABLE 399 bool "Generate a PIRQ table" 400 default n 401 help 402 Generate a PIRQ routing table for this board. The PIRQ routing table 403 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 404 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 405 It specifies the interrupt router information as well how all the PCI 406 devices' interrupt pins are wired to PIRQs. 407 408config GENERATE_SFI_TABLE 409 bool "Generate a SFI (Simple Firmware Interface) table" 410 help 411 The Simple Firmware Interface (SFI) provides a lightweight method 412 for platform firmware to pass information to the operating system 413 via static tables in memory. Kernel SFI support is required to 414 boot on SFI-only platforms. If you have ACPI tables then these are 415 used instead. 416 417 U-Boot writes this table in write_sfi_table() just before booting 418 the OS. 419 420 For more information, see http://simplefirmware.org 421 422config GENERATE_MP_TABLE 423 bool "Generate an MP (Multi-Processor) table" 424 default n 425 help 426 Generate an MP (Multi-Processor) table for this board. The MP table 427 provides a way for the operating system to support for symmetric 428 multiprocessing as well as symmetric I/O interrupt handling with 429 the local APIC and I/O APIC. 430 431config GENERATE_ACPI_TABLE 432 bool "Generate an ACPI (Advanced Configuration and Power Interface) table" 433 default n 434 help 435 The Advanced Configuration and Power Interface (ACPI) specification 436 provides an open standard for device configuration and management 437 by the operating system. It defines platform-independent interfaces 438 for configuration and power management monitoring. 439 440config QEMU_ACPI_TABLE 441 bool "Load ACPI table from QEMU fw_cfg interface" 442 depends on GENERATE_ACPI_TABLE && QEMU 443 default y 444 help 445 By default, U-Boot generates its own ACPI tables. This option, if 446 enabled, disables U-Boot's version and loads ACPI tables generated 447 by QEMU. 448 449config GENERATE_SMBIOS_TABLE 450 bool "Generate an SMBIOS (System Management BIOS) table" 451 default y 452 help 453 The System Management BIOS (SMBIOS) specification addresses how 454 motherboard and system vendors present management information about 455 their products in a standard format by extending the BIOS interface 456 on Intel architecture systems. 457 458 Check http://www.dmtf.org/standards/smbios for details. 459 460endmenu 461 462config MAX_PIRQ_LINKS 463 int 464 default 8 465 help 466 This variable specifies the number of PIRQ interrupt links which are 467 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 468 Some newer chipsets offer more than four links, commonly up to PIRQH. 469 470config IRQ_SLOT_COUNT 471 int 472 default 128 473 help 474 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 475 which in turns forms a table of exact 4KiB. The default value 128 476 should be enough for most boards. If this does not fit your board, 477 change it according to your needs. 478 479config PCIE_ECAM_BASE 480 hex 481 default 0xe0000000 482 help 483 This is the memory-mapped address of PCI configuration space, which 484 is only available through the Enhanced Configuration Access 485 Mechanism (ECAM) with PCI Express. It can be set up almost 486 anywhere. Before it is set up, it is possible to access PCI 487 configuration space through I/O access, but memory access is more 488 convenient. Using this, PCI can be scanned and configured. This 489 should be set to a region that does not conflict with memory 490 assigned to PCI devices - i.e. the memory and prefetch regions, as 491 passed to pci_set_region(). 492 493config PCIE_ECAM_SIZE 494 hex 495 default 0x10000000 496 help 497 This is the size of memory-mapped address of PCI configuration space, 498 which is only available through the Enhanced Configuration Access 499 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, 500 so a default 0x10000000 size covers all of the 256 buses which is the 501 maximum number of PCI buses as defined by the PCI specification. 502 503config I8259_PIC 504 bool 505 default y 506 help 507 Intel 8259 ISA compatible chipset incorporates two 8259 (master and 508 slave) interrupt controllers. Include this to have U-Boot set up 509 the interrupt correctly. 510 511config I8254_TIMER 512 bool 513 default y 514 help 515 Intel 8254 timer contains three counters which have fixed uses. 516 Include this to have U-Boot set up the timer correctly. 517 518config I8042_KEYB 519 default y 520 521config DM_KEYBOARD 522 default y 523 524config SEABIOS 525 bool "Support booting SeaBIOS" 526 help 527 SeaBIOS is an open source implementation of a 16-bit X86 BIOS. 528 It can run in an emulator or natively on X86 hardware with the use 529 of coreboot/U-Boot. By turning on this option, U-Boot prepares 530 all the configuration tables that are necessary to boot SeaBIOS. 531 532 Check http://www.seabios.org/SeaBIOS for details. 533 534source "arch/x86/lib/efi/Kconfig" 535 536endmenu 537