1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Mainboard vendor" 9 default VENDOR_EMULATION 10 11config VENDOR_COREBOOT 12 bool "coreboot" 13 14config VENDOR_EFI 15 bool "efi" 16 17config VENDOR_EMULATION 18 bool "emulation" 19 20config VENDOR_GOOGLE 21 bool "Google" 22 23config VENDOR_INTEL 24 bool "Intel" 25 26endchoice 27 28# board-specific options below 29source "board/coreboot/Kconfig" 30source "board/efi/Kconfig" 31source "board/emulation/Kconfig" 32source "board/google/Kconfig" 33source "board/intel/Kconfig" 34 35# platform-specific options below 36source "arch/x86/cpu/baytrail/Kconfig" 37source "arch/x86/cpu/broadwell/Kconfig" 38source "arch/x86/cpu/coreboot/Kconfig" 39source "arch/x86/cpu/ivybridge/Kconfig" 40source "arch/x86/cpu/qemu/Kconfig" 41source "arch/x86/cpu/quark/Kconfig" 42source "arch/x86/cpu/queensbay/Kconfig" 43 44# architecture-specific options below 45 46config SYS_MALLOC_F_LEN 47 default 0x800 48 49config RAMBASE 50 hex 51 default 0x100000 52 53config XIP_ROM_SIZE 54 hex 55 depends on X86_RESET_VECTOR 56 default ROM_SIZE 57 58config CPU_ADDR_BITS 59 int 60 default 36 61 62config HPET_ADDRESS 63 hex 64 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 65 66config SMM_TSEG 67 bool 68 default n 69 70config SMM_TSEG_SIZE 71 hex 72 73config X86_RESET_VECTOR 74 bool 75 default n 76 77config RESET_SEG_START 78 hex 79 depends on X86_RESET_VECTOR 80 default 0xffff0000 81 82config RESET_SEG_SIZE 83 hex 84 depends on X86_RESET_VECTOR 85 default 0x10000 86 87config RESET_VEC_LOC 88 hex 89 depends on X86_RESET_VECTOR 90 default 0xfffffff0 91 92config SYS_X86_START16 93 hex 94 depends on X86_RESET_VECTOR 95 default 0xfffff800 96 97config BOARD_ROMSIZE_KB_512 98 bool 99config BOARD_ROMSIZE_KB_1024 100 bool 101config BOARD_ROMSIZE_KB_2048 102 bool 103config BOARD_ROMSIZE_KB_4096 104 bool 105config BOARD_ROMSIZE_KB_8192 106 bool 107config BOARD_ROMSIZE_KB_16384 108 bool 109 110choice 111 prompt "ROM chip size" 112 depends on X86_RESET_VECTOR 113 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 114 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 115 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 116 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 117 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 118 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 119 help 120 Select the size of the ROM chip you intend to flash U-Boot on. 121 122 The build system will take care of creating a u-boot.rom file 123 of the matching size. 124 125config UBOOT_ROMSIZE_KB_512 126 bool "512 KB" 127 help 128 Choose this option if you have a 512 KB ROM chip. 129 130config UBOOT_ROMSIZE_KB_1024 131 bool "1024 KB (1 MB)" 132 help 133 Choose this option if you have a 1024 KB (1 MB) ROM chip. 134 135config UBOOT_ROMSIZE_KB_2048 136 bool "2048 KB (2 MB)" 137 help 138 Choose this option if you have a 2048 KB (2 MB) ROM chip. 139 140config UBOOT_ROMSIZE_KB_4096 141 bool "4096 KB (4 MB)" 142 help 143 Choose this option if you have a 4096 KB (4 MB) ROM chip. 144 145config UBOOT_ROMSIZE_KB_8192 146 bool "8192 KB (8 MB)" 147 help 148 Choose this option if you have a 8192 KB (8 MB) ROM chip. 149 150config UBOOT_ROMSIZE_KB_16384 151 bool "16384 KB (16 MB)" 152 help 153 Choose this option if you have a 16384 KB (16 MB) ROM chip. 154 155endchoice 156 157# Map the config names to an integer (KB). 158config UBOOT_ROMSIZE_KB 159 int 160 default 512 if UBOOT_ROMSIZE_KB_512 161 default 1024 if UBOOT_ROMSIZE_KB_1024 162 default 2048 if UBOOT_ROMSIZE_KB_2048 163 default 4096 if UBOOT_ROMSIZE_KB_4096 164 default 8192 if UBOOT_ROMSIZE_KB_8192 165 default 16384 if UBOOT_ROMSIZE_KB_16384 166 167# Map the config names to a hex value (bytes). 168config ROM_SIZE 169 hex 170 default 0x80000 if UBOOT_ROMSIZE_KB_512 171 default 0x100000 if UBOOT_ROMSIZE_KB_1024 172 default 0x200000 if UBOOT_ROMSIZE_KB_2048 173 default 0x400000 if UBOOT_ROMSIZE_KB_4096 174 default 0x800000 if UBOOT_ROMSIZE_KB_8192 175 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 176 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 177 178config HAVE_INTEL_ME 179 bool "Platform requires Intel Management Engine" 180 help 181 Newer higher-end devices have an Intel Management Engine (ME) 182 which is a very large binary blob (typically 1.5MB) which is 183 required for the platform to work. This enforces a particular 184 SPI flash format. You will need to supply the me.bin file in 185 your board directory. 186 187config X86_RAMTEST 188 bool "Perform a simple RAM test after SDRAM initialisation" 189 help 190 If there is something wrong with SDRAM then the platform will 191 often crash within U-Boot or the kernel. This option enables a 192 very simple RAM test that quickly checks whether the SDRAM seems 193 to work correctly. It is not exhaustive but can save time by 194 detecting obvious failures. 195 196config HAVE_FSP 197 bool "Add an Firmware Support Package binary" 198 depends on !EFI 199 help 200 Select this option to add an Firmware Support Package binary to 201 the resulting U-Boot image. It is a binary blob which U-Boot uses 202 to set up SDRAM and other chipset specific initialization. 203 204 Note: Without this binary U-Boot will not be able to set up its 205 SDRAM so will not boot. 206 207config FSP_FILE 208 string "Firmware Support Package binary filename" 209 depends on HAVE_FSP 210 default "fsp.bin" 211 help 212 The filename of the file to use as Firmware Support Package binary 213 in the board directory. 214 215config FSP_ADDR 216 hex "Firmware Support Package binary location" 217 depends on HAVE_FSP 218 default 0xfffc0000 219 help 220 FSP is not Position Independent Code (PIC) and the whole FSP has to 221 be rebased if it is placed at a location which is different from the 222 perferred base address specified during the FSP build. Use Intel's 223 Binary Configuration Tool (BCT) to do the rebase. 224 225 The default base address of 0xfffc0000 indicates that the binary must 226 be located at offset 0xc0000 from the beginning of a 1MB flash device. 227 228config FSP_TEMP_RAM_ADDR 229 hex 230 depends on HAVE_FSP 231 default 0x2000000 232 help 233 Stack top address which is used in fsp_init() after DRAM is ready and 234 CAR is disabled. 235 236config FSP_SYS_MALLOC_F_LEN 237 hex 238 depends on HAVE_FSP 239 default 0x100000 240 help 241 Additional size of malloc() pool before relocation. 242 243config FSP_USE_UPD 244 bool 245 depends on HAVE_FSP 246 default y 247 help 248 Most FSPs use UPD data region for some FSP customization. But there 249 are still some FSPs that might not even have UPD. For such FSPs, 250 override this to n in their platform Kconfig files. 251 252config FSP_BROKEN_HOB 253 bool 254 depends on HAVE_FSP 255 help 256 Indicate some buggy FSPs that does not report memory used by FSP 257 itself as reserved in the resource descriptor HOB. Select this to 258 tell U-Boot to do some additional work to ensure U-Boot relocation 259 do not overwrite the important boot service data which is used by 260 FSP, otherwise the subsequent call to fsp_notify() will fail. 261 262config ENABLE_MRC_CACHE 263 bool "Enable MRC cache" 264 depends on !EFI && !SYS_COREBOOT 265 help 266 Enable this feature to cause MRC data to be cached in NV storage 267 to be used for speeding up boot time on future reboots and/or 268 power cycles. 269 270config HAVE_MRC 271 bool "Add a System Agent binary" 272 depends on !HAVE_FSP 273 help 274 Select this option to add a System Agent binary to 275 the resulting U-Boot image. MRC stands for Memory Reference Code. 276 It is a binary blob which U-Boot uses to set up SDRAM. 277 278 Note: Without this binary U-Boot will not be able to set up its 279 SDRAM so will not boot. 280 281config CACHE_MRC_BIN 282 bool 283 depends on HAVE_MRC 284 default n 285 help 286 Enable caching for the memory reference code binary. This uses an 287 MTRR (memory type range register) to turn on caching for the section 288 of SPI flash that contains the memory reference code. This makes 289 SDRAM init run faster. 290 291config CACHE_MRC_SIZE_KB 292 int 293 depends on HAVE_MRC 294 default 512 295 help 296 Sets the size of the cached area for the memory reference code. 297 This ends at the end of SPI flash (address 0xffffffff) and is 298 measured in KB. Typically this is set to 512, providing for 0.5MB 299 of cached space. 300 301config DCACHE_RAM_BASE 302 hex 303 depends on HAVE_MRC 304 help 305 Sets the base of the data cache area in memory space. This is the 306 start address of the cache-as-RAM (CAR) area and the address varies 307 depending on the CPU. Once CAR is set up, read/write memory becomes 308 available at this address and can be used temporarily until SDRAM 309 is working. 310 311config DCACHE_RAM_SIZE 312 hex 313 depends on HAVE_MRC 314 default 0x40000 315 help 316 Sets the total size of the data cache area in memory space. This 317 sets the size of the cache-as-RAM (CAR) area. Note that much of the 318 CAR space is required by the MRC. The CAR space available to U-Boot 319 is normally at the start and typically extends to 1/4 or 1/2 of the 320 available size. 321 322config DCACHE_RAM_MRC_VAR_SIZE 323 hex 324 depends on HAVE_MRC 325 help 326 This is the amount of CAR (Cache as RAM) reserved for use by the 327 memory reference code. This depends on the implementation of the 328 memory reference code and must be set correctly or the board will 329 not boot. 330 331config HAVE_REFCODE 332 bool "Add a Reference Code binary" 333 help 334 Select this option to add a Reference Code binary to the resulting 335 U-Boot image. This is an Intel binary blob that handles system 336 initialisation, in this case the PCH and System Agent. 337 338 Note: Without this binary (on platforms that need it such as 339 broadwell) U-Boot will be missing some critical setup steps. 340 Various peripherals may fail to work. 341 342config SMP 343 bool "Enable Symmetric Multiprocessing" 344 default n 345 help 346 Enable use of more than one CPU in U-Boot and the Operating System 347 when loaded. Each CPU will be started up and information can be 348 obtained using the 'cpu' command. If this option is disabled, then 349 only one CPU will be enabled regardless of the number of CPUs 350 available. 351 352config MAX_CPUS 353 int "Maximum number of CPUs permitted" 354 depends on SMP 355 default 4 356 help 357 When using multi-CPU chips it is possible for U-Boot to start up 358 more than one CPU. The stack memory used by all of these CPUs is 359 pre-allocated so at present U-Boot wants to know the maximum 360 number of CPUs that may be present. Set this to at least as high 361 as the number of CPUs in your system (it uses about 4KB of RAM for 362 each CPU). 363 364config AP_STACK_SIZE 365 hex 366 depends on SMP 367 default 0x1000 368 help 369 Each additional CPU started by U-Boot requires its own stack. This 370 option sets the stack size used by each CPU and directly affects 371 the memory used by this initialisation process. Typically 4KB is 372 enough space. 373 374config HAVE_VGA_BIOS 375 bool "Add a VGA BIOS image" 376 help 377 Select this option if you have a VGA BIOS image that you would 378 like to add to your ROM. 379 380config VGA_BIOS_FILE 381 string "VGA BIOS image filename" 382 depends on HAVE_VGA_BIOS 383 default "vga.bin" 384 help 385 The filename of the VGA BIOS image in the board directory. 386 387config VGA_BIOS_ADDR 388 hex "VGA BIOS image location" 389 depends on HAVE_VGA_BIOS 390 default 0xfff90000 391 help 392 The location of VGA BIOS image in the SPI flash. For example, base 393 address of 0xfff90000 indicates that the image will be put at offset 394 0x90000 from the beginning of a 1MB flash device. 395 396menu "System tables" 397 depends on !EFI && !SYS_COREBOOT 398 399config GENERATE_PIRQ_TABLE 400 bool "Generate a PIRQ table" 401 default n 402 help 403 Generate a PIRQ routing table for this board. The PIRQ routing table 404 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 405 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 406 It specifies the interrupt router information as well how all the PCI 407 devices' interrupt pins are wired to PIRQs. 408 409config GENERATE_SFI_TABLE 410 bool "Generate a SFI (Simple Firmware Interface) table" 411 help 412 The Simple Firmware Interface (SFI) provides a lightweight method 413 for platform firmware to pass information to the operating system 414 via static tables in memory. Kernel SFI support is required to 415 boot on SFI-only platforms. If you have ACPI tables then these are 416 used instead. 417 418 U-Boot writes this table in write_sfi_table() just before booting 419 the OS. 420 421 For more information, see http://simplefirmware.org 422 423config GENERATE_MP_TABLE 424 bool "Generate an MP (Multi-Processor) table" 425 default n 426 help 427 Generate an MP (Multi-Processor) table for this board. The MP table 428 provides a way for the operating system to support for symmetric 429 multiprocessing as well as symmetric I/O interrupt handling with 430 the local APIC and I/O APIC. 431 432config GENERATE_ACPI_TABLE 433 bool "Generate an ACPI (Advanced Configuration and Power Interface) table" 434 default n 435 help 436 The Advanced Configuration and Power Interface (ACPI) specification 437 provides an open standard for device configuration and management 438 by the operating system. It defines platform-independent interfaces 439 for configuration and power management monitoring. 440 441config QEMU_ACPI_TABLE 442 bool "Load ACPI table from QEMU fw_cfg interface" 443 depends on GENERATE_ACPI_TABLE && QEMU 444 default y 445 help 446 By default, U-Boot generates its own ACPI tables. This option, if 447 enabled, disables U-Boot's version and loads ACPI tables generated 448 by QEMU. 449 450config GENERATE_SMBIOS_TABLE 451 bool "Generate an SMBIOS (System Management BIOS) table" 452 default y 453 help 454 The System Management BIOS (SMBIOS) specification addresses how 455 motherboard and system vendors present management information about 456 their products in a standard format by extending the BIOS interface 457 on Intel architecture systems. 458 459 Check http://www.dmtf.org/standards/smbios for details. 460 461endmenu 462 463config MAX_PIRQ_LINKS 464 int 465 default 8 466 help 467 This variable specifies the number of PIRQ interrupt links which are 468 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 469 Some newer chipsets offer more than four links, commonly up to PIRQH. 470 471config IRQ_SLOT_COUNT 472 int 473 default 128 474 help 475 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 476 which in turns forms a table of exact 4KiB. The default value 128 477 should be enough for most boards. If this does not fit your board, 478 change it according to your needs. 479 480config PCIE_ECAM_BASE 481 hex 482 default 0xe0000000 483 help 484 This is the memory-mapped address of PCI configuration space, which 485 is only available through the Enhanced Configuration Access 486 Mechanism (ECAM) with PCI Express. It can be set up almost 487 anywhere. Before it is set up, it is possible to access PCI 488 configuration space through I/O access, but memory access is more 489 convenient. Using this, PCI can be scanned and configured. This 490 should be set to a region that does not conflict with memory 491 assigned to PCI devices - i.e. the memory and prefetch regions, as 492 passed to pci_set_region(). 493 494config PCIE_ECAM_SIZE 495 hex 496 default 0x10000000 497 help 498 This is the size of memory-mapped address of PCI configuration space, 499 which is only available through the Enhanced Configuration Access 500 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory, 501 so a default 0x10000000 size covers all of the 256 buses which is the 502 maximum number of PCI buses as defined by the PCI specification. 503 504config I8259_PIC 505 bool 506 default y 507 help 508 Intel 8259 ISA compatible chipset incorporates two 8259 (master and 509 slave) interrupt controllers. Include this to have U-Boot set up 510 the interrupt correctly. 511 512config I8254_TIMER 513 bool 514 default y 515 help 516 Intel 8254 timer contains three counters which have fixed uses. 517 Include this to have U-Boot set up the timer correctly. 518 519config I8042_KEYB 520 default y 521 522config DM_KEYBOARD 523 default y 524 525config SEABIOS 526 bool "Support booting SeaBIOS" 527 help 528 SeaBIOS is an open source implementation of a 16-bit X86 BIOS. 529 It can run in an emulator or natively on X86 hardware with the use 530 of coreboot/U-Boot. By turning on this option, U-Boot prepares 531 all the configuration tables that are necessary to boot SeaBIOS. 532 533 Check http://www.seabios.org/SeaBIOS for details. 534 535source "arch/x86/lib/efi/Kconfig" 536 537endmenu 538