xref: /openbmc/u-boot/arch/x86/Kconfig (revision 95de1e2f) 
1menu "x86 architecture"
2	depends on X86
3
4config SYS_ARCH
5	default "x86"
6
7choice
8	prompt "Mainboard vendor"
9	default VENDOR_EMULATION
10
11config VENDOR_COREBOOT
12	bool "coreboot"
13
14config VENDOR_EMULATION
15	bool "emulation"
16
17config VENDOR_GOOGLE
18	bool "Google"
19
20config VENDOR_INTEL
21	bool "Intel"
22
23endchoice
24
25# board-specific options below
26source "board/coreboot/Kconfig"
27source "board/emulation/Kconfig"
28source "board/google/Kconfig"
29source "board/intel/Kconfig"
30
31# platform-specific options below
32source "arch/x86/cpu/baytrail/Kconfig"
33source "arch/x86/cpu/coreboot/Kconfig"
34source "arch/x86/cpu/ivybridge/Kconfig"
35source "arch/x86/cpu/qemu/Kconfig"
36source "arch/x86/cpu/quark/Kconfig"
37source "arch/x86/cpu/queensbay/Kconfig"
38
39# architecture-specific options below
40
41config SYS_MALLOC_F_LEN
42	default 0x800
43
44config RAMBASE
45	hex
46	default 0x100000
47
48config XIP_ROM_SIZE
49	hex
50	depends on X86_RESET_VECTOR
51	default ROM_SIZE
52
53config CPU_ADDR_BITS
54	int
55	default 36
56
57config HPET_ADDRESS
58	hex
59	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
60
61config SMM_TSEG
62	bool
63	default n
64
65config SMM_TSEG_SIZE
66	hex
67
68config X86_RESET_VECTOR
69	bool
70	default n
71
72config RESET_SEG_START
73	hex
74	depends on X86_RESET_VECTOR
75	default 0xffff0000
76
77config RESET_SEG_SIZE
78	hex
79	depends on X86_RESET_VECTOR
80	default 0x10000
81
82config RESET_VEC_LOC
83	hex
84	depends on X86_RESET_VECTOR
85	default 0xfffffff0
86
87config SYS_X86_START16
88	hex
89	depends on X86_RESET_VECTOR
90	default 0xfffff800
91
92config BOARD_ROMSIZE_KB_512
93	bool
94config BOARD_ROMSIZE_KB_1024
95	bool
96config BOARD_ROMSIZE_KB_2048
97	bool
98config BOARD_ROMSIZE_KB_4096
99	bool
100config BOARD_ROMSIZE_KB_8192
101	bool
102config BOARD_ROMSIZE_KB_16384
103	bool
104
105choice
106	prompt "ROM chip size"
107	depends on X86_RESET_VECTOR
108	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
109	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
110	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
111	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
112	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
113	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
114	help
115	  Select the size of the ROM chip you intend to flash U-Boot on.
116
117	  The build system will take care of creating a u-boot.rom file
118	  of the matching size.
119
120config UBOOT_ROMSIZE_KB_512
121	bool "512 KB"
122	help
123	  Choose this option if you have a 512 KB ROM chip.
124
125config UBOOT_ROMSIZE_KB_1024
126	bool "1024 KB (1 MB)"
127	help
128	  Choose this option if you have a 1024 KB (1 MB) ROM chip.
129
130config UBOOT_ROMSIZE_KB_2048
131	bool "2048 KB (2 MB)"
132	help
133	  Choose this option if you have a 2048 KB (2 MB) ROM chip.
134
135config UBOOT_ROMSIZE_KB_4096
136	bool "4096 KB (4 MB)"
137	help
138	  Choose this option if you have a 4096 KB (4 MB) ROM chip.
139
140config UBOOT_ROMSIZE_KB_8192
141	bool "8192 KB (8 MB)"
142	help
143	  Choose this option if you have a 8192 KB (8 MB) ROM chip.
144
145config UBOOT_ROMSIZE_KB_16384
146	bool "16384 KB (16 MB)"
147	help
148	  Choose this option if you have a 16384 KB (16 MB) ROM chip.
149
150endchoice
151
152# Map the config names to an integer (KB).
153config UBOOT_ROMSIZE_KB
154	int
155	default 512 if UBOOT_ROMSIZE_KB_512
156	default 1024 if UBOOT_ROMSIZE_KB_1024
157	default 2048 if UBOOT_ROMSIZE_KB_2048
158	default 4096 if UBOOT_ROMSIZE_KB_4096
159	default 8192 if UBOOT_ROMSIZE_KB_8192
160	default 16384 if UBOOT_ROMSIZE_KB_16384
161
162# Map the config names to a hex value (bytes).
163config ROM_SIZE
164	hex
165	default 0x80000 if UBOOT_ROMSIZE_KB_512
166	default 0x100000 if UBOOT_ROMSIZE_KB_1024
167	default 0x200000 if UBOOT_ROMSIZE_KB_2048
168	default 0x400000 if UBOOT_ROMSIZE_KB_4096
169	default 0x800000 if UBOOT_ROMSIZE_KB_8192
170	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
171	default 0x1000000 if UBOOT_ROMSIZE_KB_16384
172
173config HAVE_INTEL_ME
174	bool "Platform requires Intel Management Engine"
175	help
176	  Newer higher-end devices have an Intel Management Engine (ME)
177	  which is a very large binary blob (typically 1.5MB) which is
178	  required for the platform to work. This enforces a particular
179	  SPI flash format. You will need to supply the me.bin file in
180	  your board directory.
181
182config X86_RAMTEST
183	bool "Perform a simple RAM test after SDRAM initialisation"
184	help
185	  If there is something wrong with SDRAM then the platform will
186	  often crash within U-Boot or the kernel. This option enables a
187	  very simple RAM test that quickly checks whether the SDRAM seems
188	  to work correctly. It is not exhaustive but can save time by
189	  detecting obvious failures.
190
191config HAVE_FSP
192	bool "Add an Firmware Support Package binary"
193	help
194	  Select this option to add an Firmware Support Package binary to
195	  the resulting U-Boot image. It is a binary blob which U-Boot uses
196	  to set up SDRAM and other chipset specific initialization.
197
198	  Note: Without this binary U-Boot will not be able to set up its
199	  SDRAM so will not boot.
200
201config FSP_FILE
202	string "Firmware Support Package binary filename"
203	depends on HAVE_FSP
204	default "fsp.bin"
205	help
206	  The filename of the file to use as Firmware Support Package binary
207	  in the board directory.
208
209config FSP_ADDR
210	hex "Firmware Support Package binary location"
211	depends on HAVE_FSP
212	default 0xfffc0000
213	help
214	  FSP is not Position Independent Code (PIC) and the whole FSP has to
215	  be rebased if it is placed at a location which is different from the
216	  perferred base address specified during the FSP build. Use Intel's
217	  Binary Configuration Tool (BCT) to do the rebase.
218
219	  The default base address of 0xfffc0000 indicates that the binary must
220	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
221
222config FSP_TEMP_RAM_ADDR
223	hex
224	depends on HAVE_FSP
225	default 0x2000000
226	help
227	  Stack top address which is used in FspInit after DRAM is ready and
228	  CAR is disabled.
229
230config SMP
231	bool "Enable Symmetric Multiprocessing"
232	default n
233	help
234	  Enable use of more than one CPU in U-Boot and the Operating System
235	  when loaded. Each CPU will be started up and information can be
236	  obtained using the 'cpu' command. If this option is disabled, then
237	  only one CPU will be enabled regardless of the number of CPUs
238	  available.
239
240config MAX_CPUS
241	int "Maximum number of CPUs permitted"
242	depends on SMP
243	default 4
244	help
245	  When using multi-CPU chips it is possible for U-Boot to start up
246	  more than one CPU. The stack memory used by all of these CPUs is
247	  pre-allocated so at present U-Boot wants to know the maximum
248	  number of CPUs that may be present. Set this to at least as high
249	  as the number of CPUs in your system (it uses about 4KB of RAM for
250	  each CPU).
251
252config AP_STACK_SIZE
253	hex
254	depends on SMP
255	default 0x1000
256	help
257	  Each additional CPU started by U-Boot requires its own stack. This
258	  option sets the stack size used by each CPU and directly affects
259	  the memory used by this initialisation process. Typically 4KB is
260	  enough space.
261
262config TSC_CALIBRATION_BYPASS
263	bool "Bypass Time-Stamp Counter (TSC) calibration"
264	default n
265	help
266	  By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
267	  running frequency via Model-Specific Register (MSR) and Programmable
268	  Interval Timer (PIT). If the calibration does not work on your board,
269	  select this option and provide a hardcoded TSC running frequency with
270	  CONFIG_TSC_FREQ_IN_MHZ below.
271
272	  Normally this option should be turned on in a simulation environment
273	  like qemu.
274
275config TSC_FREQ_IN_MHZ
276	int "Time-Stamp Counter (TSC) running frequency in MHz"
277	depends on TSC_CALIBRATION_BYPASS
278	default 1000
279	help
280	  The running frequency in MHz of Time-Stamp Counter (TSC).
281
282config HAVE_VGA_BIOS
283	bool "Add a VGA BIOS image"
284	help
285	  Select this option if you have a VGA BIOS image that you would
286	  like to add to your ROM.
287
288config VGA_BIOS_FILE
289	string "VGA BIOS image filename"
290	depends on HAVE_VGA_BIOS
291	default "vga.bin"
292	help
293	  The filename of the VGA BIOS image in the board directory.
294
295config VGA_BIOS_ADDR
296	hex "VGA BIOS image location"
297	depends on HAVE_VGA_BIOS
298	default 0xfff90000
299	help
300	  The location of VGA BIOS image in the SPI flash. For example, base
301	  address of 0xfff90000 indicates that the image will be put at offset
302	  0x90000 from the beginning of a 1MB flash device.
303
304menu "System tables"
305
306config GENERATE_PIRQ_TABLE
307	bool "Generate a PIRQ table"
308	default n
309	help
310	  Generate a PIRQ routing table for this board. The PIRQ routing table
311	  is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
312	  at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
313	  It specifies the interrupt router information as well how all the PCI
314	  devices' interrupt pins are wired to PIRQs.
315
316config GENERATE_SFI_TABLE
317	bool "Generate a SFI (Simple Firmware Interface) table"
318	help
319	  The Simple Firmware Interface (SFI) provides a lightweight method
320	  for platform firmware to pass information to the operating system
321	  via static tables in memory.  Kernel SFI support is required to
322	  boot on SFI-only platforms.  If you have ACPI tables then these are
323	  used instead.
324
325	  U-Boot writes this table in write_sfi_table() just before booting
326	  the OS.
327
328	  For more information, see http://simplefirmware.org
329
330config GENERATE_MP_TABLE
331	bool "Generate an MP (Multi-Processor) table"
332	default n
333	help
334	  Generate an MP (Multi-Processor) table for this board. The MP table
335	  provides a way for the operating system to support for symmetric
336	  multiprocessing as well as symmetric I/O interrupt handling with
337	  the local APIC and I/O APIC.
338
339endmenu
340
341config MAX_PIRQ_LINKS
342	int
343	default 8
344	help
345	  This variable specifies the number of PIRQ interrupt links which are
346	  routable. On most older chipsets, this is 4, PIRQA through PIRQD.
347	  Some newer chipsets offer more than four links, commonly up to PIRQH.
348
349config IRQ_SLOT_COUNT
350	int
351	default 128
352	help
353	  U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
354	  which in turns forms a table of exact 4KiB. The default value 128
355	  should be enough for most boards. If this does not fit your board,
356	  change it according to your needs.
357
358config PCIE_ECAM_BASE
359	hex
360	default 0xe0000000
361	help
362	  This is the memory-mapped address of PCI configuration space, which
363	  is only available through the Enhanced Configuration Access
364	  Mechanism (ECAM) with PCI Express. It can be set up almost
365	  anywhere. Before it is set up, it is possible to access PCI
366	  configuration space through I/O access, but memory access is more
367	  convenient. Using this, PCI can be scanned and configured. This
368	  should be set to a region that does not conflict with memory
369	  assigned to PCI devices - i.e. the memory and prefetch regions, as
370	  passed to pci_set_region().
371
372config PCIE_ECAM_SIZE
373	hex
374	default 0x10000000
375	help
376	  This is the size of memory-mapped address of PCI configuration space,
377	  which is only available through the Enhanced Configuration Access
378	  Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
379	  so a default 0x10000000 size covers all of the 256 buses which is the
380	  maximum number of PCI buses as defined by the PCI specification.
381
382endmenu
383