xref: /openbmc/u-boot/arch/x86/Kconfig (revision 864896be)
1menu "x86 architecture"
2	depends on X86
3
4config SYS_ARCH
5	default "x86"
6
7choice
8	prompt "Run U-Boot in 32/64-bit mode"
9	default X86_RUN_32BIT
10	help
11	  U-Boot can be built as a 32-bit binary which runs in 32-bit mode
12	  even on 64-bit machines. In this case SPL is not used, and U-Boot
13	  runs directly from the reset vector (via 16-bit start-up).
14
15	  Alternatively it can be run as a 64-bit binary, thus requiring a
16	  64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
17	  start-up) then jumps to U-Boot in 64-bit mode.
18
19	  For now, 32-bit mode is recommended, as 64-bit is still
20	  experimental and is missing a lot of features.
21
22config X86_RUN_32BIT
23	bool "32-bit"
24	help
25	  Build U-Boot as a 32-bit binary with no SPL. This is the currently
26	  supported normal setup. U-Boot will stay in 32-bit mode even on
27	  64-bit machines. When booting a 64-bit kernel, U-Boot will switch
28	  to 64-bit just before starting the kernel. Only the bottom 4GB of
29	  memory can be accessed through normal means, although
30	  arch_phys_memset() can be used for basic access to other memory.
31
32config X86_RUN_64BIT
33	bool "64-bit"
34	select X86_64
35	select SUPPORT_SPL
36	select SPL
37	select SPL_SEPARATE_BSS
38	help
39	  Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
40	  experimental and many features are missing. U-Boot SPL starts up,
41	  runs through the 16-bit and 32-bit init, then switches to 64-bit
42	  mode and jumps to U-Boot proper.
43
44endchoice
45
46config X86_64
47	bool
48
49config SPL_X86_64
50	bool
51	depends on SPL
52
53choice
54	prompt "Mainboard vendor"
55	default VENDOR_EMULATION
56
57config VENDOR_ADVANTECH
58	bool "advantech"
59
60config VENDOR_CONGATEC
61	bool "congatec"
62
63config VENDOR_COREBOOT
64	bool "coreboot"
65
66config VENDOR_DFI
67	bool "dfi"
68
69config VENDOR_EFI
70	bool "efi"
71
72config VENDOR_EMULATION
73	bool "emulation"
74
75config VENDOR_GOOGLE
76	bool "Google"
77
78config VENDOR_INTEL
79	bool "Intel"
80
81endchoice
82
83# subarchitectures-specific options below
84config INTEL_MID
85	bool "Intel MID platform support"
86	select REGMAP
87	select SYSCON
88	help
89	  Select to build a U-Boot capable of supporting Intel MID
90	  (Mobile Internet Device) platform systems which do not have
91	  the PCI legacy interfaces.
92
93	  If you are building for a PC class system say N here.
94
95	  Intel MID platforms are based on an Intel processor and
96	  chipset which consume less power than most of the x86
97	  derivatives.
98
99# board-specific options below
100source "board/advantech/Kconfig"
101source "board/congatec/Kconfig"
102source "board/coreboot/Kconfig"
103source "board/dfi/Kconfig"
104source "board/efi/Kconfig"
105source "board/emulation/Kconfig"
106source "board/google/Kconfig"
107source "board/intel/Kconfig"
108
109# platform-specific options below
110source "arch/x86/cpu/baytrail/Kconfig"
111source "arch/x86/cpu/broadwell/Kconfig"
112source "arch/x86/cpu/coreboot/Kconfig"
113source "arch/x86/cpu/ivybridge/Kconfig"
114source "arch/x86/cpu/qemu/Kconfig"
115source "arch/x86/cpu/quark/Kconfig"
116source "arch/x86/cpu/queensbay/Kconfig"
117
118# architecture-specific options below
119
120config AHCI
121	default y
122
123config SYS_MALLOC_F_LEN
124	default 0x800
125
126config RAMBASE
127	hex
128	default 0x100000
129
130config XIP_ROM_SIZE
131	hex
132	depends on X86_RESET_VECTOR
133	default ROM_SIZE
134
135config CPU_ADDR_BITS
136	int
137	default 36
138
139config HPET_ADDRESS
140	hex
141	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
142
143config SMM_TSEG
144	bool
145	default n
146
147config SMM_TSEG_SIZE
148	hex
149
150config X86_RESET_VECTOR
151	bool
152	default n
153
154# The following options control where the 16-bit and 32-bit init lies
155# If SPL is enabled then it normally holds this init code, and U-Boot proper
156# is normally a 64-bit build.
157#
158# The 16-bit init refers to the reset vector and the small amount of code to
159# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
160# or missing altogether if U-Boot is started from EFI or coreboot.
161#
162# The 32-bit init refers to processor init, running binary blobs including
163# FSP, setting up interrupts and anything else that needs to be done in
164# 32-bit code. It is normally in the same place as 16-bit init if that is
165# enabled (i.e. they are both in SPL, or both in U-Boot proper).
166config X86_16BIT_INIT
167	bool
168	depends on X86_RESET_VECTOR
169	default y if X86_RESET_VECTOR && !SPL
170	help
171	  This is enabled when 16-bit init is in U-Boot proper
172
173config SPL_X86_16BIT_INIT
174	bool
175	depends on X86_RESET_VECTOR
176	default y if X86_RESET_VECTOR && SPL
177	help
178	  This is enabled when 16-bit init is in SPL
179
180config X86_32BIT_INIT
181	bool
182	depends on X86_RESET_VECTOR
183	default y if X86_RESET_VECTOR && !SPL
184	help
185	  This is enabled when 32-bit init is in U-Boot proper
186
187config SPL_X86_32BIT_INIT
188	bool
189	depends on X86_RESET_VECTOR
190	default y if X86_RESET_VECTOR && SPL
191	help
192	  This is enabled when 32-bit init is in SPL
193
194config RESET_SEG_START
195	hex
196	depends on X86_RESET_VECTOR
197	default 0xffff0000
198
199config RESET_SEG_SIZE
200	hex
201	depends on X86_RESET_VECTOR
202	default 0x10000
203
204config RESET_VEC_LOC
205	hex
206	depends on X86_RESET_VECTOR
207	default 0xfffffff0
208
209config SYS_X86_START16
210	hex
211	depends on X86_RESET_VECTOR
212	default 0xfffff800
213
214config X86_LOAD_FROM_32_BIT
215	bool "Boot from a 32-bit program"
216	help
217	  Define this to boot U-Boot from a 32-bit program which sets
218	  the GDT differently. This can be used to boot directly from
219	  any stage of coreboot, for example, bypassing the normal
220	  payload-loading feature.
221
222config BOARD_ROMSIZE_KB_512
223	bool
224config BOARD_ROMSIZE_KB_1024
225	bool
226config BOARD_ROMSIZE_KB_2048
227	bool
228config BOARD_ROMSIZE_KB_4096
229	bool
230config BOARD_ROMSIZE_KB_8192
231	bool
232config BOARD_ROMSIZE_KB_16384
233	bool
234
235choice
236	prompt "ROM chip size"
237	depends on X86_RESET_VECTOR
238	default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
239	default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
240	default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
241	default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
242	default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
243	default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
244	help
245	  Select the size of the ROM chip you intend to flash U-Boot on.
246
247	  The build system will take care of creating a u-boot.rom file
248	  of the matching size.
249
250config UBOOT_ROMSIZE_KB_512
251	bool "512 KB"
252	help
253	  Choose this option if you have a 512 KB ROM chip.
254
255config UBOOT_ROMSIZE_KB_1024
256	bool "1024 KB (1 MB)"
257	help
258	  Choose this option if you have a 1024 KB (1 MB) ROM chip.
259
260config UBOOT_ROMSIZE_KB_2048
261	bool "2048 KB (2 MB)"
262	help
263	  Choose this option if you have a 2048 KB (2 MB) ROM chip.
264
265config UBOOT_ROMSIZE_KB_4096
266	bool "4096 KB (4 MB)"
267	help
268	  Choose this option if you have a 4096 KB (4 MB) ROM chip.
269
270config UBOOT_ROMSIZE_KB_8192
271	bool "8192 KB (8 MB)"
272	help
273	  Choose this option if you have a 8192 KB (8 MB) ROM chip.
274
275config UBOOT_ROMSIZE_KB_16384
276	bool "16384 KB (16 MB)"
277	help
278	  Choose this option if you have a 16384 KB (16 MB) ROM chip.
279
280endchoice
281
282# Map the config names to an integer (KB).
283config UBOOT_ROMSIZE_KB
284	int
285	default 512 if UBOOT_ROMSIZE_KB_512
286	default 1024 if UBOOT_ROMSIZE_KB_1024
287	default 2048 if UBOOT_ROMSIZE_KB_2048
288	default 4096 if UBOOT_ROMSIZE_KB_4096
289	default 8192 if UBOOT_ROMSIZE_KB_8192
290	default 16384 if UBOOT_ROMSIZE_KB_16384
291
292# Map the config names to a hex value (bytes).
293config ROM_SIZE
294	hex
295	default 0x80000 if UBOOT_ROMSIZE_KB_512
296	default 0x100000 if UBOOT_ROMSIZE_KB_1024
297	default 0x200000 if UBOOT_ROMSIZE_KB_2048
298	default 0x400000 if UBOOT_ROMSIZE_KB_4096
299	default 0x800000 if UBOOT_ROMSIZE_KB_8192
300	default 0xc00000 if UBOOT_ROMSIZE_KB_12288
301	default 0x1000000 if UBOOT_ROMSIZE_KB_16384
302
303config HAVE_INTEL_ME
304	bool "Platform requires Intel Management Engine"
305	help
306	  Newer higher-end devices have an Intel Management Engine (ME)
307	  which is a very large binary blob (typically 1.5MB) which is
308	  required for the platform to work. This enforces a particular
309	  SPI flash format. You will need to supply the me.bin file in
310	  your board directory.
311
312config X86_RAMTEST
313	bool "Perform a simple RAM test after SDRAM initialisation"
314	help
315	  If there is something wrong with SDRAM then the platform will
316	  often crash within U-Boot or the kernel. This option enables a
317	  very simple RAM test that quickly checks whether the SDRAM seems
318	  to work correctly. It is not exhaustive but can save time by
319	  detecting obvious failures.
320
321config FLASH_DESCRIPTOR_FILE
322	string "Flash descriptor binary filename"
323	depends on HAVE_INTEL_ME
324	default "descriptor.bin"
325	help
326	  The filename of the file to use as flash descriptor in the
327	  board directory.
328
329config INTEL_ME_FILE
330	string "Intel Management Engine binary filename"
331	depends on HAVE_INTEL_ME
332	default "me.bin"
333	help
334	  The filename of the file to use as Intel Management Engine in the
335	  board directory.
336
337config HAVE_FSP
338	bool "Add an Firmware Support Package binary"
339	depends on !EFI
340	help
341	  Select this option to add an Firmware Support Package binary to
342	  the resulting U-Boot image. It is a binary blob which U-Boot uses
343	  to set up SDRAM and other chipset specific initialization.
344
345	  Note: Without this binary U-Boot will not be able to set up its
346	  SDRAM so will not boot.
347
348config FSP_FILE
349	string "Firmware Support Package binary filename"
350	depends on HAVE_FSP
351	default "fsp.bin"
352	help
353	  The filename of the file to use as Firmware Support Package binary
354	  in the board directory.
355
356config FSP_ADDR
357	hex "Firmware Support Package binary location"
358	depends on HAVE_FSP
359	default 0xfffc0000
360	help
361	  FSP is not Position Independent Code (PIC) and the whole FSP has to
362	  be rebased if it is placed at a location which is different from the
363	  perferred base address specified during the FSP build. Use Intel's
364	  Binary Configuration Tool (BCT) to do the rebase.
365
366	  The default base address of 0xfffc0000 indicates that the binary must
367	  be located at offset 0xc0000 from the beginning of a 1MB flash device.
368
369config FSP_TEMP_RAM_ADDR
370	hex
371	depends on HAVE_FSP
372	default 0x2000000
373	help
374	  Stack top address which is used in fsp_init() after DRAM is ready and
375	  CAR is disabled.
376
377config FSP_SYS_MALLOC_F_LEN
378	hex
379	depends on HAVE_FSP
380	default 0x100000
381	help
382	  Additional size of malloc() pool before relocation.
383
384config FSP_USE_UPD
385	bool
386	depends on HAVE_FSP
387	default y
388	help
389	  Most FSPs use UPD data region for some FSP customization. But there
390	  are still some FSPs that might not even have UPD. For such FSPs,
391	  override this to n in their platform Kconfig files.
392
393config FSP_BROKEN_HOB
394	bool
395	depends on HAVE_FSP
396	help
397	  Indicate some buggy FSPs that does not report memory used by FSP
398	  itself as reserved in the resource descriptor HOB. Select this to
399	  tell U-Boot to do some additional work to ensure U-Boot relocation
400	  do not overwrite the important boot service data which is used by
401	  FSP, otherwise the subsequent call to fsp_notify() will fail.
402
403config ENABLE_MRC_CACHE
404	bool "Enable MRC cache"
405	depends on !EFI && !SYS_COREBOOT
406	help
407	  Enable this feature to cause MRC data to be cached in NV storage
408	  to be used for speeding up boot time on future reboots and/or
409	  power cycles.
410
411	  For platforms that use Intel FSP for the memory initialization,
412	  please check FSP output HOB via U-Boot command 'fsp hob' to see
413	  if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
414	  If such GUID does not exist, MRC cache is not avaiable on such
415	  platform (eg: Intel Queensbay), which means selecting this option
416	  here does not make any difference.
417
418config HAVE_MRC
419	bool "Add a System Agent binary"
420	depends on !HAVE_FSP
421	help
422	  Select this option to add a System Agent binary to
423	  the resulting U-Boot image. MRC stands for Memory Reference Code.
424	  It is a binary blob which U-Boot uses to set up SDRAM.
425
426	  Note: Without this binary U-Boot will not be able to set up its
427	  SDRAM so will not boot.
428
429config CACHE_MRC_BIN
430	bool
431	depends on HAVE_MRC
432	default n
433	help
434	  Enable caching for the memory reference code binary. This uses an
435	  MTRR (memory type range register) to turn on caching for the section
436	  of SPI flash that contains the memory reference code. This makes
437	  SDRAM init run faster.
438
439config CACHE_MRC_SIZE_KB
440	int
441	depends on HAVE_MRC
442	default 512
443	help
444	  Sets the size of the cached area for the memory reference code.
445	  This ends at the end of SPI flash (address 0xffffffff) and is
446	  measured in KB. Typically this is set to 512, providing for 0.5MB
447	  of cached space.
448
449config DCACHE_RAM_BASE
450	hex
451	depends on HAVE_MRC
452	help
453	  Sets the base of the data cache area in memory space. This is the
454	  start address of the cache-as-RAM (CAR) area and the address varies
455	  depending on the CPU. Once CAR is set up, read/write memory becomes
456	  available at this address and can be used temporarily until SDRAM
457	  is working.
458
459config DCACHE_RAM_SIZE
460	hex
461	depends on HAVE_MRC
462	default 0x40000
463	help
464	  Sets the total size of the data cache area in memory space. This
465	  sets the size of the cache-as-RAM (CAR) area. Note that much of the
466	  CAR space is required by the MRC. The CAR space available to U-Boot
467	  is normally at the start and typically extends to 1/4 or 1/2 of the
468	  available size.
469
470config DCACHE_RAM_MRC_VAR_SIZE
471	hex
472	depends on HAVE_MRC
473	help
474	  This is the amount of CAR (Cache as RAM) reserved for use by the
475	  memory reference code. This depends on the implementation of the
476	  memory reference code and must be set correctly or the board will
477	  not boot.
478
479config HAVE_REFCODE
480        bool "Add a Reference Code binary"
481        help
482          Select this option to add a Reference Code binary to the resulting
483          U-Boot image. This is an Intel binary blob that handles system
484          initialisation, in this case the PCH and System Agent.
485
486          Note: Without this binary (on platforms that need it such as
487          broadwell) U-Boot will be missing some critical setup steps.
488          Various peripherals may fail to work.
489
490config SMP
491	bool "Enable Symmetric Multiprocessing"
492	default n
493	help
494	  Enable use of more than one CPU in U-Boot and the Operating System
495	  when loaded. Each CPU will be started up and information can be
496	  obtained using the 'cpu' command. If this option is disabled, then
497	  only one CPU will be enabled regardless of the number of CPUs
498	  available.
499
500config MAX_CPUS
501	int "Maximum number of CPUs permitted"
502	depends on SMP
503	default 4
504	help
505	  When using multi-CPU chips it is possible for U-Boot to start up
506	  more than one CPU. The stack memory used by all of these CPUs is
507	  pre-allocated so at present U-Boot wants to know the maximum
508	  number of CPUs that may be present. Set this to at least as high
509	  as the number of CPUs in your system (it uses about 4KB of RAM for
510	  each CPU).
511
512config AP_STACK_SIZE
513	hex
514	depends on SMP
515	default 0x1000
516	help
517	  Each additional CPU started by U-Boot requires its own stack. This
518	  option sets the stack size used by each CPU and directly affects
519	  the memory used by this initialisation process. Typically 4KB is
520	  enough space.
521
522config HAVE_VGA_BIOS
523	bool "Add a VGA BIOS image"
524	help
525	  Select this option if you have a VGA BIOS image that you would
526	  like to add to your ROM.
527
528config VGA_BIOS_FILE
529	string "VGA BIOS image filename"
530	depends on HAVE_VGA_BIOS
531	default "vga.bin"
532	help
533	  The filename of the VGA BIOS image in the board directory.
534
535config VGA_BIOS_ADDR
536	hex "VGA BIOS image location"
537	depends on HAVE_VGA_BIOS
538	default 0xfff90000
539	help
540	  The location of VGA BIOS image in the SPI flash. For example, base
541	  address of 0xfff90000 indicates that the image will be put at offset
542	  0x90000 from the beginning of a 1MB flash device.
543
544menu "System tables"
545	depends on !EFI && !SYS_COREBOOT
546
547config GENERATE_PIRQ_TABLE
548	bool "Generate a PIRQ table"
549	default n
550	help
551	  Generate a PIRQ routing table for this board. The PIRQ routing table
552	  is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
553	  at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
554	  It specifies the interrupt router information as well how all the PCI
555	  devices' interrupt pins are wired to PIRQs.
556
557config GENERATE_SFI_TABLE
558	bool "Generate a SFI (Simple Firmware Interface) table"
559	help
560	  The Simple Firmware Interface (SFI) provides a lightweight method
561	  for platform firmware to pass information to the operating system
562	  via static tables in memory.  Kernel SFI support is required to
563	  boot on SFI-only platforms.  If you have ACPI tables then these are
564	  used instead.
565
566	  U-Boot writes this table in write_sfi_table() just before booting
567	  the OS.
568
569	  For more information, see http://simplefirmware.org
570
571config GENERATE_MP_TABLE
572	bool "Generate an MP (Multi-Processor) table"
573	default n
574	help
575	  Generate an MP (Multi-Processor) table for this board. The MP table
576	  provides a way for the operating system to support for symmetric
577	  multiprocessing as well as symmetric I/O interrupt handling with
578	  the local APIC and I/O APIC.
579
580config GENERATE_ACPI_TABLE
581	bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
582	default n
583	select QFW if QEMU
584	help
585	  The Advanced Configuration and Power Interface (ACPI) specification
586	  provides an open standard for device configuration and management
587	  by the operating system. It defines platform-independent interfaces
588	  for configuration and power management monitoring.
589
590endmenu
591
592config MAX_PIRQ_LINKS
593	int
594	default 8
595	help
596	  This variable specifies the number of PIRQ interrupt links which are
597	  routable. On most older chipsets, this is 4, PIRQA through PIRQD.
598	  Some newer chipsets offer more than four links, commonly up to PIRQH.
599
600config IRQ_SLOT_COUNT
601	int
602	default 128
603	help
604	  U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
605	  which in turns forms a table of exact 4KiB. The default value 128
606	  should be enough for most boards. If this does not fit your board,
607	  change it according to your needs.
608
609config PCIE_ECAM_BASE
610	hex
611	default 0xe0000000
612	help
613	  This is the memory-mapped address of PCI configuration space, which
614	  is only available through the Enhanced Configuration Access
615	  Mechanism (ECAM) with PCI Express. It can be set up almost
616	  anywhere. Before it is set up, it is possible to access PCI
617	  configuration space through I/O access, but memory access is more
618	  convenient. Using this, PCI can be scanned and configured. This
619	  should be set to a region that does not conflict with memory
620	  assigned to PCI devices - i.e. the memory and prefetch regions, as
621	  passed to pci_set_region().
622
623config PCIE_ECAM_SIZE
624	hex
625	default 0x10000000
626	help
627	  This is the size of memory-mapped address of PCI configuration space,
628	  which is only available through the Enhanced Configuration Access
629	  Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
630	  so a default 0x10000000 size covers all of the 256 buses which is the
631	  maximum number of PCI buses as defined by the PCI specification.
632
633config I8259_PIC
634	bool
635	default y
636	help
637	  Intel 8259 ISA compatible chipset incorporates two 8259 (master and
638	  slave) interrupt controllers. Include this to have U-Boot set up
639	  the interrupt correctly.
640
641config I8254_TIMER
642	bool
643	default y
644	help
645	  Intel 8254 timer contains three counters which have fixed uses.
646	  Include this to have U-Boot set up the timer correctly.
647
648config SEABIOS
649	bool "Support booting SeaBIOS"
650	help
651	  SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
652	  It can run in an emulator or natively on X86 hardware with the use
653	  of coreboot/U-Boot. By turning on this option, U-Boot prepares
654	  all the configuration tables that are necessary to boot SeaBIOS.
655
656	  Check http://www.seabios.org/SeaBIOS for details.
657
658config HIGH_TABLE_SIZE
659	hex "Size of configuration tables which reside in high memory"
660	default 0x10000
661	depends on SEABIOS
662	help
663	  SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
664	  configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
665	  puts a copy of configuration tables in high memory region which
666	  is reserved on the stack before relocation. The region size is
667	  determined by this option.
668
669	  Increse it if the default size does not fit the board's needs.
670	  This is most likely due to a large ACPI DSDT table is used.
671
672source "arch/x86/lib/efi/Kconfig"
673
674endmenu
675