1menu "x86 architecture" 2 depends on X86 3 4config SYS_ARCH 5 default "x86" 6 7choice 8 prompt "Mainboard vendor" 9 default VENDOR_EMULATION 10 11config VENDOR_COREBOOT 12 bool "coreboot" 13 14config VENDOR_EMULATION 15 bool "emulation" 16 17config VENDOR_GOOGLE 18 bool "Google" 19 20config VENDOR_INTEL 21 bool "Intel" 22 23endchoice 24 25# board-specific options below 26source "board/coreboot/Kconfig" 27source "board/emulation/Kconfig" 28source "board/google/Kconfig" 29source "board/intel/Kconfig" 30 31# platform-specific options below 32source "arch/x86/cpu/baytrail/Kconfig" 33source "arch/x86/cpu/coreboot/Kconfig" 34source "arch/x86/cpu/ivybridge/Kconfig" 35source "arch/x86/cpu/qemu/Kconfig" 36source "arch/x86/cpu/quark/Kconfig" 37source "arch/x86/cpu/queensbay/Kconfig" 38 39# architecture-specific options below 40 41config SYS_MALLOC_F_LEN 42 default 0x800 43 44config RAMBASE 45 hex 46 default 0x100000 47 48config XIP_ROM_SIZE 49 hex 50 depends on X86_RESET_VECTOR 51 default ROM_SIZE 52 53config CPU_ADDR_BITS 54 int 55 default 36 56 57config HPET_ADDRESS 58 hex 59 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE 60 61config SMM_TSEG 62 bool 63 default n 64 65config SMM_TSEG_SIZE 66 hex 67 68config X86_RESET_VECTOR 69 bool 70 default n 71 72config SYS_X86_START16 73 hex 74 depends on X86_RESET_VECTOR 75 default 0xfffff800 76 77config BOARD_ROMSIZE_KB_512 78 bool 79config BOARD_ROMSIZE_KB_1024 80 bool 81config BOARD_ROMSIZE_KB_2048 82 bool 83config BOARD_ROMSIZE_KB_4096 84 bool 85config BOARD_ROMSIZE_KB_8192 86 bool 87config BOARD_ROMSIZE_KB_16384 88 bool 89 90choice 91 prompt "ROM chip size" 92 depends on X86_RESET_VECTOR 93 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512 94 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024 95 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048 96 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096 97 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192 98 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384 99 help 100 Select the size of the ROM chip you intend to flash U-Boot on. 101 102 The build system will take care of creating a u-boot.rom file 103 of the matching size. 104 105config UBOOT_ROMSIZE_KB_512 106 bool "512 KB" 107 help 108 Choose this option if you have a 512 KB ROM chip. 109 110config UBOOT_ROMSIZE_KB_1024 111 bool "1024 KB (1 MB)" 112 help 113 Choose this option if you have a 1024 KB (1 MB) ROM chip. 114 115config UBOOT_ROMSIZE_KB_2048 116 bool "2048 KB (2 MB)" 117 help 118 Choose this option if you have a 2048 KB (2 MB) ROM chip. 119 120config UBOOT_ROMSIZE_KB_4096 121 bool "4096 KB (4 MB)" 122 help 123 Choose this option if you have a 4096 KB (4 MB) ROM chip. 124 125config UBOOT_ROMSIZE_KB_8192 126 bool "8192 KB (8 MB)" 127 help 128 Choose this option if you have a 8192 KB (8 MB) ROM chip. 129 130config UBOOT_ROMSIZE_KB_16384 131 bool "16384 KB (16 MB)" 132 help 133 Choose this option if you have a 16384 KB (16 MB) ROM chip. 134 135endchoice 136 137# Map the config names to an integer (KB). 138config UBOOT_ROMSIZE_KB 139 int 140 default 512 if UBOOT_ROMSIZE_KB_512 141 default 1024 if UBOOT_ROMSIZE_KB_1024 142 default 2048 if UBOOT_ROMSIZE_KB_2048 143 default 4096 if UBOOT_ROMSIZE_KB_4096 144 default 8192 if UBOOT_ROMSIZE_KB_8192 145 default 16384 if UBOOT_ROMSIZE_KB_16384 146 147# Map the config names to a hex value (bytes). 148config ROM_SIZE 149 hex 150 default 0x80000 if UBOOT_ROMSIZE_KB_512 151 default 0x100000 if UBOOT_ROMSIZE_KB_1024 152 default 0x200000 if UBOOT_ROMSIZE_KB_2048 153 default 0x400000 if UBOOT_ROMSIZE_KB_4096 154 default 0x800000 if UBOOT_ROMSIZE_KB_8192 155 default 0xc00000 if UBOOT_ROMSIZE_KB_12288 156 default 0x1000000 if UBOOT_ROMSIZE_KB_16384 157 158config HAVE_INTEL_ME 159 bool "Platform requires Intel Management Engine" 160 help 161 Newer higher-end devices have an Intel Management Engine (ME) 162 which is a very large binary blob (typically 1.5MB) which is 163 required for the platform to work. This enforces a particular 164 SPI flash format. You will need to supply the me.bin file in 165 your board directory. 166 167config X86_RAMTEST 168 bool "Perform a simple RAM test after SDRAM initialisation" 169 help 170 If there is something wrong with SDRAM then the platform will 171 often crash within U-Boot or the kernel. This option enables a 172 very simple RAM test that quickly checks whether the SDRAM seems 173 to work correctly. It is not exhaustive but can save time by 174 detecting obvious failures. 175 176config MARK_GRAPHICS_MEM_WRCOMB 177 bool "Mark graphics memory as write-combining" 178 default n 179 help 180 The graphics performance may increase if the graphics 181 memory is set as write-combining cache type. This option 182 enables marking the graphics memory as write-combining. 183 184config HAVE_FSP 185 bool "Add an Firmware Support Package binary" 186 help 187 Select this option to add an Firmware Support Package binary to 188 the resulting U-Boot image. It is a binary blob which U-Boot uses 189 to set up SDRAM and other chipset specific initialization. 190 191 Note: Without this binary U-Boot will not be able to set up its 192 SDRAM so will not boot. 193 194config FSP_FILE 195 string "Firmware Support Package binary filename" 196 depends on HAVE_FSP 197 default "fsp.bin" 198 help 199 The filename of the file to use as Firmware Support Package binary 200 in the board directory. 201 202config FSP_ADDR 203 hex "Firmware Support Package binary location" 204 depends on HAVE_FSP 205 default 0xfffc0000 206 help 207 FSP is not Position Independent Code (PIC) and the whole FSP has to 208 be rebased if it is placed at a location which is different from the 209 perferred base address specified during the FSP build. Use Intel's 210 Binary Configuration Tool (BCT) to do the rebase. 211 212 The default base address of 0xfffc0000 indicates that the binary must 213 be located at offset 0xc0000 from the beginning of a 1MB flash device. 214 215config FSP_TEMP_RAM_ADDR 216 hex 217 depends on HAVE_FSP 218 default 0x2000000 219 help 220 Stack top address which is used in FspInit after DRAM is ready and 221 CAR is disabled. 222 223config MAX_CPUS 224 int "Maximum number of CPUs permitted" 225 default 4 226 help 227 When using multi-CPU chips it is possible for U-Boot to start up 228 more than one CPU. The stack memory used by all of these CPUs is 229 pre-allocated so at present U-Boot wants to know the maximum 230 number of CPUs that may be present. Set this to at least as high 231 as the number of CPUs in your system (it uses about 4KB of RAM for 232 each CPU). 233 234config SMP 235 bool "Enable Symmetric Multiprocessing" 236 default n 237 help 238 Enable use of more than one CPU in U-Boot and the Operating System 239 when loaded. Each CPU will be started up and information can be 240 obtained using the 'cpu' command. If this option is disabled, then 241 only one CPU will be enabled regardless of the number of CPUs 242 available. 243 244config AP_STACK_SIZE 245 hex 246 default 0x1000 247 help 248 Each additional CPU started by U-Boot requires its own stack. This 249 option sets the stack size used by each CPU and directly affects 250 the memory used by this initialisation process. Typically 4KB is 251 enough space. 252 253config TSC_CALIBRATION_BYPASS 254 bool "Bypass Time-Stamp Counter (TSC) calibration" 255 default n 256 help 257 By default U-Boot automatically calibrates Time-Stamp Counter (TSC) 258 running frequency via Model-Specific Register (MSR) and Programmable 259 Interval Timer (PIT). If the calibration does not work on your board, 260 select this option and provide a hardcoded TSC running frequency with 261 CONFIG_TSC_FREQ_IN_MHZ below. 262 263 Normally this option should be turned on in a simulation environment 264 like qemu. 265 266config TSC_FREQ_IN_MHZ 267 int "Time-Stamp Counter (TSC) running frequency in MHz" 268 depends on TSC_CALIBRATION_BYPASS 269 default 1000 270 help 271 The running frequency in MHz of Time-Stamp Counter (TSC). 272 273menu "System tables" 274 275config GENERATE_PIRQ_TABLE 276 bool "Generate a PIRQ table" 277 default n 278 help 279 Generate a PIRQ routing table for this board. The PIRQ routing table 280 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff 281 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR"). 282 It specifies the interrupt router information as well how all the PCI 283 devices' interrupt pins are wired to PIRQs. 284 285config GENERATE_SFI_TABLE 286 bool "Generate a SFI (Simple Firmware Interface) table" 287 help 288 The Simple Firmware Interface (SFI) provides a lightweight method 289 for platform firmware to pass information to the operating system 290 via static tables in memory. Kernel SFI support is required to 291 boot on SFI-only platforms. If you have ACPI tables then these are 292 used instead. 293 294 U-Boot writes this table in write_sfi_table() just before booting 295 the OS. 296 297 For more information, see http://simplefirmware.org 298 299endmenu 300 301config MAX_PIRQ_LINKS 302 int 303 default 8 304 help 305 This variable specifies the number of PIRQ interrupt links which are 306 routable. On most older chipsets, this is 4, PIRQA through PIRQD. 307 Some newer chipsets offer more than four links, commonly up to PIRQH. 308 309config IRQ_SLOT_COUNT 310 int 311 default 128 312 help 313 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table 314 which in turns forms a table of exact 4KiB. The default value 128 315 should be enough for most boards. If this does not fit your board, 316 change it according to your needs. 317 318config PCIE_ECAM_BASE 319 hex 320 default 0xe0000000 321 help 322 This is the memory-mapped address of PCI configuration space, which 323 is only available through the Enhanced Configuration Access 324 Mechanism (ECAM) with PCI Express. It can be set up almost 325 anywhere. Before it is set up, it is possible to access PCI 326 configuration space through I/O access, but memory access is more 327 convenient. Using this, PCI can be scanned and configured. This 328 should be set to a region that does not conflict with memory 329 assigned to PCI devices - i.e. the memory and prefetch regions, as 330 passed to pci_set_region(). 331 332endmenu 333